Bio

I am a PhD student interested in more productive methods for creating FPGA designs and ASICs for the datacenter.

Contact

Additional Info

  • Mail Code: 9025

Links

All Publications

  • Fleet: A Framework for Massively Parallel Streaming on FPGAs Thomas, J., Hanrahan, P., Zaharia, M., ACM ASSOC COMPUTING MACHINERY. 2020: 639–51

    View details for DOI 10.1145/3373376.3378495

    View details for Web of Science ID 000541369300041

  • Creating an Agile Hardware Design Flow Bahr, R., Barrett, C., Bhagdikar, N., Carsello, A., Daly, R., Donovick, C., Durst, D., Fatahalian, K., Feng, K., Hanrahan, P., Hofstee, T., Horowitz, M., Huff, D., Kjolstad, F., Kong, T., Liu, Q., Mann, M., Melchert, J., Nayak, A., Niemetz, A., Nyengele, G., Raina, P., Richardson, S., Setaluri, R., Setter, J., Sreedhar, K., Strange, M., Thomas, J., Torng, C., Truong, L., Tsiskaridze, N., Zhang, K., IEEE IEEE. 2020

    View details for Web of Science ID 000628528400063

  • TASO: Optimizing Deep Learning Computation with Automatic Generation of Graph Substitutions Jia, Z., Padon, O., Thomas, J., Warszawski, T., Zaharia, M., Aiken, A., ACM ASSOC COMPUTING MACHINERY. 2019: 47–62

    View details for DOI 10.1145/3341301.3359630

    View details for Web of Science ID 000524218600004