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AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers
ACM Transactions on Embedded Computing Systems
2023; 22 (2)
View details for DOI 10.1145/3534933
Creating an Agile Hardware Design Flow
View details for Web of Science ID 000628528400063
Optimized Gateway Placement for Interference Cancellation in Transmit-Only LPWA Networks.
Sensors (Basel, Switzerland)
2018; 18 (11)
We study the placement of gateways in a low-power wide-area sensor network, when the gateways perform interference cancellation and when the model of the residual error of interference cancellation is proportional to the power of the packet being canceled. For the case of two sensor nodes sending packets that collide, by which we mean overlap in time, we deduce a symmetric two-crescent region wherein a gateway can decode both collided packets. For a large network of many sensors and multiple gateways, we propose two greedy algorithms to optimize the locations of the gateways. Simulation results show that the gateway placements by our algorithms achieve lower average contention, which means higher packet delivery ratio in the same conditions, than when gateways are naively placed, for several area distributions of sensors.
View details for PubMedID 30423893