Bio

I’m an EE PhD candidate at Stanford University supervised by Prof. H.-S. Philip Wong. My current research interests focus on in-memory computing enabled by emerging memory technologies (e.g., 3D vertical RRAM), with technical efforts spanning from device characterization and cross-stack modeling, to efficient architectures and their hardware realizations.

Published more than 30 papers appearing in top conferences (IEDM, ISSCC, VLSI, DAC) and journals (JSSC, Nature Electronics), including several invited papers. Our research has been featured on EE Times, Forbes, Storage Newsletter, Stanford News, ScienceNet, and PKU News. Meanwhile, I serve as an active reviewer for JSSC, Scientific Reports, EDL, T-ED, Applied Physics Letters, T-CAD, T-VLSI, and several IEEE conferences.

I’m a recipient of 2016 IEEE EDS Masters Student Fellowship, Best Paper Award at 2016 SRC TECHCON, ‘Golden List of Reviewers’ by IEEE EDL and T-ED, and nomination for Best Student Paper Award at 2016 Symposium of VLSI Technology.

Homepage: https://web.stanford.edu/~haitongl

Links

All Publications

  • Device and materials requirements for neuromorphic computing JOURNAL OF PHYSICS D-APPLIED PHYSICS Islam, R., Li, H., Chen, P., Wan, W., Chen, H., Gao, B., Wu, H., Yu, S., Saraswat, K., Wong, H. 2019; 52 (11)

    View details for DOI 10.1088/1361-6463/aaf784

    View details for Web of Science ID 000456266700001

  • Ternary content-addressable memory with MoS2 transistors for massively parallel data search NATURE ELECTRONICS Yang, R., Li, H., Smithe, K. H., Kim, T. R., Okabe, K., Pop, E., Fan, J. A., Wong, H. 2019; 2 (3): 108–14

    View details for DOI 10.1038/s41928-019-0220-7

    View details for Web of Science ID 000463819800010

  • A 43pJ/Cycle Non-Volatile Microcontroller with 4.7 mu s Shutdown/Wake-up Integrating 2.3-bit/Cell Resistive RAM and Resilience Techniques Wu, T. F., Le, B. Q., Radway, R., Bartolo, A., Hwang, W., Jeong, S., Li, H., Tandon, P., Vianello, E., Vivet, P., Nowak, E., Wootters, M. K., Wong, H., Aly, M., Beigne, E., Mitra, S., Fujino, L. C., Anderson, J. H., Belostotski, L., Dunwell, D., Gaudet, Gulak, G., Haslett, J. W., Halupka, D., Smith, K. C. IEEE. 2019: 226-+

    View details for Web of Science ID 000463153600071

  • On-Chip Memory Technology Design Space Explorations for Mobile Deep Neural Network Accelerators Li, H., Bhargava, M., Whatmough, P. N., Wong, H., ACM ASSOC COMPUTING MACHINERY. 2019

    View details for DOI 10.1145/3316781.3317874

    View details for Web of Science ID 000482058200131

  • Recommended Methods to Study Resistive Switching Devices ADVANCED ELECTRONIC MATERIALS Lanza, M., Wong, H., Pop, E., Ielmini, D., Strukov, D., Regan, B. C., Larcher, L., Villena, M. A., Yang, J., Goux, L., Belmonte, A., Yang, Y., Puglisi, F. M., Kang, J., Magyari-Kope, B., Yalon, E., Kenyon, A., Buckwell, M., Mehonic, A., Shluger, A., Li, H., Hou, T., Hudec, B., Akinwande, D., Ge, R., Ambrogio, S., Roldan, J. B., Miranda, E., Sune, J., Pey, K., Wu, X., Raghavan, N., Wu, E., Lu, W. D., Navarro, G., Zhang, W., Wu, H., Li, R., Holleitner, A., Wurstbauer, U., Lemme, M. C., Liu, M., Long, S., Liu, Q., Lv, H., Padovani, A., Pavan, P., Valov, I., Jing, X., Han, T., Zhu, K., Chen, S., Hui, F., Shi, Y. 2019; 5 (1)

    View details for DOI 10.1002/aelm.201800143

    View details for Web of Science ID 000455220900021

  • Hyperdimensional Computing Exploiting Carbon Nanotube FETs, Resistive RAM, and Their Monolithic 3D Integration IEEE JOURNAL OF SOLID-STATE CIRCUITS Wu, T. F., Li, H., Huang, P., Rahimi, A., Hills, G., Hodson, B., Hwang, W., Rabaey, J. M., Wong, H., Shulaker, M. M., Mitra, S. 2018; 53 (11): 3183–96

    View details for DOI 10.1109/JSSC.2018.2870560

    View details for Web of Science ID 000449108400016

  • Electronic synapses made of layered two-dimensional materials NATURE ELECTRONICS Shi, Y., Liang, X., Yuan, B., Chen, V., Li, H., Hui, F., Yu, Z., Yuan, F., Pop, E., Wong, H., Lanza, M. 2018; 1 (8): 458–65

    View details for DOI 10.1038/s41928-018-0118-9

    View details for Web of Science ID 000444080500012

  • Selector Requirements for Tera-Bit Ultra-High-Density 3D Vertical RRAM Jiang, Z., Qin, S., Li, H., Fujii, S., Lee, D., Wong, S., Wong, H., IEEE IEEE. 2018: 107–8

    View details for Web of Science ID 000465075200039

  • Brain-Inspired Computing Exploiting Carbon Nanotube FETs and Resistive RAM: Hyperdimensional Computing Case Study Wu, T. F., Li, H., Huang, P., Rahimi, A., Rabaey, J. M., Wong, H., Shulaker, M. M., Mitra, S., IEEE IEEE. 2018: 492-+

    View details for Web of Science ID 000459205600205

  • First Principles Study of Memory Selectors using Heterojunctions of 2D Layered Materials Li, L., Magyari-Kope, B., Wang, C., Deshmukh, S., Jiang, Z., Li, H., Yang, Y., Li, H., Tian, H., Pop, E., Ren, T., Wong, H., IEEE IEEE. 2018

    View details for Web of Science ID 000459882300229

  • Brain-Inspired Computing Exploiting Carbon Nanotube FETs and Resistive RAM: Hyperdimensional Computing Case Study Wu, T. F., Li, H., Huang, P., Rahimi, A., Rabaey, J. M., Wong, H., Shulaker, M. M., Mitra, S., IEEE IEEE. 2018

    View details for Web of Science ID 000432256300204

  • Device and Circuit Interaction Analysis of Stochastic Behaviors in Cross-Point RRAM Arrays IEEE TRANSACTIONS ON ELECTRON DEVICES Li, H., Huang, P., Gao, B., Liu, X., Kang, J., Wong, H. 2017; 64 (12): 4928–36

    View details for DOI 10.1109/TED.2017.2766046

    View details for Web of Science ID 000417727500017

  • 2D Molybdenum Disulfide (MoS2) Transistors Driving RRAMs with 1T1R Configuration Yang, R., Li, H., Smithe, K. H., Kim, T. R., Okabe, K., Pop, E., Fan, J. A., Wong, H., IEEE IEEE. 2017

    View details for Web of Science ID 000424868900117

  • Design and Application of Oxide-Based Resistive Switching Devices for Novel Computing Architectures IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY Kang, J., Huang, P., Gao, B., Li, H., Chen, Z., Zhao, Y., Liu, C., Liu, L., Liu, X. 2016; 4 (5): 307-313

    View details for DOI 10.1109/JEDS.2016.2577051

    View details for Web of Science ID 000382676700015

  • Disturbance characteristics of half-selected cells in a cross-point resistive switching memory array NANOTECHNOLOGY Chen, Z., Li, H., Chen, H., Chen, B., Liu, R., Huang, P., Zhang, F., Jiang, Z., Ye, H., Gao, B., Liu, L., Liu, X., Kang, J., Wong, H. P., Yu, S. 2016; 27 (21)

    Abstract

    Disturbance characteristics of cross-point resistive random access memory (RRAM) arrays are comprehensively studied in this paper. An analytical model is developed to quantify the number of pulses (#Pulse) the cell can bear before disturbance occurs under various sub-switching voltage stresses based on physical understanding. An evaluation methodology is proposed to assess the disturb behavior of half-selected (HS) cells in cross-point RRAM arrays by combining the analytical model and SPICE simulation. The characteristics of cross-point RRAM arrays such as energy consumption, reliable operating cycles and total error bits are evaluated by the methodology. A possible solution to mitigate disturbance is proposed.

    View details for DOI 10.1088/0957-4484/27/21/215204

    View details for Web of Science ID 000374507600006

  • 3-D Resistive Memory Arrays: From Intrinsic Switching Behaviors to Optimization Guidelines IEEE TRANSACTIONS ON ELECTRON DEVICES Li, H., Gao, B., Chen, H. (., Chen, Z., Huang, P., Liu, R., Zhao, L., Jiang, Z. (., Liu, L., Liu, X., Yu, S., Kang, J., Nishi, Y., Wong, H. P. 2015; 62 (10): 3160-3167

    View details for DOI 10.1109/TED.2015.2468602

    View details for Web of Science ID 000361684000008

  • A learnable parallel processing architecture towards unity of memory and computing SCIENTIFIC REPORTS Li, H., Gao, B., Chen, Z., Zhao, Y., Huang, P., Ye, H., Liu, L., Liu, X., Kang, J. 2015; 5

    Abstract

    Developing energy-efficient parallel information processing systems beyond von Neumann architecture is a long-standing goal of modern information technologies. The widely used von Neumann computer architecture separates memory and computing units, which leads to energy-hungry data movement when computers work. In order to meet the need of efficient information processing for the data-driven applications such as big data and Internet of Things, an energy-efficient processing architecture beyond von Neumann is critical for the information society. Here we show a non-von Neumann architecture built of resistive switching (RS) devices named "iMemComp", where memory and logic are unified with single-type devices. Leveraging nonvolatile nature and structural parallelism of crossbar RS arrays, we have equipped "iMemComp" with capabilities of computing in parallel and learning user-defined logic functions for large-scale information processing tasks. Such architecture eliminates the energy-hungry data movement in von Neumann computers. Compared with contemporary silicon technology, adder circuits based on "iMemComp" can improve the speed by 76.8% and the power dissipation by 60.3%, together with a 700 times aggressive reduction in the circuit area.

    View details for DOI 10.1038/srep13330

    View details for Web of Science ID 000359464200001

    View details for PubMedID 26271243

  • Analysis of the Voltage-Time Dilemma of Metal Oxide-Based RRAM and Solution Exploration of High Speed and Low Voltage AC Switching IEEE TRANSACTIONS ON NANOTECHNOLOGY Huang, P., Wang, Y., Li, H., Gao, B., Chen, B., Zhang, F., Zeng, L., Du, G., Kang, J., Liu, X. 2014; 13 (6): 1127-1132

    View details for DOI 10.1109/TNANO.2014.2340571

    View details for Web of Science ID 000345087900015

  • A SPICE Model of Resistive Random Access Memory for Large-Scale Memory Array Simulation IEEE ELECTRON DEVICE LETTERS Li, H., Huang, P., Gao, B., Chen, B., Liu, X., Kang, J. 2014; 35 (2): 211-213

    View details for DOI 10.1109/LED.2013.2293354

    View details for Web of Science ID 000331377500021

  • Write Disturb Analyses on Half-Selected Cells of Cross-Point RRAM Arrays International Reliability Physics Symposium (IRPS) Li, H., Chen, H., Chen, Z., Chen, B., Liu, R., Qiu, G., Huang, P., Zhang, F., Jiang, Z., Gao, B., Liu, L., Liu, X., Yu, S., Wong, H. P., Kang, J. IEEE. 2014

    View details for Web of Science ID 000343833200160

  • Statistical Assessment Methodology for the Design and Optimization of Cross-Point RRAM Arrays IEEE 6th International Memory Workshop (IMW) Li, H., Jiang, Z., Huang, P., Chen, H., Chen, B., Liu, R., Chen, Z., Zhang, F., Liu, L., Gao, B., Liu, X., Yu, S., Wong, H. P., Kang, J. IEEE. 2014

    View details for Web of Science ID 000346141000008

  • Impact of Pulse Rise Time on Programming of Cross-Point RRAM Arrays PROCEEDINGS OF TECHNICAL PROGRAM - 2014 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATION (VLSI-TSA) Liu, R., Chen, H., Li, H., Huang, P., Zhao, L., Chen, Z., Zhang, F., Chen, B., Liu, L., Liu, X., Gao, B., Yu, S., Nishi, Y., Wong, H. P., Kang, J. 2014

    View details for Web of Science ID 000358865800050

  • Parameters Extraction on HfOX based RRAM PROCEEDINGS OF THE 2014 44TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE (ESSDERC 2014) Huang, P., Chen, B., Li, H., Chen, Z., Gao, B., Liu, X., Kang, J. 2014: 250-253

    View details for Web of Science ID 000348858100059

  • A Physics-Based Compact Model of Metal-Oxide-Based RRAM DC and AC Operations IEEE TRANSACTIONS ON ELECTRON DEVICES Huang, P., Liu, X. Y., Chen, B., Li, H. T., Wang, Y. J., Deng, Y. X., Wei, K. L., Zeng, L., Gao, B., Du, G., Zhang, X., Kang, J. F. 2013; 60 (12): 4090-4097

    View details for DOI 10.1109/TED.2013.2287755

    View details for Web of Science ID 000327584400018