Bio

Jeff is a Ph.D. candidate at Stanford University in Electrical Engineering advised by Mark Horowitz. His research interests are in building hardware accelerators from software languages. Halide to Hardware is a project to use a data-parallel functional program formerly developed for CPU programs to produce hardware. Through the AHA hardware toolflow, these image processing and deep learning algorithms are mapped to a CGRA. Previously, Jeff received a B.S. in Electrical and Computer Engineering from Cornell University in 2015.

Contact

  • Academic
    setter@stanford.edu
    University - Student Department: Electrical Engineering Position: Graduate

Additional Info

  • Mail Code: 9505

All Publications

  • Amber: A 16-nm System-on-Chip With a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra IEEE JOURNAL OF SOLID-STATE CIRCUITS Feng, K., Kong, T., Koul, K., Melchert, J., Carsello, A., Liu, Q., Nyengele, G., Strange, M., Zhang, K., Nayak, A., Setter, J., Thomas, J., Sreedhar, K., Chen, P., Bhagdikar, N., Myers, Z. A., D'Agostino, B., Joshi, P., Richardson, S., Torng, C., Horowitz, M., Raina, P. 2023

    View details for DOI 10.1109/JSSC.2023.3313116

    View details for Web of Science ID 001078350700001

  • AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers ACM Transactions on Embedded Computing Systems Koul, K., Melchert, J., Sreedhar, K., Truong, L., Nyengele, G., Zhang, K., Liu, Q., Setter, J., Chen, P., Mei, Y., Strange, M., Daly, R., Donovick, C., Carsello, A., Kong, T., Feng, K., Huff, D., Nayak, A., Setaluri, R., Thomas, J., Bhagdikar, N., Durst, D., Myers, Z., Tsiskaridze, N., Richardson, S., et al 2023; 22 (2)

    View details for DOI 10.1145/3534933

  • Unified Buffer: Compiling Image Processing and Machine Learning Applications to Push-Memory Accelerators ACM Transactions on Architecture and Code Optimization Liu, Q., Setter, J., Huff, D., Strange, M., Feng, K., Horowitz, M., Raina, P., Kjolstad, F. 2022: 26

    View details for DOI 10.1145/3572908

  • Interstellar: Using Halide's Scheduling Language to Analyze DNN Accelerators Yang, X., Gao, M., Liu, Q., Setter, J., Pu, J., Nayak, A., Bell, S., Cao, K., Ha, H., Raina, P., Kozyrakis, C., Horowitz, M., ACM ASSOC COMPUTING MACHINERY. 2020: 369–83

    View details for DOI 10.1145/3373376.3378514

    View details for Web of Science ID 000541369300024

  • Creating an Agile Hardware Design Flow Bahr, R., Barrett, C., Bhagdikar, N., Carsello, A., Daly, R., Donovick, C., Durst, D., Fatahalian, K., Feng, K., Hanrahan, P., Hofstee, T., Horowitz, M., Huff, D., Kjolstad, F., Kong, T., Liu, Q., Mann, M., Melchert, J., Nayak, A., Niemetz, A., Nyengele, G., Raina, P., Richardson, S., Setaluri, R., Setter, J., Sreedhar, K., Strange, M., Thomas, J., Torng, C., Truong, L., Tsiskaridze, N., Zhang, K., IEEE IEEE. 2020

    View details for Web of Science ID 000628528400063

  • Programming Heterogeneous Systems from an Image Processing DSL ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION Pu, J., Bell, S., Yang, X., Setter, J., Richardson, S., Ragan-Kelley, J., Horowitz, M. 2017; 14 (3)

    View details for DOI 10.1145/3107953

    View details for Web of Science ID 000423744000006