
Jeff Setter
Ph.D. Student in Electrical Engineering, admitted Autumn 2015
Bio
Jeff is a Ph.D. candidate at Stanford University in Electrical Engineering advised by Mark Horowitz. His research interests are in building hardware accelerators from software languages. Halide to Hardware is a project to use a data-parallel functional program formerly developed for CPU programs to produce hardware. Through the AHA hardware toolflow, these image processing and deep learning algorithms are mapped to a CGRA. Previously, Jeff received a B.S. in Electrical and Computer Engineering from Cornell University in 2015.
All Publications
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Amber: A 16-nm System-on-Chip With a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra
IEEE JOURNAL OF SOLID-STATE CIRCUITS
2023
View details for DOI 10.1109/JSSC.2023.3313116
View details for Web of Science ID 001078350700001
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AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers
ACM Transactions on Embedded Computing Systems
2023; 22 (2)
View details for DOI 10.1145/3534933
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Unified Buffer: Compiling Image Processing and Machine Learning Applications to Push-Memory Accelerators
ACM Transactions on Architecture and Code Optimization
2022: 26
View details for DOI 10.1145/3572908
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Interstellar: Using Halide's Scheduling Language to Analyze DNN Accelerators
ASSOC COMPUTING MACHINERY. 2020: 369–83
View details for DOI 10.1145/3373376.3378514
View details for Web of Science ID 000541369300024
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Creating an Agile Hardware Design Flow
IEEE. 2020
View details for Web of Science ID 000628528400063
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Programming Heterogeneous Systems from an Image Processing DSL
ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION
2017; 14 (3)
View details for DOI 10.1145/3107953
View details for Web of Science ID 000423744000006