
Qiaoyi (Joey) Liu
Ph.D. Student in Electrical Engineering, admitted Autumn 2017
Bio
Qiaoyi(Joey) is a PhD student advised by Mark Horowitz. He is working on agile hardware design methodology, generating computer vision hardware from domain specific language, Halide. His research interests include energy efficient system design, compiler and domain-specific architecture.
Education & Certifications
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M.S., Stanford University, Electrical Engineering (2020)
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B.S., Tsinghua University, Electronic Engineering (2017)
All Publications
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AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers
ACM Transactions on Embedded Computing Systems
2023; 22 (2)
View details for DOI 10.1145/3534933
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Amber: A 367 GOPS, 538 GOPS/W 16nm SoC with a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
2022
View details for DOI 10.1109/VLSITechnologyandCir46769.2022.9830509
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Unified Buffer: Compiling Image Processing and Machine Learning Applications to Push-Memory Accelerators
ACM Transactions on Architecture and Code Optimization
2022: 26
View details for DOI 10.1145/3572908
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Interstellar: Using Halide's Scheduling Language to Analyze DNN Accelerators
ASSOC COMPUTING MACHINERY. 2020: 369–83
View details for DOI 10.1145/3373376.3378514
View details for Web of Science ID 000541369300024
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Creating an Agile Hardware Design Flow
IEEE. 2020
View details for Web of Science ID 000628528400063