Bio

Qiaoyi(Joey) is a PhD student advised by Mark Horowitz. He is working on agile hardware design methodology, generating computer vision hardware from domain specific language, Halide. His research interests include energy efficient system design, compiler and domain-specific architecture.

Education & Certifications

  • M.S., Stanford University, Electrical Engineering (2020)
  • B.S., Tsinghua University, Electronic Engineering (2017)

Contact

  • Academic
    University - Student Department: Electrical Engineering Position: Graduate

Additional Info

  • Mail Code: 9505

Links

All Publications

  • AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers ACM Transactions on Embedded Computing Systems Koul, K., Melchert, J., Sreedhar, K., Truong, L., Nyengele, G., Zhang, K., Liu, Q., Setter, J., Chen, P., Mei, Y., Strange, M., Daly, R., Donovick, C., Carsello, A., Kong, T., Feng, K., Huff, D., Nayak, A., Setaluri, R., Thomas, J., Bhagdikar, N., Durst, D., Myers, Z., Tsiskaridze, N., Richardson, S., et al 2023; 22 (2)

    View details for DOI 10.1145/3534933

  • Amber: A 367 GOPS, 538 GOPS/W 16nm SoC with a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Carsello, A., et al 2022

    View details for DOI 10.1109/VLSITechnologyandCir46769.2022.9830509

  • Unified Buffer: Compiling Image Processing and Machine Learning Applications to Push-Memory Accelerators ACM Transactions on Architecture and Code Optimization Liu, Q., Setter, J., Huff, D., Strange, M., Feng, K., Horowitz, M., Raina, P., Kjolstad, F. 2022: 26

    View details for DOI 10.1145/3572908

  • Interstellar: Using Halide's Scheduling Language to Analyze DNN Accelerators Yang, X., Gao, M., Liu, Q., Setter, J., Pu, J., Nayak, A., Bell, S., Cao, K., Ha, H., Raina, P., Kozyrakis, C., Horowitz, M., ACM ASSOC COMPUTING MACHINERY. 2020: 369–83

    View details for DOI 10.1145/3373376.3378514

    View details for Web of Science ID 000541369300024

  • Creating an Agile Hardware Design Flow Bahr, R., Barrett, C., Bhagdikar, N., Carsello, A., Daly, R., Donovick, C., Durst, D., Fatahalian, K., Feng, K., Hanrahan, P., Hofstee, T., Horowitz, M., Huff, D., Kjolstad, F., Kong, T., Liu, Q., Mann, M., Melchert, J., Nayak, A., Niemetz, A., Nyengele, G., Raina, P., Richardson, S., Setaluri, R., Setter, J., Sreedhar, K., Strange, M., Thomas, J., Torng, C., Truong, L., Tsiskaridze, N., Zhang, K., IEEE IEEE. 2020

    View details for Web of Science ID 000628528400063