All Publications


  • Low-Temperature Side Contact to Carbon Nanotube Transistors: Resistance Distributions Down to 10 nm Contact Length NANO LETTERS Pitner, G., Hills, G., Llinas, J., Persson, K., Park, R., Bokor, J., Mitra, S., Wong, H. 2019; 19 (2): 1083–89

    Abstract

    Carbon nanotube field-effect transistors (CNFETs) promise to improve the energy efficiency, speed, and transistor density of very large scale integration circuits owing to the intrinsic thin channel body and excellent charge transport properties of carbon nanotubes. Low-temperature fabrication (e.g., <400 °C) is a key enabler for the monolithic three-dimensional (3D) integration of CNFET digital logic into a device technology platform that overcomes memory bandwidth bottlenecks for data-abundant applications such as big-data analytics and machine learning. However, high contact resistance for short CNFET contacts has been a major roadblock to establishing CNFETs as a viable technology because the contact resistance, in series with the channel resistance, reduces the on-state current of CNFETs. Additionally, the variation in contact resistance remains unstudied for short contacts and will further degrade the energy efficiency and speed of CNFET circuits. In this work, we investigate by experiments the contact resistance and statistical variation of room-temperature fabricated CNFET contacts down to 10 nm contact lengths. These CNFET contacts are ∼15 nm shorter than the state-of-the-art Si CMOS "7 nm node" contact length, allowing for multiple generations of future scaling of the transistor-contacted gate pitch. For the 10 nm contacts, we report contact resistance values down to 6.5 kΩ per source/drain contact for a single carbon nanotube (CNT) with a median contact resistance of 18.2 kΩ. The 10 nm contacts reduce the CNFET current by as little as 13% at VDS = 0.7 V compared with the best reported 200 nm contacts to date, corroborated by results in this work. Our analysis of RC from 232 single-CNT CNFETs between the long-contact (e.g., 200 nm) and short-contact (e.g., 10 nm) regimes quantifies the resistance variation and projects the impact on CNFET current variability versus the number of CNT in the transistor. The resistance distribution reveals contact-length-dependent RC variations become significant below 20 nm contact length. However, a larger source of CNFET resistance variation is apparent at all contact lengths used in this work. To further investigate the origins of this contact-length-independent resistance variation, we analyze the variation of RC in arrays of identical CNFETs along a single CNT of constant diameter and observe the random occurrence of high  RC, even on correlated CNFETs.

    View details for DOI 10.1021/acs.nanolett.8b04370

    View details for Web of Science ID 000459222300060

    View details for PubMedID 30677297

  • Negative Capacitance Carbon Nanotube FETs IEEE ELECTRON DEVICE LETTERS Srimani, T., Hills, G., Bishop, M. D., Radhakrishna, U., Zubair, A., Park, R. S., Stein, Y., Palacios, T., Antoniadis, D., Shulaker, M. M. 2018; 39 (2): 304–7
  • TRIG: Hardware Accelerator for Inference-Based Applications and Experimental Demonstration Using Carbon Nanotube FETs Hills, G., Bankman, D., Moons, B., Yang, L., Hillard, J., Kahng, A., Park, R., Verhelst, M., Murmann, B., Shulaker, M. M., Wong, H., Mitra, S., IEEE IEEE. 2018
  • Three-dimensional integration of nanotechnologies for computing and data storage on a single chip NATURE Shulaker, M. M., Hills, G., Park, R. S., Howe, R. T., Saraswat, K., Wong, H., Mitra, S. 2017; 547 (7661): 74-+

    Abstract

    The computing demands of future data-intensive applications will greatly exceed the capabilities of current electronics, and are unlikely to be met by isolated improvements in transistors, data storage technologies or integrated circuit architectures alone. Instead, transformative nanosystems, which use new nanotechnologies to simultaneously realize improved devices and new integrated circuit architectures, are required. Here we present a prototype of such a transformative nanosystem. It consists of more than one million resistive random-access memory cells and more than two million carbon-nanotube field-effect transistors-promising new nanotechnologies for use in energy-efficient digital logic circuits and for dense data storage-fabricated on vertically stacked layers in a single chip. Unlike conventional integrated circuit architectures, the layered fabrication realizes a three-dimensional integrated circuit architecture with fine-grained and dense vertical connectivity between layers of computing, data storage, and input and output (in this instance, sensing). As a result, our nanosystem can capture massive amounts of data every second, store it directly on-chip, perform in situ processing of the captured data, and produce 'highly processed' information. As a working prototype, our nanosystem senses and classifies ambient gases. Furthermore, because the layers are fabricated on top of silicon logic circuitry, our nanosystem is compatible with existing infrastructure for silicon-based technologies. Such complex nano-electronic systems will be essential for future high-performance and highly energy-efficient electronic systems.

    View details for PubMedID 28682331

  • Hysteresis-Free Carbon Nanotube Field-Effect Transistors. ACS nano Park, R. S., Hills, G., Sohn, J., Mitra, S., Shulaker, M. M., Wong, H. P. 2017; 11 (5): 4785-4791

    Abstract

    While carbon nanotube (CNT) field-effect transistors (CNFETs) promise high-performance and energy-efficient digital systems, large hysteresis degrades these potential CNFET benefits. As hysteresis is caused by traps surrounding the CNTs, previous works have shown that clean interfaces that are free of traps are important to minimize hysteresis. Our previous findings on the sources and physics of hysteresis in CNFETs enabled us to understand the influence of gate dielectric scaling on hysteresis. To begin with, we validate through simulations how scaling the gate dielectric thickness results in greater-than-expected benefits in reducing hysteresis. Leveraging this insight, we experimentally demonstrate reducing hysteresis to <0.5% of the gate-source voltage sweep range using a very large-scale integration compatible and solid-state technology, simply by fabricating CNFETs with a thin effective oxide thickness of 1.6 nm. However, even with negligible hysteresis, large subthreshold swing is still observed in the CNFETs with multiple CNTs per transistor. We show that the cause of large subthreshold swing is due to threshold voltage variation between individual CNTs. We also show that the source of this threshold voltage variation is not explained solely by variations in CNT diameters (as is often ascribed). Rather, other factors unrelated to the CNTs themselves (i.e., process variations, random fixed charges at interfaces) are a significant factor in CNT threshold voltage variations and thus need to be further improved.

    View details for DOI 10.1021/acsnano.7b01164

    View details for PubMedID 28463503

  • Hysteresis in Carbon Nanotube Transistors: Measurement and Analysis of Trap Density, Energy Level, and Spatial Distribution ACS NANO Park, R. S., Shulaker, M. M., Hills, G., Liyanage, L. S., Lee, S., Tang, A., Mitra, S., Wong, H. P. 2016; 10 (4): 4599-4608

    Abstract

    We present a measurement technique, which we call the Pulsed Time-Domain Measurement, for characterizing hysteresis in carbon nanotube field-effect transistors, and demonstrate its applicability for a broad range of 1D and 2D nanomaterials beyond carbon nanotubes. The Pulsed Time-Domain Measurement enables the quantification (density, energy level, and spatial distribution) of charged traps responsible for hysteresis. A physics-based model of the charge trapping process for a carbon nanotube field-effect transistor is presented and experimentally validated using the Pulsed Time-Domain Measurement. Leveraging this model, we discover a source of traps (surface traps) unique to devices with low-dimensional channels such as carbon nanotubes and nanowires (beyond interface traps which exist in today's silicon field-effect transistors). The different charge trapping mechanisms for interface traps and surface traps are studied based on their temperature dependencies. Through these advances, we are able to quantify the interface trap density for carbon nanotube field-effect transistors (∼3 × 10(13) cm(-2) eV(-1) near midgap), and compare this against a range of previously studied dielectric/semiconductor interfaces.

    View details for DOI 10.1021/acsnano.6b00792

    View details for PubMedID 27002483