All Publications


  • A novel hardmask-to-substrate pattern transfer method for creating 3D, multi-level, hierarchical, high aspect-ratio structures for applications in microfluidics and cooling technologies. Scientific reports Hazra, S., Zhang, C., Wu, Q., Asheghi, M., Goodson, K., Dede, E. M., Palko, J., Narumanchi, S. 2022; 12 (1): 12180

    Abstract

    This letter solves a major hurdle that mars photolithography-based fabrication of micro-mesoscale structures in silicon. Conventional photolithography is usually performed on smooth, flat wafer surfaces to lay a 2D design and subsequently etch it to create single-level features. It is, however, unable to process non-flat surfaces or already etched wafers and create more than one level in the structure. In this study, we have described a novel cleanroom-based process flow that allows for easy creation of such multi-level, hierarchical 3D structures in a substrate. This is achieved by introducing an ultra-thin sacrificial silicon dioxide hardmask layer on the substrate which is first 3D patterned via multiple rounds of lithography. This 3D pattern is then scaled vertically by a factor of 200-300 and transferred to the substrate underneath via a single shot deep etching step. The proposed method is also easily characterizable-using features of different topographies and dimensions, the etch rates and selectivities were quantified; this characterization information was later used while fabricating specific target structures. Furthermore, this study comprehensively compares the novel pattern transfer technique to already existing methods of creating multi-level structures, like grayscale lithography and chip stacking. The proposed process was found to be cheaper, faster, and easier to standardize compared to other methods-this made the overall process more reliable and repeatable. We hope it will encourage more research into hybrid structures that hold the key to dramatic performance improvements in several micro-mesoscale devices.

    View details for DOI 10.1038/s41598-022-16281-5

    View details for PubMedID 35842450

  • Thermal and Manufacturing Design Considerations for Silicon-Based Embedded Microchannel Three-Dimensional-Manifold Coolers (EMMC)-Part 3: Addressing Challenges in Laser Micromachining-Based Manufacturing of Three-Dimensional-Manifolded Microcooler Devices Hazra, S., Jung, K., Iyengar, M., Malone, C., Asheghi, M., Goodson, K. E. ASME. 2020

    View details for DOI 10.1115/1.4047847

    View details for Web of Science ID 000576282500020

  • Thermal and Manufacturing Design Considerations for Silicon-Based Embedded Microchannel-Three-Dimensional Manifold Coolers-Part 2: Parametric Study of EMMCs for High Heat Flux (similar to 1kW/cm(2)) Power Electronics Cooling Jung, K., Hazra, S., Kwon, H., Piazza, A., Jih, E., Asheghi, M., Gupta, M., Degner, M., Goodson, K. E. ASME. 2020

    View details for DOI 10.1115/1.4047883

    View details for Web of Science ID 000576282500019

  • ADDRESSING THE CHALLENGES IN LASER MICRO-MACHINING AND BONDING OF SILICON MICROCHANNEL COLD-PLATE AND 3D-MANIFOLD FOR EMBEDDED COOLING APPLICATIONS: PERFECT DEBRIS REMOVAL Hazra, S., Jung, K., Lyengar, M., Malone, C., Asheghi, M., Goodson, K. E., ASME AMER SOC MECHANICAL ENGINEERS. 2020
  • Considerations and Challenges for Large Area Embedded Micro-channels with 3D Manifold in High Heat Flux Power Electronics Applications Piazza, A., Hazra, S., Jung, K., Degner, M., Gupta, M., Jih, E., Asheghi, M., Goodson, K. E., IEEE IEEE. 2020: 77-82
  • Microfabrication Challenges for Silicon-based Large Area (> 500 mm(2)) 3D-manifolded Embedded Microcooler Devices for High Heat Flux Removal Hazra, S., Piazza, A., Jung, K., Asheghi, M., Gupta, M., Jih, E., Degner, M., Goodson, K. E., IEEE IEEE. 2020: 83-90