Steven Herbst is working to speed up the chip design process through research in FPGA emulation of mixed-signal circuits. Current work includes an open-source framework for emulating chip designs, a Python-based generator that produces synthesizable models of analog/mixed-signal blocks, and a SystemVerilog library for conveniently working with fixed-point numbers. Previous research includes methods to accelerate emulations of high-speed link designs. Prior to starting the PhD program at Stanford, he was an engineer at Apple (2013-2016) and Intersil (2011-2013). Steven holds B.S. and M.Eng. degrees in EE from MIT (2010, 2011).