Bio


Athanasios Ramkaj (S’16) received the B.Sc. degree in physics (electronics specialization) from Aristotle University of Thessaloniki, Thessaloniki, Greece, the M.Sc. degree (cum laude) in electrical engineering (microelectronics) from TU Delft, Delft, The Netherlands, and the Ph.D. degree (summa cum laude) in electrical engineering from KU Leuven, Leuven, Belgium, in 2012, 2014, and 2021, respectively. His Ph.D. research was in the field of Multi-GHz Bandwidth Power-Efficient Nyquist A/D Conversion, supervised by Prof. Dr. Ir. Filip Tavernier, Prof. Dr. Ir. Michiel Steyaert and Dr. Ir. Marcel Pelgrom. He is currently a postdoctoral research fellow with the Murmann Mixed-Signal Group, Stanford University, Stanford, CA, USA, in the field of high-performance ultra-low jitter ADCs.

From 2013 to 2014, he was a research intern with the Central Research & Development Department, NXP Semiconductors, Eindhoven, The Netherlands, where he worked in the modeling of different DACs and the design of GHz-range ADCs for communications applications. In 2019, he was a research/design intern with the High-Speed Data Converters Group, Analog Devices Inc., Wilmington, MA, USA, investigating highly integrated solutions for bandwidth extension of next-generation RF ADCs.

Dr. Ramkaj was the recipient of the 2021 Analog Devices Outstanding Student Designer Award, the 2019-2020 IEEE Solid-State Circuits Society Predoctoral Achievement Award, and the 2015 IEEE PRIME Golden Leaf Best Student Paper Award. He also serves as a reviewer for the IEEE Journal of Solid-State Circuits (JSSC), IEEE Transactions on Very Large Scale Integration Systems (TVLSI), IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), MDPI Journal Electronics, and IEEE International Symposium on Circuits & Systems (ISCAS).

Honors & Awards


  • PhD Summa Cum Laude Distinction, KU Leuven - Faculty of Engineering Science (March 2021)
  • 2021 ADI Outstanding Student Designer Award, Analog Devices Inc. (Feb 2021)
  • 2019-2020 IEEE SSCS Predoctoral Achievement Award, IEEE Solid-State Circuits Society (SSCS) (Dec 2019)
  • Golden Leaf Student Paper Award @ IEEE PRIME 2015, IEEE Society (June 2015)

Professional Education


  • Doctor of Philosophy, Katholieke Universiteit Leuven (2021)
  • Master of Science, Technische Universiteit Delft (2021)
  • Bachelor of Science, Arist. University Of Thessaloniki (2012)
  • Ph.D., KU Leuven, Faculty of Engineering Science, Electrical Engineering (2021)
  • M.Sc., TU Delft, Electrical Engineering, Math & Computer Science Faculty, Electrical Engineering (2014)
  • B.Sc., Aristotle University, Physics Department, Physics (2012)

Stanford Advisors


Current Research and Scholarly Interests


- Research in analog/mixed-signal systems for various applications to improve performance and energy efficiency over existing solutions.
- Investigation of architecture and circuit solutions in both BiCMOS and advanced CMOS technologies to realize ultra-low jitter high-linearity multi-GHz-bandwidth next-generation data converter systems.

All Publications


  • In the Pursuit of the Optimal Accuracy–Speed–Power Analog-to-Digital Converter Architecture: A mathematical framework IEEE Solid-State Circuits Magazine (SSC-M) Ramkaj, A., Pelgrom, M. J., Steyaert, M. S., Tavernier, F. 2022; 14 (1): 45-53
  • A 5-GS/s 158.6-mW 9.4-ENOB Passive-Sampling Time-Interleaved Three-Stage Pipelined-SAR ADC With Analog-Digital Corrections in 28-nm CMOS IEEE JOURNAL OF SOLID-STATE CIRCUITS Ramkaj, A. T., Pena Ramos, J. C., Pelgrom, M. M., Steyaert, M. J., Verhelst, M., Tavernier, F. 2020; 55 (6): 1553-1564
  • A 13.5-Gb/s 5-mV-Sensitivity 26.8-ps-CLK-OUT Delay Triple-Latch Feedforward Dynamic Comparator in 28-nm CMOS Ramkaj, A. T., Steyaert, M. J., Tavernier, F., IEEE IEEE. 2019: 167-170
  • An 11 GHz Dual-Sided Self-Calibrating Dynamic Comparator in 28 nm CMOS ELECTRONICS Ramkaj, A., Strackx, M., Steyaert, M., Tavernier, F. 2019; 8 (1)
  • A 1.25-GS/s 7-b SAR ADC With 36.4-dB SNDR at 5 GHz Using Switch-Bootstrapping, USPC DAC and Triple-Tail Comparator in 28-nm CMOS IEEE JOURNAL OF SOLID-STATE CIRCUITS Ramkaj, A. T., Strackx, M., Steyaert, M. J., Tavernier, F. 2018; 53 (7): 1889-1901
  • High-gain and power-efficient dynamic amplifier for pipelined SAR ADCs ELECTRONICS LETTERS Lyu, Y., Ramkaj, A., Tavernier, F. 2017; 53 (23): 1510-1511
  • A 36.4dB SNDR @ 5GHz 1.25GS/s 7b 3.56mW Single-Channel SAR ADC in 28nm Bulk CMOS Ramkaj, A., Strackx, M., Steyaert, M., Tavernier, F., IEEE IEEE. 2017: 167-170
  • Fast Switch Bootstrapping for GS/s High-Resolution Analog-to-Digital Converter Ramkaj, A., Tavernier, F., Steyaert, M., IEEE IEEE. 2015: 73-76