Tiwei Wei is currently a postdoctoral research scholar at the NanoHeat group at Stanford University. He received his Ph.D. degree at the Interuniversity Microelectronics Centre (imec) and KU Leuven, Belgium in 2020. He joined imec in 2015, starting the Ph.D. research with developing electronic cooling solutions for high-performance systems. Before joining in imec, he worked as a researcher staff in Tsinghua University and Hong Kong University of Science and Technology, from 2011 until 2015, where he worked on advanced microelectronic packaging techniques. His current research interests include impingement jet cooling and embedded microchannel cooling for high heat flux applications. Personal website:

Honors & Awards

  • 2020 imec PhD Excellence award, Interuniversity Microelectronics Centre (imec) (2020)
  • IEEE ICEPT2013 Outstanding Paper Award, IEEE Electronics Packaging Society (EPS) (2013)
  • EPS / ECTC Student Travel Award 2019, IEEE Electronics Packaging Society (EPS) (2019)
  • Fellowship for Long Term Research Stay, FWO, Belgium, National Fund for Scientific Research (FWO) of Belgium (Oct 2019)

Boards, Advisory Committees, Professional Organizations

  • Technical committee, IEEE EPS-Reliability (2021 - Present)
  • Executive committee member, IEEE-EPS Silicon Valley Area Chapter (2021 - Present)
  • Technical program committee, IEEE 3DIC 2021 Conference (2021 - Present)
  • Organization committee, REPP (Reliability for Electronics and Photonics Packaging) (2021 - Present)

Professional Education

  • Joint master program, Tsinghua University, Microelectronic packaging (2012)
  • Master of Engineering, Chongqing University of Posts and Telecommunmicati (2012)
  • Doctor of Philosophy, Katholieke Universiteit Leuven (2020)
  • Doctoral Degree, imec & KU Leuven, Microelectronic packaging; Heat Transfer (2020)

Stanford Advisors

Research Interests

  • Technology and Education

Current Research and Scholarly Interests

♦ Package/Chip Level Thermal Management
Perform thermal and flow dynamics analysis for electronics cooling solutions;
BEOL/Thin film thermal modeling and analysis;
♦ MEMS-based Microfluidic Cooling Device Demonstration
Strong background in Microfluidic cooler design and fabrication using CAD design tools, CFD
modeling, and semiconductor processing or additive manufacturing.
♦ 3D Electronic Packaging Development
Thorough understanding of the Chip/Package Level and Wafer Level Processes development with 5
years of cleanroom experience: 3D system integration, embedded packaging.
♦ Topology optimization for advanced manifold flow delivery system
Perform code development for jet cooling manifold fluidic system

All Publications

  • All-in-one design integrates microfluidic cooling into electronic chips. Nature Wei, T. n. 2020; 585 (7824): 188–89

    View details for DOI 10.1038/d41586-020-02503-1

    View details for PubMedID 32908259

  • Conjugate Heat Transfer and Fluid Flow Modeling for Liquid Microjet Impingement Cooling with Alternating Feeding and Draining Channels FLUIDS Wei, T., Oprins, H., Cherman, V., Beyne, E., Baelmans, M. 2019; 4 (3)
  • First Demonstration of a Low Cost/Customizable Chip Level 3D Printed Microjet Hotspot-Targeted Cooler for High Power Applications Wei, T., Oprins, H., Cherman, De Wolf, Beyne, E., Baelmans, M., IEEE IEEE. 2019: 126–34
  • Optimization and Evaluation of Sputtering Barrier/Seed Layer in Through Silicon Via for 3-D Integration TSINGHUA SCIENCE AND TECHNOLOGY Wei, T., Cai, J., Wang, Q., Hu, Y., Wang, L., Liu, Z., Wu, Z. 2014; 19 (2): 150–60
  • Performance and Reliability Study of TGV Interposer in 3D Integration Wei, T., Wang, Q., Cai, J., Chen, L., Huang, J., Wang, L., Zhang, L., Li, C., IEEE IEEE. 2014: 601–5
  • A 3D Integration Testing Vehicle with TSV Interconnects Wei, T., Wang, Q., Liu, Z., Li, Y., Wang, D., Wang, T., Cai, J., IEEE IEEE. 2012
  • Copper Chemical Mechanical Polishing and Wafer Thinning with Temporary Bonding for Through Silicon Via Interconnect Liu, Z., Cai, J., Wang, Q., Wang, T., Wei, T., Li, L., Bi, K., Yang, D., Cai, M. IEEE. 2012: 487–92
  • Copper Filling Process for Small Diameter, High Aspect Ratio Through Silicon Via (TSV) Wei, T., Cai, J., Wang, Q., Liu, Z., Li, Y., Wang, T., Wang, D., Bi, K., Yang, D., Cai, M. IEEE. 2012: 482–86