Alex is currently a Ph.D. student in Electrical Engineering advised by Mark Horowitz and affiliated with the AHA! Agile Hardware Center. He is interested in reconfigurable computing, domain-specific architectures for image processing, and hardware design methodology. He is currently working within the AHA Agile Hardware Project on a next-generation CGRA (coarse-grained reconfigurable architecture) chip generator. Alex received a B.S. in Electrical and Computer Engineering from Washington University in St. Louis in 2017.

Education & Certifications

  • M.S., Stanford University, Electrical Engineering (2020)
  • B.S., Washington University in St. Louis, Electrical Engineering (2017)
  • B.S., Washington University in St. Louis, Computer Engineering (2017)

All Publications

  • AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers ACM Transactions on Embedded Computing Systems Koul, K., Melchert, J., Sreedhar, K., Truong, L., Nyengele, G., Zhang, K., Liu, Q., Setter, J., Chen, P., Mei, Y., Strange, M., Daly, R., Donovick, C., Carsello, A., Kong, T., Feng, K., Huff, D., Nayak, A., Setaluri, R., Thomas, J., Bhagdikar, N., Durst, D., Myers, Z., Tsiskaridze, N., Richardson, S., et al 2023; 22 (2)

    View details for DOI 10.1145/3534933

  • A Framework for Adding Low-Overhead, Fine-Grained Power Domains to CGRAs Nayak, A., Zhang, K., Setaluri, R., Carsello, A., Mann, M., Richardson, S., Bahr, R., Hanrahan, P., Horowitz, M., Raina, P., DiNatale, G., Bolchini, C., Vatajelu, E. I. IEEE. 2020: 846–51
  • Creating an Agile Hardware Design Flow Bahr, R., Barrett, C., Bhagdikar, N., Carsello, A., Daly, R., Donovick, C., Durst, D., Fatahalian, K., Feng, K., Hanrahan, P., Hofstee, T., Horowitz, M., Huff, D., Kjolstad, F., Kong, T., Liu, Q., Mann, M., Melchert, J., Nayak, A., Niemetz, A., Nyengele, G., Raina, P., Richardson, S., Setaluri, R., Setter, J., Sreedhar, K., Strange, M., Thomas, J., Torng, C., Truong, L., Tsiskaridze, N., Zhang, K., IEEE IEEE. 2020