Bio

Alex is currently a Ph.D. student in Electrical Engineering advised by Mark Horowitz and affiliated with the AHA! Agile Hardware Center. He is interested in reconfigurable computing, domain-specific architectures for image processing, and hardware design methodology. He is currently working within the AHA Agile Hardware Project on a next-generation CGRA (coarse-grained reconfigurable architecture) chip generator. Alex received a B.S. in Electrical and Computer Engineering from Washington University in St. Louis in 2017.

Education & Certifications

  • M.S., Stanford University, Electrical Engineering (2020)
  • B.S., Washington University in St. Louis, Electrical Engineering (2017)
  • B.S., Washington University in St. Louis, Computer Engineering (2017)

Contact

  • Academic
    ajcars@stanford.edu
    University - Student Department: Electrical Engineering Position: Graduate

Additional Info

All Publications

  • Amber: A 16-nm System-on-Chip With a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra IEEE JOURNAL OF SOLID-STATE CIRCUITS Feng, K., Kong, T., Koul, K., Melchert, J., Carsello, A., Liu, Q., Nyengele, G., Strange, M., Zhang, K., Nayak, A., Setter, J., Thomas, J., Sreedhar, K., Chen, P., Bhagdikar, N., Myers, Z. A., D'Agostino, B., Joshi, P., Richardson, S., Torng, C., Horowitz, M., Raina, P. 2023

    View details for DOI 10.1109/JSSC.2023.3313116

    View details for Web of Science ID 001078350700001

  • AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers ACM Transactions on Embedded Computing Systems Koul, K., Melchert, J., Sreedhar, K., Truong, L., Nyengele, G., Zhang, K., Liu, Q., Setter, J., Chen, P., Mei, Y., Strange, M., Daly, R., Donovick, C., Carsello, A., Kong, T., Feng, K., Huff, D., Nayak, A., Setaluri, R., Thomas, J., Bhagdikar, N., Durst, D., Myers, Z., Tsiskaridze, N., Richardson, S., et al 2023; 22 (2)

    View details for DOI 10.1145/3534933

  • mflowgen: a modular flow generator and ecosystem for community-driven physical design DAC '22: Proceedings of the 59th ACM/IEEE Design Automation Conference Carsello, A., Thomas, J., Nayak, A., Chen, P., Horowitz, M., Raina, P., Torng, C. 2022: 1339–1342

    View details for DOI 10.1145/3489517.3530633

  • Improving Energy Efficiency of CGRAs with Low-Overhead Fine-Grained Power Domains ACM Transactions on Reconfigurable Technology and Systems Nayak, A., Zhang, K., Setaluri, R., Carsello, A., Mann, M., Torng, C., Richardson, S., Bahr, R., Hanrahan, P., Horowitz, M., Raina, P. 2022

    View details for DOI 10.1145/3558394

  • Amber: A 367 GOPS, 538 GOPS/W 16nm SoC with a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Carsello, A., et al 2022

    View details for DOI 10.1109/VLSITechnologyandCir46769.2022.9830509

  • A Framework for Adding Low-Overhead, Fine-Grained Power Domains to CGRAs Nayak, A., Zhang, K., Setaluri, R., Carsello, A., Mann, M., Richardson, S., Bahr, R., Hanrahan, P., Horowitz, M., Raina, P., DiNatale, G., Bolchini, C., Vatajelu, E. I. IEEE. 2020: 846–51

    View details for Web of Science ID 000610549200156

  • Creating an Agile Hardware Design Flow Bahr, R., Barrett, C., Bhagdikar, N., Carsello, A., Daly, R., Donovick, C., Durst, D., Fatahalian, K., Feng, K., Hanrahan, P., Hofstee, T., Horowitz, M., Huff, D., Kjolstad, F., Kong, T., Liu, Q., Mann, M., Melchert, J., Nayak, A., Niemetz, A., Nyengele, G., Raina, P., Richardson, S., Setaluri, R., Setter, J., Sreedhar, K., Strange, M., Thomas, J., Torng, C., Truong, L., Tsiskaridze, N., Zhang, K., IEEE IEEE. 2020

    View details for Web of Science ID 000628528400063

https://orcid.org/0000-0003-2549-9525