Bio

Azalia Mirhoseini is an Assistant Professor in the Computer Science Department at Stanford University. Professor Mirhoseini's research interest is in developing capable, reliable, and efficient AI systems for solving high-impact, real-world problems. Her work includes generalized learning-based methods for decision-making problems in systems and chip design, self-improving AI models through interactions with the world, and scalable deep learning optimization. Prior to Stanford, she spent several years in industry AI labs, including Anthropic and Google Brain. At Anthropic, she worked on advancing the capabilities and reliability of large language models. At Google Brain, she co-founded the ML for Systems team, with a focus on automating and optimizing computer systems and chip design. She received her BSc degree in Electrical Engineering from Sharif University of Technology and her PhD in Electrical and Computer Engineering from Rice University. Her work has been recognized through the MIT Technology Review’s 35 Under 35 Award, the Best ECE Thesis Award at Rice University, publications in flagship venues such as Nature, and coverage by various media outlets, including MIT Technology Review, IEEE Spectrum, The Verge, The Times, ZDNet, VentureBeat, and WIRED.

Academic Appointments

Contact

  • Academic
    azalia@stanford.edu
    University - Faculty Department: Computer Science Position: Asst Professor

Links

2023-24 Courses

Stanford Advisees

All Publications

  • A Full-Stack Search Technique for Domain Optimized Deep Learning Accelerators Zhang, D., Huda, S., Songhori, E., Prabhu, K., Quoc Le, Goldie, A., Mirhoseini, A., Falsafi, B., Ferdman, M., Lu, S., Weinisch, T. ASSOC COMPUTING MACHINERY. 2022: 27-42

    View details for DOI 10.1145/3503222.3507767

    View details for Web of Science ID 000810486300003

  • A graph placement methodology for fast chip design. Nature Mirhoseini, A., Goldie, A., Yazgan, M., Jiang, J. W., Songhori, E., Wang, S., Lee, Y., Johnson, E., Pathak, O., Nazi, A., Pak, J., Tong, A., Srinivasa, K., Hang, W., Tuncer, E., Le, Q. V., Laudon, J., Ho, R., Carpenter, R., Dean, J. 2021; 594 (7862): 207-212

    Abstract

    Chip floorplanning is the engineering task of designing the physical layout of a computer chip. Despite five decades of research1, chip floorplanning has defied automation, requiring months of intense effort by physical design engineers to produce manufacturable layouts. Here we present a deepreinforcementlearning approach to chip floorplanning. In under six hours, our method automatically generates chip floorplans that are superior or comparable to those produced by humans in all key metrics, including power consumption, performance and chip area. To achieve this, we pose chip floorplanning as a reinforcementlearning problem, and develop an edge-based graph convolutional neural network architecture capable of learning rich and transferable representations of the chip. As a result, our method utilizes past experience to become better and faster at solving new instances of the problem, allowing chip design to be performed by artificial agents with more experience than any human designer. Our method was used to design the next generation of Google's artificial intelligence (AI) accelerators, and has the potential to save thousands of hours of human effort for each new generation. Finally, we believe that more powerful AI-designed hardware will fuel advances in AI, creating a symbiotic relationship between the two fields.

    View details for DOI 10.1038/s41586-021-03544-w

    View details for PubMedID 34108699