All Publications

  • EMBER: A 100 MHz, 0.86 mm<SUP>2</SUP>, Multiple-Bits-per-Cell RRAM Macro in 40 nm CMOS with Compact Peripherals and 1.0 pJ/bit Read Circuitry Upton, L. R., Levy, A., Scott, M. D., Rich, D., Khwa, W., Chih, Y., Chang, M., Mitra, S., Raina, P., Murmann, B., IEEE IEEE. 2023: 469-472
  • Ultra-Dense 3D Physical Design Unlocks New Architectural Design Points with Large Benefits Srimani, T., Radway, R. M., Kim, J., Prabhu, K., Rich, D., Gilardi, C., Raina, P., Shulaker, M., Lim, S., Mitra, S., IEEE IEEE. 2023
  • Testbench on a Chip: A Yield Test Vehicle for Resistive Memory Devices Upton, L. R., Lallement, G., Scott, M. D., Taylor, J., Radway, R. M., Rich, D., Nelson, M., Mitra, S., Murmann, B., IEEE IEEE. 2023: 576-582