Bio

Kalhan Koul is an EE Ph.D. student at Stanford University supervised by Prof. Priyanka Raina. Previously, he was a Digital Design Intern at Micron and Silicon Labs. He received a B.S. in Electrical Engineering Honors and a B.A. in Plan II Honors (Liberal Arts) from The University of Texas in 2018 and his M.S. in Electrical Engineering from Stanford University in 2021. During his PhD he has worked on three chip tapeouts. The first was Chimera, a DNN accelerator utilizing RRAM for low energy inference. The next was Amber, a coarse grained reconfigurable array (CGRA) optimized for image processing and machine learning applications. Finally, Kalhan led the tapeout of Onyx, a CGRA accelerating both dense and sparse kernels on the same fabric. His current research focuses on further improving the efficiency of the CGRA and extending its acceleration to end-to-end machine learning workloads.

Contact

  • Academic
    kkoul@stanford.edu
    University - Student Department: Electrical Engineering Position: Graduate

Additional Info

  • Mail Code: 9505

All Publications

  • Cascade: An Application Pipelining Toolkit for Coarse-Grained Reconfigurable Arrays IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS Melchert, J., Mei, Y., Koul, K., Liu, Q., Horowitz, M., Raina, P. 2024; 43 (10): 3055-3067

    View details for DOI 10.1109/TCAD.2024.3390542

    View details for Web of Science ID 001319522900009

  • Amber: A 16-nm System-on-Chip With a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra IEEE JOURNAL OF SOLID-STATE CIRCUITS Feng, K., Kong, T., Koul, K., Melchert, J., Carsello, A., Liu, Q., Nyengele, G., Strange, M., Zhang, K., Nayak, A., Setter, J., Thomas, J., Sreedhar, K., Chen, P., Bhagdikar, N., Myers, Z. A., D'Agostino, B., Joshi, P., Richardson, S., Torng, C., Horowitz, M., Raina, P. 2023

    View details for DOI 10.1109/JSSC.2023.3313116

    View details for Web of Science ID 001078350700001

  • AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers ACM Transactions on Embedded Computing Systems Koul, K., Melchert, J., Sreedhar, K., Truong, L., Nyengele, G., Zhang, K., Liu, Q., Setter, J., Chen, P., Mei, Y., Strange, M., Daly, R., Donovick, C., Carsello, A., Kong, T., Feng, K., Huff, D., Nayak, A., Setaluri, R., Thomas, J., Bhagdikar, N., Durst, D., Myers, Z., Tsiskaridze, N., Richardson, S., et al 2023; 22 (2)

    View details for DOI 10.1145/3534933

  • CHIMERA: A 0.92-TOPS, 2.2-TOPS/W Edge AI Accelerator With 2-MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference IEEE JOURNAL OF SOLID-STATE CIRCUITS Prabhu, K., Gural, A., Khan, Z. F., Radway, R. M., Giordano, M., Koul, K., Doshi, R., Kustin, J. W., Liu, T., Lopes, G. B., Turbiner, V., Khwa, W., Chih, Y., Chang, M., Lallement, G., Murmann, B., Mitra, S., Raina, P. 2022

    View details for DOI 10.1109/JSSC.2022.3140753

    View details for Web of Science ID 000750226200001