
Kavya Sreedhar
Ph.D. Student in Electrical Engineering, admitted Autumn 2019
Bio
Kavya is an electrical engineering PhD student advised by Mark Horowitz. She is interested in architecture design and developing hardware accelerators for machine learning and cryptography applications. Her current research explores how to efficiently accelerate the extended GCD computation for verifiable delay functions and modular inversion in cryptography. She previously worked with the Agile Hardware (AHA) Project in developing Lake, a parameterizable memory generator that can be configured at runtime to support different image processing and machine learning applications. She is supported by Stanford's Knight-Hennessy scholarship and received her B.S. in electrical engineering and BEM (Business, Economics, & Management) from Caltech in 2019 and her M.S. in electrical engineering from Stanford in 2021.
Education & Certifications
-
M.S., Stanford University, Electrical Engineering (2021)
-
B.S., California Institute of Technology, Business, Economics, and Management (2019)
-
B.S., California Institute of Technology, Electrical Engineering (2019)
All Publications
-
AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers
ACM Transactions on Embedded Computing Systems
2023; 22 (2)
View details for DOI 10.1145/3534933
-
Creating an Agile Hardware Design Flow
IEEE. 2020
View details for Web of Science ID 000628528400063