Pumiao Yan

All Publications

• A 1024-Channel 268 nW/pixel 36×36 μm2/channel Data-Compressive Neural Recording IC for High-Bandwidth Brain-Computer Interfaces. IEEE journal of solid-state circuits Jang, M., Hays, M., Yu, W. H., Lee, C., Caragiulo, P., Ramkaj, A., Wang, P., Phillips, A. J., Vitale, N., Tandon, P., Yan, P., Mak, P. I., Chae, Y., Chichilnisky, E. J., Murmann, B., Muratore, D. G. 2024; 59 (4): 1123-1136

  Abstract

  This paper presents a data-compressive neural recording IC for single-cell resolution high-bandwidth brain-computer interfaces. The IC features wired-OR lossy compression during digitization, thus preventing data deluge and massive data movement. By discarding unwanted baseline samples of the neural signals, the output data rate is reduced by 146× on average while allowing the reconstruction of spike samples. The recording array consists of pulse position modulation-based active digital pixels with a global single-slope analog-to-digital conversion scheme, which enables a low-power and compact pixel design with significantly simple routing and low array readout energy. Fabricated in a 28-nm CMOS process, the neural recording IC features 1024 channels (i.e., 32 × 32 array) with a pixel pitch of 36 μm that can be directly matched to a high-density microelectrode array. The pixel achieves 7.4 μVrms input-referred noise with a -3 dB bandwidth of 300-Hz to 5-kHz while consuming only 268 nW from a single 1-V supply. The IC achieves the smallest area per channel (36 × 36 μm2) and the highest energy efficiency among the state-of-the-art neural recording ICs published to date.

  View details for DOI 10.1109/jssc.2023.3344798

  View details for PubMedID 39391047

  View details for PubMedCentralID PMC11463976

• A 1024-Channel 268-nW/Pixel 36 x 36 μm<SUP>2</SUP>/Channel Data-Compressive Neural Recording IC for High-Bandwidth Brain-Computer Interfaces IEEE JOURNAL OF SOLID-STATE CIRCUITS Jang, M., Hays, M., Yu, W., Lee, C., Caragiulo, P., Ramkaj, A. T., Wang, P., Phillips, A. J., Vitale, N., Tandon, P., Yan, P., Mak, P., Chae, Y., Chichilnisky, E. J., Murmann, B., Muratore, D. G. 2023

  View details for DOI 10.1109/JSSC.2023.3344798

  View details for Web of Science ID 001137386500001

• Data Compression Versus Signal Fidelity Tradeoff in Wired-OR Analog-to-Digital Compressive Arrays for Neural Recording. IEEE transactions on biomedical circuits and systems Yan, P., Akhoundi, A., Shah, N. P., Tandon, P., Muratore, D. G., Chichilnisky, E. J., Murmann, B. 2023; PP

  Abstract

  Future high-density and high channel count neural interfaces that enable simultaneous recording of tens of thousands of neurons will provide a gateway to study, restore and augment neural functions. However, building such technology within the bit-rate limit and power budget of a fully implantable device is challenging. The wired-OR compressive readout architecture addresses the data deluge challenge of a high channel count neural interface using lossy compression at the analog-to-digital interface. In this paper, we assess the suitability of wired-OR for several steps that are important for neuroengineering, including spike detection, spike assignment and waveform estimation. For various wiring configurations of wired-OR and assumptions about the quality of the underlying signal, we characterize the trade-off between compression ratio and task-specific signal fidelity metrics. Using data from 18 large-scale microelectrode array recordings in macaque retina ex vivo, we find that for an event SNR of 7-10, wired-OR correctly detects and assigns at least 80% of the spikes with at least 50* compression. The wired-OR approach also robustly encodes action potential waveform information, enabling downstream processing such as cell -type classification. Finally, we show that by applying an LZ77-based lossless compressor (gzip) to the output of the wired-OR architecture, 1000* compression can be achieved over the baseline recordings.

  View details for DOI 10.1109/TBCAS.2023.3292058

  View details for PubMedID 37402181