Bio


Wong studies the fabrication and design of high-performance integrated circuits. His work focuses on understanding and overcoming the limitations of circuit performance imposed by device, interconnect and on-chip components.

Academic Appointments


Honors & Awards


  • Fellow, IEEE

Boards, Advisory Committees, Professional Organizations


  • Board Director, Pericom Semiconductor (2006 - Present)

Professional Education


  • PhD, UC Berkeley (1983)

Current Research and Scholarly Interests


Current research focuses on

Resistive Random Access Memory (RRAM) and Integration with CMOS
Student : Yu-Chung Lien

Design of 3D Memory and 3D Programmable Logic
Students : Alexander Hu, Kibum Lee

Energy Efficient Analog-to-Digital Matrix Multiplication Techniques
Student : Edward Lee

2014-15 Courses


Journal Articles


  • All-Metal-Nitride RRAM Devices IEEE ELECTRON DEVICE LETTERS Zhang, Z., Gao, B., Fang, Z., Wang, X., Tang, Y., Sohn, J., Wong, H. P., Wong, S. S., Lo, G. 2015; 36 (1): 29-31
  • Nanometer-Scale HfOx RRAM IEEE ELECTRON DEVICE LETTERS Zhang, Z., Wu, Y., Wong, H. P., Wong, S. S. 2013; 34 (8): 1005-1007
  • Low-Temperature Monolithic Three-Layer 3-D Process for FPGA IEEE ELECTRON DEVICE LETTERS Zhang, Z., Chen, C., Crnogorac, F., Chen, S., Griffin, P. B., Pease, R. F., Plummer, J. D., Wong, S. S. 2013; 34 (8): 1044-1046
  • Impact of III-V and Ge Devices on Circuit Performance IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS Park, J., Oh, S., Kim, S., Wong, H. P., Wong, S. S. 2013; 21 (7): 1189-1200
  • Effect of Wordline/Bitline Scaling on the Performance, Energy Consumption, and Reliability of Cross-Point Memory Array ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS Liang, J., Yeh, S., Wong, S. S., Wong, H. P. 2013; 9 (1)
  • Characterization of Geometric Leakage Current of GeO2 Isolation and Effect of Forming Gas Annealing in Germanium p-n Junctions IEEE ELECTRON DEVICE LETTERS Jung, W., Park, J., Lin, J. J., Wong, S., Saraswat, K. C. 2012; 33 (11): 1520-1522
  • A superheterodyne receiver front-end with on-chip automatically Q-tuned notch filters ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING Chi, B., Wang, Z., Wong, S. S. 2012; 71 (3): 453-463
  • Array Architecture for a Nonvolatile 3-Dimensional Cross-Point Resistance-Change Memory IEEE JOURNAL OF SOLID-STATE CIRCUITS Ou, E., Wong, S. S. 2011; 46 (9): 2158-2170
  • A 65 nm CMOS fully-integrated dynamic reconfigurable differential power amplifier with high gain in both bands MICROELECTRONICS JOURNAL Chi, B., Omid-Zohoor, K., Wang, Z., Wong, S. S. 2011; 42 (6): 855-862
  • Optimization of Driver Preemphasis for On-Chip Interconnects IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS Bai, Y., Wong, S. S. 2009; 56 (9): 2033-2041
  • RESET Mechanism of TiOx Resistance-Change Memory Device IEEE ELECTRON DEVICE LETTERS Wang, W., Fujita, S., Wong, S. S. 2009; 30 (7): 733-735
  • Elimination of Forming Process for TiOx Nonvolatile Memory Devices IEEE ELECTRON DEVICE LETTERS Wang, W., Fujita, S., Wong, S. S. 2009; 30 (7): 763-765
  • Reduction of Inductive Crosstalk Using Quadrupole Inductors IEEE JOURNAL OF SOLID-STATE CIRCUITS Poon, A., Chang, A., Samavati, H., Wong, S. S. 2009; 44 (6): 1756-1764
  • Pi Coil: A New Element for Bandwidth Extension IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS Lin, S., Huang, D., Wong, S. 2009; 56 (6): 454-458
  • A 60-GHz LOW-NOISE AMPLIFIER FOR 60-GHz DUAL-CONVERSION RECEIVER MICROWAVE AND OPTICAL TECHNOLOGY LETTERS Lin, Y., Wong, S. S. 2009; 51 (4): 885-891

    View details for DOI 10.1002/mop.24200

    View details for Web of Science ID 000264111800004

  • The Prospect of 3D-IC PROCEEDINGS OF THE IEEE 2009 CUSTOM INTEGRATED CIRCUITS CONFERENCE Wong, S. S., El Gamal, A. 2009: 445-448
  • Performance Comparison between Capacitively Driven Low Swing and Conventional Interconnects for Cu and Carbon Nanotube Wire Technologies PROCEEDINGS OF THE 2009 IEEE INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE Koo, K., Kapur, P., Park, J., Noh, H., Wong, S. S., Saraswat, K. C. 2009: 23-25
  • Numerical estimation of yield in sub-100-nm SRAM design using Monte Carlo simulation IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS Nho, H., Yoon, S., Wong, S. S., Jung, S. 2008; 55 (9): 907-911
  • High-performance gate-all-around GeOI p-MOSFETs fabricated by rapid melt growth using plasma nitridation and ALD Al2O3 gate dielectric and self-aligned NiGe contacts IEEE ELECTRON DEVICE LETTERS Feng, J., Thareja, G., Kobayashi, M., Chen, S., Poon, A., Bai, Y., Griffin, P. B., Wong, S. S., Nishi, Y., Plummer, J. D. 2008; 29 (7): 805-807
  • A High-speed, Low-power 3D-SRAM Architecture PROCEEDINGS OF THE IEEE 2008 CUSTOM INTEGRATED CIRCUITS CONFERENCE Nho, H. H., Horowitz, M., Wong, S. S. 2008: 201-204
  • An on-chip dipole antenna for millimeter-wave transmitters 2008 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS SYMPOSIUM, VOLS 1 AND 2 Park, P. H., Wong, S. S. 2008: 571-574
  • Thickness and stoichiometry dependence of the thermal conductivity of GeSbTe films APPLIED PHYSICS LETTERS Reifenberg, J. P., Panzer, M. A., Kim, S., Gibby, A. M., Zhang, Y., Wong, S., Wong, H. P., Pop, E., Goodson, K. E. 2007; 91 (11)

    View details for DOI 10.1063/1.2784169

    View details for Web of Science ID 000249474000022

  • Closed-form RC and RLC delay models considering input rise time IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS Kim, S., Wong, S. S. 2007; 54 (9): 2001-2010
  • Statistical simulation methodology for sub100 nm memory design ELECTRONICS LETTERS Nho, H., Yoon, S., Wong, S., Jung, S. 2007; 43 (16): 869-870
  • Resistive switching mechanism in ZnxCd1-xS nonvolatile memory devices IEEE ELECTRON DEVICE LETTERS Wang, Z., Griffin, P. B., McVittie, J., Wong, S., McIntyre, P. C., Nishi, Y. 2007; 28 (1): 14-16
  • Integrated transformer baluns for RF low noise and power amplifiers 2006 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS (RFIC) SYMPOSIUM, DIGEST OF PAPERS Gan, H., Wong, S. S. 2006: 85-88
  • Multiphysics modeling and impact of thermal boundary resistance in phase change memory devices 2006 PROCEEDINGS 10TH INTERSOCIETY CONFERENCE ON THERMAL AND THERMOMECHANICAL PHENOMENA IN ELECTRONICS SYSTEMS, VOLS 1 AND 2 Reifenberg, J., Pop, E., Gibby, A., Wong, S., Goodson, K. 2006: 106-113
  • Integrated transformer baluns for RF low noise and power amplifiers 2006 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS SYMPOSIUM Gan, H., Wong, S. S. 2006: 69-72
  • Analysis and synthesis of on-chip spiral inductors IEEE TRANSACTIONS ON ELECTRON DEVICES Talwalkar, N. A., Yue, C. P., Wong, S. S. 2005; 52 (2): 176-182
  • Studies of the driving force for room-temperature microstructure evolution in electroplated copper films JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B Lee, H., Nix, W. D., Wong, S. S. 2004; 22 (5): 2369-2374

    View details for DOI 10.1116/1.1788680

    View details for Web of Science ID 000225048300022

  • Integrated CMOS transmit-receive switch using LC-Tuned substrate bias for 2.4-GHz and 5.2-GHz applications IEEE JOURNAL OF SOLID-STATE CIRCUITS Talwalkar, N. A., Yue, C. P., Gan, H. T., Wong, S. S. 2004; 39 (6): 863-870
  • Valuation of American options via basis functions IEEE TRANSACTIONS ON AUTOMATIC CONTROL Lai, T. L., Wong, S. P. 2004; 49 (3): 374-385
  • Modeling and optimization of substrate resistance for RF-CMOS IEEE TRANSACTIONS ON ELECTRON DEVICES Chang, R. T., Yang, M. T., Ho, P. P., Wang, Y. J., Chia, Y. T., Liew, B. K., Yue, C. P., Wong, S. S. 2004; 51 (3): 421-426
  • Near speed-of-light velocities for on-chip - transmission of electrical signals SOLID STATE TECHNOLOGY Chang, R. T., Wong, S. S. 2003; 46 (5): 52-?
  • Correlation of stress and texture evolution during self- and thermal annealing of electroplated Cu films JOURNAL OF APPLIED PHYSICS Lee, H., Wong, S. S., Lopatin, S. D. 2003; 93 (7): 3796-3804

    View details for DOI 10.1063/1.1555274

    View details for Web of Science ID 000181729600010

  • Design of a 10GHz clock distribution network using coupled standing-wave oscillators 40TH DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2003 O'Mahony, F., Yue, C. P., Horowitz, M. A., Wong, S. S. 2003: 682-687
  • Compact modeling of high frequency phenomena for on-chip spiral inductors NANOTECH 2003, VOL 2 Talwalkar, N., Yue, C. P., Wong, S. S. 2003: 360-363
  • On the accuracy of return path assumption for loop inductance extraction for 0.1 mu m technology and beyond 4TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, PROCEEDINGS Kim, S. Y., Massoud, Y., Wong, S. S. 2003: 401-404
  • High-frequency characterization of on-chip digital interconnects IEEE JOURNAL OF SOLID-STATE CIRCUITS Kleveland, B., Qi, X. N., Madden, L., Furusawa, T., DUTTON, R. W., Horowitz, M. A., Wong, S. S. 2002; 37 (6): 716-725
  • Exploiting CMOS reverse interconnect scaling in multigigahertz amplifier and oscillator design (vol 36, pg 1480, 2001) IEEE JOURNAL OF SOLID-STATE CIRCUITS Kleveland, B., Diaz, C. H., Vook, D., Madden, L., Lee, T. H., Wong, S. S. 2002; 37 (2): 255-255
  • Recovery of open via after electromigration in Cu dual Damascene interconnect 40TH ANNUAL PROCEEDINGS: INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM Sun, Y. H., Zhou, P., Kim, D. Y., Goodson, K. E., Wong, S. S. 2002: 435-436
  • High Frequency Characterization of On-Chip Digital Interconnects IEEE Journal of Solid State Circuits Kleveland, B., Qi, X., Madden, L., Furusawa, T., Dutton, R., Horowitz, M., Wong, S. S. 2002; 37: 716-725
  • Exploiting CMOS reverse interconnect scaling in multigigahertz amplifier and oscillator design IEEE JOURNAL OF SOLID-STATE CIRCUITS Kleveland, B., Diaz, C. H., Vook, D., Madden, L., Lee, T. H., Wong, S. S. 2001; 36 (10): 1480-1488
  • A 0dB-IL, 2140 +/- 30 MHz bandpass filter utilizing Q-enhanced spiral inductors in standard CMOS 2001 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS Soorapanth, T., Wong, S. S. 2001: 15-18
  • CMOS RF integrated circuits at 5 GHz and beyond PROCEEDINGS OF THE IEEE Lee, T. H., Wong, S. S. 2000; 88 (10): 1560-1571
  • Distributed ESD protection for high-speed integrated circuits IEEE ELECTRON DEVICE LETTERS Kleveland, B., Maloney, T. J., Morgan, I., Madden, L., Lee, T. H., Wong, S. S. 2000; 21 (8): 390-392
  • Physical modeling of spiral inductors on silicon IEEE TRANSACTIONS ON ELECTRON DEVICES Yue, C. P., Wong, S. S. 2000; 47 (3): 560-568
  • Kinetics of copper drift in low-kappa polymer interlevel dielectrics IEEE TRANSACTIONS ON ELECTRON DEVICES Loke, A. L., Wetzel, J. T., Townsend, P. H., Tanabe, T., Vrtis, R. N., Zussman, M. P., Kumar, D., Ryu, C., Wong, S. S. 1999; 46 (11): 2178-2187
  • A BICMOS active substrate probe-card technology for digital testing IEEE JOURNAL OF SOLID-STATE CIRCUITS Zargari, M., Leung, J., Wong, S. S., Wooley, B. A. 1999; 34 (8): 1118-1135
  • Microstructure and reliability of copper interconnects IEEE TRANSACTIONS ON ELECTRON DEVICES Ryu, C., Kwon, K. W., Loke, A. L., LEE, H., Nogami, T., Dubin, V. M., Kavari, R. A., Ray, G. W., Wong, S. S. 1999; 46 (6): 1113-1120
  • Barriers for copper interconnections SOLID STATE TECHNOLOGY Ryu, C. S., Lee, H. B., Kwon, K. W., Loke, A. L., Wong, S. S. 1999; 42 (4): 53-?
  • Kinetics of Copper Drift in Low-k Polymer Interlevel Dielectrics IEEE Transactions on Electron Devices Loke, A., Wetzel, J., Townsend, P., Tanabe, T., Vrtis, R., Zussman, M., Wong, S. S. 1999; 46: 2178-2187
  • Evaluation of copper penetration in low-kappa polymer dielectrics by bias-temperature stress ADVANCED INTERCONNECTS AND CONTACTS Loke, A. L., Wong, S. S., Talwalkar, N. A., Wetzel, J. T., Townsend, P. H., Tanabe, T., Vrtis, R. N., Zussman, M. P., Kumar, D. 1999; 564: 535-549
  • Evaluation of copper penetration in low-kappa polymer dielectrics by bias-temperature stress LOW-DIELECTRIC CONSTANT MATERIALS V Loke, A. L., Wong, S. S., Talwalkar, N. A., Wetzel, J. T., Townsend, P. H., Tanabe, T., Vrtis, R. N., Zussman, M. P., Kumar, D. 1999; 565: 173-187
  • Lateral IGBT in thin SOI for high voltage, high speed power IC IEEE TRANSACTIONS ON ELECTRON DEVICES Leung, Y. K., Paul, A. K., Plummer, J. D., Wong, S. S. 1998; 45 (10): 2251-2254
  • Electrical leakage at low-K polyimide/TEOS interface IEEE ELECTRON DEVICE LETTERS Loke, A. L., Wetzel, J. T., Stankus, J. J., Angyal, M. S., Mowry, B. K., Wong, S. S. 1998; 19 (6): 177-179
  • SOI MOSFET with buried body strap by wafer bonding IEEE TRANSACTIONS ON ELECTRON DEVICES Kuehne, S. C., Chan, A. B., Nguyen, C. T., Wong, S. S. 1998; 45 (5): 1084-1091
  • Electrical reliability of Cu and low-K dielectric integration LOW-DIELECTRIC CONSTANT MATERIALS IV Wong, S. S., Loke, A. L., Wetzel, J. T., Townsend, P. H., Vrtis, R. N., Zussman, M. P. 1998; 511: 317-327
  • A Novel Crosstalk Isolation Structure for Bulk CMOS Power IC’s IEEE Transactions on Electron Devices Chan, W., Sin, J., Wong, S. 1998; 45: 1580-1586
  • Evidence of heteroepitaxial growth of copper on beta-tantalum APPLIED PHYSICS LETTERS Kwon, K. V., Ryu, C., Sinclair, R., Wong, S. S. 1997; 71 (21): 3069-3071
  • Phonon-boundary scattering in thin silicon layers APPLIED PHYSICS LETTERS Asheghi, M., Leung, Y. K., Wong, S. S., Goodson, K. E. 1997; 71 (13): 1798-1800
  • Investigation of aluminum nitride grown by metal-organic chemical-vapor deposition on silicon JOURNAL OF APPLIED PHYSICS Zetterling, C. M., Ostling, M., Wongchotigul, K., Spencer, M. G., Tang, X., Harris, C. I., Nordell, N., Wong, S. S. 1997; 82 (6): 2990-2995
  • Heating mechanisms of LDMOS and LIGBT in ultrathin SOI IEEE ELECTRON DEVICE LETTERS Leung, Y. K., Paul, A. K., Goodson, K. E., Plummer, J. D., Wong, S. S. 1997; 18 (9): 414-416
  • Short-timescale thermal mapping of semiconductor devices IEEE ELECTRON DEVICE LETTERS Ju, Y. S., KADING, O. W., Leung, Y. K., Wong, S. S., Goodson, K. E. 1997; 18 (5): 169-171
  • Reactive-ion-etched diffraction-limited unstable resonator semiconductor lasers IEEE JOURNAL OF QUANTUM ELECTRONICS Biellak, S. A., Fanning, G., Sun, Y., Wong, S. S., Siegman, A. E. 1997; 33 (2): 219-230
  • Spatial temperature profiles due to nonuniform self-heating in LDMOS's in thin SOI IEEE ELECTRON DEVICE LETTERS Leung, Y. K., Kuehne, S. C., Huang, V. S., Nguyen, C. T., Paul, A. K., Plummer, J. D., Wong, S. S. 1997; 18 (1): 13-15
  • Polished TFT's: Surface Roughness Reduction and Its Correlation to Device Performance Improvement IEEE Transactions on Electron Devices Chan, A., Nguyen, C., Ko, P., Chan, S., Wong, S. 1997; 44: 455-463
  • Electrical extraction of the in-plane dielectric constant of fluorinated polyimide LOW-DIELECTRIC CONSTANT MATERIALS III Loke, A. L., Wetzel, J. T., Stankus, J. J., Wong, S. S. 1997; 476: 129-134
  • Pnonon-Boundary Scattering in Thin Silicon Layers Applied Physics Letters Asheghi, M., leung, Y., Wong, S., Goodson, K. 1997; 71: 1798-1800
  • Evidence of reduced maximum E-field in Quasi-SOI MOSFET's IEEE TRANSACTIONS ON ELECTRON DEVICES Ng, C. M., Nguyen, C. T., Kuehne, S. C., Wong, S. S. 1996; 43 (12): 2308-2310
  • Kinetics of copper drift in PECVD dielectrics IEEE ELECTRON DEVICE LETTERS Loke, A. L., Ryu, C., Yue, C. P., CHO, J. S., Wong, S. S. 1996; 17 (12): 549-551
  • Optimizing Polysilicon Thin-Film Transistor Performance with Chemical-Mechanical Polishing and Hydrogenation IEEE Electron Device Letters Chan, A., Nguyen, C., Ko, P., Wong, M., Kumar, A., Sin, J. 1996; 17: 518-520
  • A Power IC technology with Excellent Cross-Talk Isolation IEEE Electron Device Letters Chan, W., Sin, J., Mok, P., Wong, S. 1996; 17: 467-469
  • High voltage LDMOS transistors in sub-micron SOI films ISPSD '96 - 8TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES AND ICS, PROCEEDINGS Paul, A. K., Leung, Y. K., Plummer, J. D., Wong, S. S., Kuehne, S. C., Huang, V. S., Nguyen, C. T. 1996: 89-92
  • A Micromachined Array Probe Card - Characterization IEEE Transactions on Components, Packaging and Manufacturing Technology Part B: Advanced Packaging Beiley, M., Leung, J., Wong, S. 1995; 18: 184-191
  • A Micromachined Array Probe Card - Fabrication Process IEEE Transactions on Components, Packaging and Manufacturing Technology Part B: Advanced Packaging Beiley, M., Leung, J., Wong, S. 1995; 18: 179-183
  • Reliability of Chemically Vapor Deposited (CVD) Copper Interconnections Journal of Materials Chemistry and Physics Wong, S., Cho, J., Kang, H., Ryu, C. 1995; 41: 229-233
  • Contact Technology for High Performance Scalable BiCMOS on TFSOI IEEE Electron Device Letters Racanelli, M., Huang, W., Kuehne, S., Foerstner, J., Wong, S., Hwang, B. 1995; 16: 424-426
  • Lateral Mode Behavior of Reactive-Ion-Etched Stable-Resonator Semiconductor Lasers Journal of Applied Physics Biellak, S., Sun, Y., Wong, S., Siegman, A. 1995; 78: 4294-4296
  • THE EFFECTS OF IMPACT IONIZATION ON THE OPERATION OF NEIGHBORING DEVICES AND CIRCUITS IEEE TRANSACTIONS ON ELECTRON DEVICES Sakui, K., Wong, S. S., Wooley, B. A. 1994; 41 (9): 1603-1607
  • MEASUREMENT OF SUBSTRATE CURRENT IN SOI MOSFETS IEEE ELECTRON DEVICE LETTERS Nguyen, C. T., VERPLOEG, E. P., Kuehne, S. C., Plummer, J. D., Wong, S. S., Renteln, P. 1994; 15 (4): 132-134
  • Parasitic Bipolar Gain in Fully Depleted n-Channel SOI MOSFET’s IEEE Transactions on Electron Devices Ploeg, E., Ver, Nguyen, C., Wong, S., Plummer, J. 1994; 41: 970-977
  • Application of Selective Epitaxial Silicon and Chemo-Mechanical Polishing to Bipolar Transistors IEEE Transactions on Electron Devices Nguyen, C., Kuehne, S., Wong, S., Garling, L., Drowley, C. 1994; 41: 2343-2350
  • ELECTROLESS CU FOR VLSI MRS BULLETIN CHO, J. S., Kang, H. K., Wong, S. S., SHACHAMDIAMAND, Y. 1993; 18 (6): 31-38
  • A Selective CVD Tungsten-Strapped Polysilicon Local Interconnection Technology IEEE Transactions on Electron Devices Lee, V., Kuehne, S., Nguyen, C., Beiley, M., Wong, S. 1993; 40: 1223-1230
  • THE EFFECTS OF HOT CARRIERS GENERATION ON THE OPERATION OF NEIGHBORING DEVICES AND CIRCUITS 1993 SYMPOSIUM ON VLSI TECHNOLOGY Sakui, K., Wong, S. S., Wooley, B. A. 1993: 11-12
  • Serial-Parallel FFT Array Processor IEEE Transactions on Signal Processing You, J., Wong, S. 1993; 41: 1472-1476
  • ELECTROMIGRATION PROPERTIES OF ELECTROLESS PLATED CU METALLIZATION IEEE ELECTRON DEVICE LETTERS Kang, H. K., CHO, J. S., Wong, S. S. 1992; 13 (9): 448-450
  • A Planar Interconnection Technology Utilizing the Selective Deposition of Tungsten – Multilevel Implementation IEEE Transactions on Electron Devices Thomas, D., Wong, S. 1992; 39: 901-907
  • Complementary Lateral Bipolar Transistor Action in a CMOS Technology IEEE Electron Device Letters Verdonckt-Vandebroek, S., You, J., Woo, J., Wong, S. 1992; 13: 312-313
  • Measurement of Lateral Dopant Diffusion in Thin Silicide Layers IEEE Transactions on Electron Devices Chu, C., Saraswat, K., Wong, S. 1992; 60: 2333-2340
  • Electromigration Performance of Electroless Plated Copper / Pd-Silicide Metallization IEEE Electron Device Letters Tao, J., Cheung, N., Hu, C., Kang, H., Wong, S. 1992; 13: 433-435
  • AlGaAs/GaAs-Based Triangular-Shaped Ring Ridge Laser Applied Physics Letters Behfar-Rad, A., Ballantyne, J., Wong, S. 1992; 60: 1658-1660
  • Monolithic AlGaAs/GaAs Single Quantum Well Ridge Lasers Fabricated with Dry-Etched Facets and Ridges IEEE Journal of Quantum Electronics Behfar-Rad, A., Wong, S. 1992; 28: 1227-1231
  • A Planar Interconnection Technology Utilizing the Selective Deposition of Tungsten – Process Characterization IEEE Transactions on Electron Devices Thomas, D., Behfar-Rad, A., Comeau, G., Skvarla, M., Wong, S. 1992; 39: 893-900
  • HIGH-GAIN LATERAL BIPOLAR ACTION IN A MOSFET STRUCTURE IEEE TRANSACTIONS ON ELECTRON DEVICES VERDONCKTVANDEBROEK, S., Wong, S. S., Woo, J. C., Ko, P. K. 1991; 38 (11): 2487-2496
  • Implantation to Suppress Parasitic Bipolar Action in CMOS IEEE Transactions on Electron Devices Ratanaphanyarat, S., Renteln, P., Drowley, C., Wong, S. 1991; 38: 355-364
  • Series Resistance of Devices with Submicrometer Source/Drain Areas IEEE Electron Device Letters Lee, V., Biellak, S., Cho, J., Wong, S. 1991; 12: 664-666
  • Technology Limitations for N+/P+ Polycide Gate CMOS Due to Lateral Dopant Diffusion in Silicide/Polysilicon Layers IEEE Electron Device Letters Chu, C., Chin, G., Saraswat, K., Wong, S., Dutton, R. 1991; 12: 696-698
  • Etched-Facet AlGaAs Triangular-Shaped Ring Lasers with Output Coupling Applied Physics Letters Behfar-Rad, A., Ballantyne, J., Wong, S. 1991; 59: 1395-1397
  • A COMPLEMENTARY HIGH-CURRENT GAIN TRANSISTOR FOR USE IN A CMOS COMPATIBLE TECHNOLOGY PROCEEDINGS OF THE 1990 BIPOLAR CIRCUITS AND TECHNOLOGY MEETING VERDONCKTVANDEBROEK, S., Woo, J. C., Wong, S. S. 1990: 82-85
  • Hot-Electron-Induced Minority-Carrier Generation in Bipolar Junction Transistors IEEE Electron Device Letters Ishiuchi, H., Tamba, N., Shott, J., Knorr, C., Wong, S. 1990; 11: 490-492
  • A Self-Aligned Nitrogen Implantation Process (SNIP) to Minimize Field Oxide Thinning Effect in Submicrometer LOCOS IEEE Transactions on Electron Devices Ratanaphanyarat, S., Wong, S. 1990; 37: 1948-1958
  • Effect of Cladding Layer Thickness on the Performance of GaAs-AlGaAs Graded Index Separate Confinement Heterostructure Single Quantum-Well Lasers IEEE Journal of Quantum Electronics Behfar-Rad, J., Shealy, Chinn, S., Wong, S. 1990; 26: 1476-1480
  • Efficient Coupling of Optical Fiber to Silicon Photodiode IEEE Electron Device Letters Baltuch, O., Lee, V., Wong, S. 1989; 10: 255-256
  • Masking Considerations in Chemically Assisted Ion Beam Etching of GaAs/AlGaAs Laser Structures Journal of Electrochemical Society Behfar-Rad, A., Wong, S., Davis, R., Wolf, E. 1989; 136: 779-782
  • A Framework to Evaluate Technology and Device Design Enhancements for MOS Integrated Circuits IEEE Journal of Solid-State Circuits Sodini, C., Wong, S., Ko, P. 1989; 24: 118-127
  • Rectangular and L-Shaped GaAs/AlGaAs Lasers with Very High Quality Etched Facets Applied Physics Letters Behfar-Rad, A., Wong, S., Ballantyne, J., Soltz, B., Harding, C. 1989; 54: 493-495
  • Oxygen Implantation for Internal Gettering and Reducing Carrier Lifetime Applied Physics Letters Weiner, D., Wong, S., Drowley, C. 1987; 50: 986-988
  • HPSAC – A Silicided Amorphous-Silicon Contact and Interconnect Technology for VLSI IEEE Transactions on Electron Devices Wong, S., Chen, D., Merchant, P., Cass, T., Amano, J., Chiu, K. 1987; 34: 587-592
  • Specific Contact Resistivity of TiSi2 to p+ and n+ Junctions IEEE Electron Device Letters Hui, J., Wong, S., Moll, J. 1985; 6: 479-481
  • CMOS Well Drive-In in NH3 for Reduced Lateral Diffusion and Heat Cycle IEEE Electron Device Letters Wong, S., Ekstedt, T. 1985; 6: 659-661
  • Anodic Nitridation of Silicon and Silicon Dioxide IEEE Transactions on Electron Devices Wong, S., Oldham, W. 1985; 32: 978-982
  • A Multiwafer Plasma System for Anodic Nitridation and Oxidation IEEE Electron Device Letters Wong, S., Oldham, W. 1984; 5: 175-177
  • A JMOS Transistor Fabricated with 100-Å Low-Pressure Nitrided-Oxide Gate Dielectric IEEE Transactions on Electron Devices Sodini, C., Wong, S., Ekstedt, T., Grinolds, H., Oldham, W. 1984; 31: 17-21
  • Low Pressure, Nitrided-Oxide as a Thin Gate Dielectric for MOSFETs Journal of Electrochemical Society Wong, S., Sodini, C., Ekstedt, T., Grinolds, H., Jackson, K., Kwan, S. 1983; 130: 1139-1144
  • Sealed-Interface Local Oxidation Technology Transactions on Electron Devices Hui, J., Chiu, T., Wong, S., Oldham, W. 1982; 29: 554-561
  • Selective Oxidation Technologies for High Density MOS IEEE Electron Device Letters Hui, J., Chiu, T., Wong, S., Oldham, W. 1981; 2: 244-247
  • A 64 Kbit MOS Dynamic RAM with Novel Memory Capacitor IEEE Journal of Solid-State Circuits Smith, F., Yau, R., Lee, I., Wong, S., Embrathiry, M. 1980; 15: 184-189
  • Synthesis of Piecewise-Linear Networks IEE Journal of Electronic Circuits and Systems Chua, L., Wong, S. 1978; 2: 102-108

Conference Proceedings


  • Trusted Integrated Chips Integrating Non-Volatile Memory with CMOS Provine, J., Wong, H., Wong, S., Mitra, S. 2013
  • Scaling Challenges for the Cross-point Resistive Memory Array to the Single-digit-nm Node – An Interconnect Perspective Liang, S., Yip, S., Wong, H., S., Wong, P. 2012
  • Nonvolatile 3D-FPGA with Monolithically Stacked RRAM-Based Configuration Memory Yang-Liauw, Y., Zhang, Z., Kim, W., El-Gamal, A., Wong, S. 2012
  • A 60GHz Digitally Controlled RF Beamforming Array in 65nm CMOS with Off-Chip Antennas Lin, S., Ng, K., Wong, H., Luk, K., Wong, S., Poon, A. 2011
  • Forming-Free Nitrogen-Doped AlOx RRAM with Sub-μA Programming Current Kim, W., Park, S., I., Zhang, Z., Yang-Liauw, Y., Sekar, D., Wong, H., S. P. 2011
  • 3D Field Programmable Gate Array Yang-Liauw, Y., Crnororac, F., Chen, E., Jung, W., Kim, W., Park, S., Wong, S. S. 2011
  • Semiconductor crystal islands for three-dimensional integration Crnogorac, F., Wong, S., Pease, R. F. A V S AMER INST PHYSICS. 2010: C6P53-C6P58

    View details for DOI 10.1116/1.3511473

    View details for Web of Science ID 000285015200113

  • Leakage Current Analysis of Lateral p+/n Ge Based Diode Activated at Low Temperature for Three-Dimensional Integrated Circuit (3D-ICs) Jung, W., Park, J., Kuzum, D., Kim, W., Wong, S., Saraswat, K. 2010
  • Low-Power 48-GHz CMOS VCO and 60-GHz CMOS LNA for 60-GHz Dual-Conversion Receiver Lin, Y., Chang, T., Chen, C., Chen, C., Yang, H., Wong, S. 2009
  • A High-Performance 3D-SRAM Architecture Wong, S., Nho, H. 2009
  • A Low-Power V-Band CMOS Low Noise Amplifier using Current Sharing Technique Yang, H., Lin, Y., Chen, C., Wong, S. 2008
  • Monolithic 3D Integrated Circuits Wong, S., El-Gamal, A., Griffin, P., Nishi, Y., Pease, F., Plummer, J. 2008
  • Performance benefits of monolithically stacked 3-D FPGA Lin, M., El Gamal, A., Lu, Y., Wong, S. IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. 2007: 216-229
  • A Fully Integrated RF Front-End with Independent RX/TX Matching and +20dbm Output Power for WLAN Applications Chang, R., Weber, D., Lee, M., Su, D., Vleugels, K., Wong, S. 2007
  • Nonvolatile SRAM Cell Wang, W., Gibby, A., Wang, Z., Fujita, S., Griffin, P., Nishi, Y., Wong, S. S. 2006
  • Performance Benefits of Monolithically Stacked 3D-FPGA Lin, M., El Gamal, A., Lu, Y., Wong, S. 2006
  • A 10-GHz global clock distribution using coupled standing-wave oscillators O'Mahony, F., Yue, C. P., Horowitz, M. A., Wong, S. S. IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. 2003: 1813-1820
  • Near speed-of-light signaling over on-chip electrical interconnects Chang, R. T., Talwalkar, N., Yue, C. P., Wong, S. S. IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. 2003: 834-838
  • An Integrated 5.2GHz CMOS T/R Switch with LC-Tuned Substrate Bias Talwalkar, N., Yue, C., Wong, S. 2003
  • Mechanism for Early Failure in Cu Dual Damascene Structure Kim, D., Wong, S. 2003
  • 10GHz Clock Distribution Using Coupled Standing-Wave Oscillators O’Mahony, F., Yue, C., Wong, S. 2003
  • A 0-dB IL 2140 +/- 30 MHz bandpass filter utilizing Q-enhanced spiral inductors in standard CMOS Soorapanth, T., Wong, S. S. IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. 2002: 579-586
  • Near Speed-of-Light On-Chip Electrical Interconnect Chang, R., Yue, C., Wong, S. 2002
  • Evidence of Dislocation Loops as a Driving Force for Self Annealing in Electroplated Cu Films Lee, H., Lopatin, S.., Marshall, A., Wong, S. 2001
  • Microanalysis of VLSI Interconnect Failure Modes under Short-Pulse Stress Conditions Banerjee, K., Mehrota, A., Hunter, W., Saraswat, K., Wong, S., Goodson, K. 2000
  • Quantitative Projections of Reliability and Performance for Low-k/Cu Interconnect Systems Banerjee, K., Kim, D., Amerasekera, A., Hu, C., Goodson, K., Wong, S. 2000
  • On-Chip Inductance Modeling of VLSI Interconnects Qi, X., Kleveland, B., Yu, Z., Wong, S., Dutton, R. 2000
  • Correlation of Stress and Texture Evolution During Self- and Thermal Annealing of Electroplated Cu Films Lee, H., Lopatin, S., Wong, S. 2000
  • Ultra-low resistance, through-wafer via (TWV) technology and its applications in three dimensional structures on silicon Soh, H. T., Yue, C. P., McCarthy, A., Ryu, C., Lee, T. H., Wong, S. S., Quate, C. F. JAPAN SOC APPLIED PHYSICS. 1999: 2393-2396
  • Monolithic CMOS Distributed Amplifier and Oscillator Kleveland, B., Diaz, C., Vook, D., Madden, L., Lee, T., Wong, S. 1999
  • A Study on Substrate Effects of Silicon-Based RF Passive Components Yue, C., Wong, S. 1999
  • Line Inductance Extraction and Modeling in a Real Chip with Power Grid Kleveland, B., Qi, X., Madden, L., Dutton, R., Wong, S. 1999
  • Effects of Plating Current Density and Solution Additive on the Microstructure and Recrystallization Rate of Electroplated Copper Films Lee, H., Lopatin, S., Kim, D., Dubin, V., Wong, S. 1999
  • On-chip spiral inductors with patterned ground shields for Si-based RF IC's Yue, C. P., Wong, S. S. IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. 1998: 743-752
  • Temperature-dependent thermal conductivity of single-crystal silicon layers in SOI substrates Asheghi, M., Touzelbaev, M. N., Goodson, K. E., Leung, Y. K., Wong, S. S. ASME-AMER SOC MECHANICAL ENG. 1998: 30-36
  • Modeling and Characterization of On-Chip Transformer Mohan, S., Yue, C., Hershenson, M., Mar, Wong, S., Lee, T. 1998
  • Effect of Seed Layer Texture and Surface Roughness on the Microstructure of Electroplated Copper Film Lee, H., Lopatin, S., Nogami, T., Wong, S. 1998
  • Copper Drift in Low-K Polymer Dielectrics for ULSI Metallization Loke, A., Wetzel, J., Ryu, C., Wong, S. 1998
  • Electromigration of Submicron Damascene Copper Ryu, C., Kwon, K., Loke, A., Dubin, V., Kavari, R., Ray, G., Wong, S. S. 1998
  • Copper Electroplating for Damascene ULSI Interconnects Dubin, V., Chen, S., Cheung, R., Ryu, C., Wong, S. 1998
  • Lateral Emitter Controlled Thyristor (LECT) on SOI Zhao, Y., Huang, A., Leung, Y., Wong, S. 1998
  • 50 Ghz Interconnect Design in Standard Silicon Technology Kleveland, B., Wong, S., Lee, T. 1998
  • Analysis and Optimization of Accumulation-Mode Varactor for RF ICs Soorapanth, T., Yue, C., Shaeffer, D., Lee, T., Wong, S. 1998
  • Copper Drift in Low-K Polymer Dielectrics for ULSI Metallization Loke, A., Wetzel, J., Ryu, C., Lee, W., Wong, S. 1998
  • Microstructure and Mechanical properties of Electroplated Cu Films for Damascene ULSI Metallization Dubin, V., Morales, G., Ryu, C., Wong, S. 1997
  • Characteristics of Ta as an Underlayer for Cu Interconnect Kwon, K., Lee, H., Ryu, C., Sinclair, R., Wong, S. 1997
  • A Novel Methodology for Reliability Studies in Fully Depleted SOI MOSFETs Banna, S., Chan, P., Wong, S., Fung, S., Ko, P. 1997
  • Electrical Stability of Low-K Polyimide/TEOS Interface Loke, A., Wetzel, J., Stankus, J., Angyal, M., Gregory, R., Abramowitz, P., Wong, S. S. 1997
  • A Quasi-Stadium Semiconductor Laser Fukishima, Beillak, S., A., Sun, Y., Fanning, C., G., Cheng, Y., Wong, S. 1997
  • On-Chip Spiral Inductors with Patterned Ground Shields for Si-Based RF IC’s Yue, C., Wong, S. 1997
  • Effect of Texture on the Electromigration of CVD Copper Ryu, C., Loke, A., Nogami, T., Wong, S. 1997
  • A physical model for planar spiral inductors on silicon Yue, C. P., Ryu, C. S., Lau, J., Lee, T. H., Wong, S. S. IEEE. 1996: 155-158
  • Lateral IGBT on Thin SOI for High-Speed Power IC Applications Leung, Y., Kuehne, S., Huang, V., Nguyen, C., Paul, A., Plummer, J., Wong, S. S. 1996
  • Deep Sub-Micron SOI MOSFET with Buried Body Strap Kuehne, S., Chan, A., Nguyen, C., Wong, S. 1996
  • Active Substrate Membrane Probe Card Leung, J., Zargari, M., Wooley, B., Wong, S. 1996
  • The Combined Effects of Chemical-Mechanical Polishing and Hydrogenation on Poly-Si TFT’s Chan, A., Nguyen, C., Ko, P., Wong, S. 1996
  • CMOS Latchup Characterization for LDMOS/LIGBT Power Integrated Circuits Chan, W., Sin, J., Mok, P., Wong, S. 1996
  • Temperature-Dependent Thermal Conductivity of Single Crystal Silicon Layers in SOI Substrates Asheghi, M., Touzelbaev, M., Goodson, K., Leung, Y., Wong, S. 1996
  • Grain Structure of CVD Copper Films Ryu, C., Loke, A., Wong, S. 1996
  • Formation and high frequency CV-measurements of aluminum aluminum nitride 6H silicon carbide structures Zetterling, C. M., Wongchotigul, K., Spencer, M. G., Harris, C. I., Wong, S. S., Ostling, M. MATERIALS RESEARCH SOCIETY. 1996: 667-672
  • A BICMOS active substrate probe card technology for digital testing Zargari, M., Leung, J. T., Wong, S. S., Wooley, B. A. I E E E. 1996: 308-309
  • Evidence of Reduced Maximum Lateral E-Field in Quasi-SOI MOSFETs Ng, C., Nguyen, C., Wong, S. 1995
  • Electrical and Thermal Study of Membrane Multi-Chip Module Systems Cheng, W., Wong, S. 1995
  • Self-heating effect in lateral DMOS on SOI Leung, Y. K., Suzuki, Y., Goodson, K. E., Wong, S. S. I E E E. 1995: 136-140
  • Active substrate membrane probe card Leung, J., Zargari, M., Wooley, B. A., Wong, S. S. IEEE. 1995: 709-712
  • Non-Radial Non-Uniformity in Chemo-Mechanical Polishing Huang, V., Nguyen, C., Chan, A., Ling, C., Wong, S. 1995
  • An Effective Cross-Talk Isolation Structure for Power IC Applications Chan, W., Sin, J., Wong, S. 1995
  • Influence of Parasitic Capacitances on Switching Characteristics of SOI-LDMOSs Suzuki, Y., Leung, Y., Wong, S. 1995
  • Cross-Talk Prevention for Power Integrated Circuits Chan, W., Wong, F., Sin, J., Wong, S. 1995
  • Monolithic Stable-Resonator Semiconductor Laser Biellak, S., Sun, Y., Wong, S., Siegman, A. 1995
  • Microstructure of CVD Copper on TiW Ryu, C., Lee, H., Ostling, M., Wong, S. 1994
  • High-Power Diffraction-Limited Reactive-Ion-Etched Unstable-Resonator Diode Lasers Biellak, S., Fanning, G., Sun, Y., Wong, S., Siegman, A. 1994
  • Development of an Active Membrane Probe Card Leung, J., Beiley, M., Zargari, M., Wong, S. 1993
  • Membrane Multi-Chip Module Technology on Si Cheng, W., Beiley, M., Wong, S. 1993
  • First Direct Beta Measurement for Parasitic Lateral Bipolar Transistors in Fully Depleted SOI MOSFET’s Ploeg, E., Ver, Nguyen, C., Kistler, N., Wong, S., Woo, J., Plummer, J. 1993
  • Reliability of CVD Cu Buried Interconnections Cho, J., Kang, H., Ryu, C., Wong, S. 1993
  • The Effects of Hot Carriers Generation on the Operation of Neighboring Devices and Circuits Sakui, K., Wong, S., Wooley, B. 1993
  • Grain Structure and Electromigration Properties of CVD Cu Metallization Kang, H., Asano, I., Ryu, C., Wong, S., Norman, J. 1993
  • CVD Cu Interconnections for VLSI Metallization Cho, J., Kang, H., Gross, M., Wong, S. 1993
  • Electromigration Properties of Electroless and CVD Cu Metallization Kang, H., Cho, J., Asano, I., Wong, S. 1992
  • Array probe card Beiley, M., Ichishita, F., Nguyen, C., Wong, S. 1992
  • Micro-Machined Array Probe Card Beiley, M., Wong, S. 1992
  • CVD Cu Interconnections for ULSI Cho, J., Kang, H., Asano, I., Wong, S. 1992
  • Monolithic Integration of GaAs and Si Bipolar Devices for Optical Interconnect Systems Nasserbakht, G., Adkisson, J., Wooley, B., Harris, J., Kamins, T., Wong, S. 1992
  • Quasi-SOI MOSFETs Using Selective Epitaxy and Polishing Nguyen, C., Kuehne, S., Wong, S., Renteln, P. 1992
  • Al-Cu Interconnection Formed by Diffusing Selectively Deposited CVD Cu into Patterned Al Lines Kang, H., Asano, I., Wong, S., Norman, J. 1992
  • Single-Poly Bipolar Transistor with Selective Epitaxial Silicon and Chemo-Mechanical Polishing Nguyen, C., Kuehne, S., Wong, S. 1992
  • Copper Interconnection with Tungsten Cladding for ULSI Cho, J., Kang, H., Beiley, M., Wong, S., Ting, C. 1991
  • Characterization of Lateral Bipolar Transistor Structure Theodore, D., Verdonckt-Vandebroek, S., Carter, C., Wong, S. 1990
  • Traveling-Wave Operation in a Triangular-Shaped Monolithic Semiconductor Ring Ridge Laser Behfar-Rad, A., Wong, S., Ballantyne, J. 1990
  • A High Performance Single Chip FFT Array Processor for Wafer Scale Integration You, J., Wong, S. 1990
  • A Complementary High Gain Transistor for Use in a CMOS Compatible Technology Verdonckt-Vandebroek, S., Woo, J., Wong, S. 1990
  • Fully Monolithic Self-Aligned GaAs/AlGaAs Single Quantum Well Ridge Laser Behfar-Rad, A., Wong, S. 1990
  • Characterization of Lateral Dopant Diffusion in Silicides Chu, C., Saraswat, K., Wong, S. 1990
  • Characterization of Lateral Dopant Diffusion in Silicides Chu, C., Saraswat, K., Wong, S. 1990
  • Hot Electron Induced Minority Carrier Generation in Bipolar Junction Transistors Ishiuchi, H., Tamba, N., Shott, J., Knorr, C., Wong, S. 1989
  • Lateral NPN Bipolar Transistor for High Current Gain Applications at Reduced Temperatures Woo, J., Wong, S., Verdonckt-Vandebroek, S., Ko, P., Terrill, K., Vasudev, P. 1989
  • A Multilevel Tungsten Interconnect Technology Thomas, D., Wong, S., Dinsmore, D., Soave, R. 1988
  • A Triangular-Shaped GaAs/AlGaAs Laser Behfar-Rad, A., Wong, S. 1988
  • A Selective CVD Tungsten Local Interconnect Technology Lee, V., Verdonckt, S., Wong, S. 1988
  • High Gain Lateral Bipolar Transistor Verdonckt, S., Wong, S., Ko, P. 1988
  • Multilevel Tungsten Interconnect Technology Wong, S., Thomas, D., Verdonckt, S. 1988
  • Semiconductor Lasers with Very High Quality Etched Facets Behfar-Rad, A., Wong, S. 1987
  • Oxygen Implantation for Improved CMOS Latchup Immunity Ratanaphanyarat, S., Verdonckt, S., Wong, S., Drowley, C. 1987
  • Oxygen Implantation for Lifetime Control Weiner, D., Wong, S., Drowley, C. 1986
  • A Planar Multi-Level Tungsten Interconnect Technology Thomas, D., Wong, S. 1986
  • CMOS Well Drive-In in NH3 for Reduced Lateral Diffusion and Heat Cycle Wong, S., Ekstedt, T. 1985
  • Anodic Nitridation of Silicon-Dioxide Wong, S., Oldham, W. 1984
  • Enhancement of Hot-Electron Currents in Graded-Gate-Oxide (GGO) MOSFETs Ko, P., Tam, S., Hu, C., Wong, S., Sodini, C. 1984
  • Elevated Source/Drain MOSFET Wong, S., Bradbury, D., Chen, D., Chiu, K. 1984
  • A New Device Interconnect Scheme for Sub-Micron VLSI Chen, D., Wong, S., Voorde, P., Vande, Merchant, P., Cass, T., Amano, J. 1984
  • Anodic Si3N4 Grown in a New Plasma Reactor Wong, S., Oldham, W., Grinolds, H. 1983
  • Composition and Electrical Properties of Nitrided-Oxide and Re-Oxidized Nitrided-Oxide Wong, S., Kwan, S., Grinolds, H., Oldham, W. 1983
  • Electrical Properties of MOS Devices Made with SILO Technology Hui, J., Chiu, T., Wong, S., Oldham, W. 1982
  • Nitrided-Oxide, Thin Gate Dielectric for MOS Devices Sodini, C., Wong, S., Ekstedt, T. 1982