
Subhasish Mitra
William E. Ayer Professor of Electrical Engineering and Professor of Computer Science
Web page: http://web.stanford.edu/people/subh
Bio
Subhasish Mitra holds the William E. Ayer Endowed Chair Professorship in the Departments of Electrical Engineering and Computer Science at Stanford University. He directs the Stanford Robust Systems Group, serves on the leadership team of the Microelectronics Commons AI Hardware Hub funded by the US CHIPS and Science Act, leads the Computation Focus Area of the Stanford SystemX Alliance, and is the Associate Chair (Faculty Affairs) of Computer Science. His research ranges across Robust Computing, NanoSystems, Electronic Design Automation (EDA), and Neurosciences. Results from his research group have influenced almost every contemporary electronic system and have inspired significant government and research initiatives in multiple countries. He has held several international academic appointments — the Carnot Chair of Excellence in NanoSystems at CEA-LETI in France, Invited Professor at EPFL in Switzerland, and Visiting Professor at the University of Tokyo in Japan. Prof. Mitra also has consulted for major technology companies including AMD (XIlinx), Cisco, Google, Intel, Merck (EMD Electronics), and Samsung.
In the field of Robust Computing, he has created many key approaches for circuit failure prediction, on-line diagnostics, QED system validation, soft error resilience, and X-Compact test compression. Their adoption by industry is growing rapidly, in markets ranging from cloud computing to automotive systems, under various names (System Lifecycle Management, Predictive Health Monitoring, In-System Test Architecture, In-field Scan). His X-Compact approach has proven essential to cost-effective manufacturing and high-quality testing of almost all 21st century systems. X-Compact and its derivatives enabled billions of dollars of cost savings across the industry.
In the field of NanoSystems, with his students and collaborators, he demonstrated several firsts: the first NanoSystems hardware among all beyond-silicon nanotechnologies for energy-efficient computing (the carbon nanotube computer), the first 3D NanoSystem with computation immersed in data storage, the first published end-to-end computing systems using resistive memories (Resistive RAM-based non-volatile computing systems delivering 10-fold energy efficiency versus embedded flash), and the first monolithic 3D integration combining heterogeneous logic and memory technologies in a silicon foundry. These received wide recognition: cover of NATURE, several Highlights to the US Congress, and highlight as "important scientific breakthrough" by news organizations worldwide.
Prof. Mitra's honors include the Harry H. Goode Memorial Award (by IEEE Computer Society for outstanding contributions in the information processing field), Newton Technical Impact Award in EDA (test-of-time honor by ACM SIGDA and IEEE CEDA), the University Researcher Award (by Semiconductor Industry Association and Semiconductor Research Corporation to recognize lifetime research contributions), the EDAA Achievement Award (by European Design and Automation Association, given to individuals who made outstanding contributions to electronic design, automation and testing in their life), the Intel Achievement Award (Intel’s highest honor), and the Distinguished Alumnus Award from the Indian Institute of Technology, Kharagpur. He and his students have published over 15 award-winning papers across 5 topic areas (technology, circuits, EDA, test, verification) at major venues including the Design Automation Conference, International Electron Devices Meeting, International Solid-State Circuits Conference, International Test Conference, Symposia on VLSI Technology/VLSI Circuits, and Formal Methods in Computer-Aided Design. Stanford undergraduates have honored him several times "for being important to them." He is a Fellow of the Association for Computing Machinery (ACM) and the Institute of Electrical and Electronics Engineers (IEEE), and a Foreign Member of Academia Europaea.
Academic Appointments
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Professor, Electrical Engineering
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Professor, Computer Science
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Member, Bio-X
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Member, Wu Tsai Neurosciences Institute
Administrative Appointments
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Associate Chair, Faculty Affairs, Department of Computer Science, Stanford University (2021 - Present)
Honors & Awards
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Achievement Award, lifetime honor for outstanding contributions to design/design automation/testing, European Design and Automation Association (EDAA) (2025)
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Roger A. Haken Best Student Paper Award, IEEE International Electron Devices Meeting (with Stanford advisee) (2024)
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Top Picks in Hardware Security, IEEE (2024)
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Best Student Paper Award, Symposium on VLSI Technology (with Stanford advisees) (2023)
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Top Picks in Test and Reliability, IEEE (2023)
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William E. Ayer Endowed Chair Professorship, Stanford University (2023)
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Distinguished Alumnus Award, Indian Institute of Technology, Kharagpur (2022)
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Harry H. Goode Memorial Award, IEEE Computer Society (2022)
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Best Student Paper Award, Symposium on VLSI Circuits (with Stanford advisees) (2021)
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Foerign Member, Academia Europaea (2021)
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University Researcher Award for lifetime research contributions to the U.S. semiconductor industry, Jointly by Semiconductor Industry Association (SIA) and Semiconductor Research Corporation (SRC) (2021)
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Honorable Mention Paper, Formal Methods in Computer-Aided Design (2020)
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Humboldt Prize (Humboldt Research Award), Alexander von Humboldt Foundation, Germany (2019)
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Faculty Research Award, Google (2018)
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Ten Year Retrospective Most Influential Paper Award, IEEE International Conference on Computer-Aided Design (2018)
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Carnot Chair of Excellence in NanoSystems, CEA-LETI, Grenoble, France (2017-2020)
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Best of SELSE, IEEE International Conference on Dependable Systems and Networks (2016)
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Special recognition for carbon nanotube research, SEMI, the global microelectronics industry association (2016)
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Best Paper Award, IEEE International Test Conference (2015)
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Technical Excellence Award, Semiconductor Research Corporation (SRC) (2015)
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A. Richard Newton Technical Impact Award in Electronic Design Automation (test of time honor), ACM SIGDA & IEEE CEDA (2014)
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Fellow, Association for Computing Machinery (ACM) (2014)
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Fellow, Institute of Electrical and Electronics Engineers (IEEE) (2013)
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Jack Raper Award for Outstanding Technology Directions Paper, IEEE International Solid-State Circuits Conference (2013)
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Kavli Foundation Fellow, United States National Academy of Sciences (2013)
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World Economic Forum Young Scientist, World Economic Forum (2013)
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Chambers Faculty Scholar, Stanford School of Engineering (2011)
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Best Paper Award, IEEE VLSI Test Symposium (2010)
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Best Student Paper Award, IEEE International Test Conference (with Stanford advsees) (2010)
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Research Highlight, Communications of the ACM (2010)
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Honored by graduating seniors as a Stanford professor who had been important to them, Stanford University School of Engineering (2009-2021)
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Invited Participant, National Academy of Engineering, US Frontiers of Engineering Symposium (2009)
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Okawa Foundation Research Grant, Okawa Foundation for Information and Telecommunications, Japan (2009)
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Best Paper Award, ACM/IEEE Design Automation Conference (2008)
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Best Student Paper Award, Symposium on VLSI Technology (with Stanford advisees) (2008)
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Outstanding New Faculty Award, ACM SIGDA (2008)
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Presidential Early Career Award for Scientists and Engineers (PECASE), The White House, the United States government (2008)
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IBM Faculty Award, IBM (2006, 2007, 2008)
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Terman Fellow, Stanford University (2006)
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Best Paper Award, Intel Design and Test Technology Conference (2005)
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Divisional Recognition award (for Breakthrough Soft Error Protection Technology), Intel Corporation (2005)
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Donald O. Pederson Outstanding Paper Award, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2005)
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Inaugural S. Seshu Scholar Lecturer, Coordinated Science Laboratory, University of Illinois at Urbana-Champaign (2005)
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Intel Achievement Award, Intel’s highest corporate honor, Intel Corporation (For the development and deployment of a breakthrough test compression technology) (2004)
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Divisional Recognition award, Intel Corporation (For Development and Proliferation of Industry Leading Response Compactor Design) (2002)
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Silver medal recipient for highest rank among all M. Tech students, Indian Institute of Technology, Kharagpur (1996)
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Cadence Fellowship, Indian Institute of Technology, Kharagpur (1994-1996)
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Gold medals for Rank 1 in engineering during all four years of undergraduate study, Jadavpur University, India (1994)
Program Affiliations
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Stanford SystemX Alliance
All Publications
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CLEAR Cross-Layer Resilience: A Retrospective
IEEE DESIGN & TEST
2025; 42 (3): 74-85
View details for DOI 10.1109/MDAT.2024.3483028
View details for Web of Science ID 001471147300009
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Monolithic 3-D Integration of Diverse Memories: Resistive Switching (RRAM) and Gain Cell (GC) Memory Integrated on Si CMOS
IEEE TRANSACTIONS ON ELECTRON DEVICES
2025
View details for DOI 10.1109/TED.2025.3556113
View details for Web of Science ID 001480280000001
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Three-Independent-Gate Transistors: The Swiss Army Knife of Devices [Special Section on 2025 IEEE Kirchhoff Award]
IEEE CIRCUITS AND SYSTEMS MAGAZINE
2025; 25 (2): 17-22
View details for DOI 10.1109/MCAS.2025.3531819
View details for Web of Science ID 001492691500008
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Omni 3D: BEOL-Compatible 3-D Logic With Omnipresent Power, Signal, and Clock
IEEE TRANSACTIONS ON ELECTRON DEVICES
2025; 72 (4): 2038-2045
View details for DOI 10.1109/TED.2025.3537955
View details for Web of Science ID 001457760300047
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MINOTAUR: A Posit-Based 0.42-0.50-TOPS/W Edge Transformer Inference and Training Accelerator
IEEE JOURNAL OF SOLID-STATE CIRCUITS
2025; 60 (4): 1311-1323
View details for DOI 10.1109/JSSC.2025.3545731
View details for Web of Science ID 001456403900020
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Understanding responses to multi-electrode epiretinal stimulation using a biophysical model.
Journal of neural engineering
2024
Abstract
Neural interfaces are designed to evoke specific patterns of electrical activity in populations of neurons by stimulating with many electrodes. However, currents passed simultaneously through multiple electrodes often combine nonlinearly to drive neural responses, making evoked responses difficult to predict and control. This response nonlinearity could arise from the interaction of many excitable sites in each cell, any of which can produce a spike. However, this multi-site activation hypothesis is difficult to verify experimentally.We developed a biophysical model to study retinal ganglion cell (RGC) responses to multi-electrode stimulation and validated it using data collected from ex vivo preparations of the macaque retina using a microelectrode array (512 electrodes; 30µm pitch; 10µm diameter).First, the model was validated by using it to reproduce essential empirical findings from single-electrode recording and stimulation, including recorded spike voltage waveforms at multiple locations and sigmoidal responses to injected current. Then, stimulation with two electrodes was modeled to test how the positioning of the electrodes relative to the cell affected the degree of response nonlinearity. Currents passed through pairs of electrodes positioned near the cell body or far from the axon (>40 µm) exhibited approximately linear summation in evoking spikes. Currents passed through pairs of electrodes close to the axon summed linearly when their locations along the axon were similar, and nonlinearly otherwise. Over a range of electrode placements, several localized spike initiation sites were observed, and the number of these sites covaried with the degree of response nonlinearity. Similar trends were observed for three-electrode stimuli. All of these trends in the simulation were consistent with experimental observations.These findings support the multi-site activation hypothesis for nonlinear activation of neurons, providing a biophysical interpretation of previous experimental results and potentially enabling more efficient use of multi-electrode stimuli in future neural implants.
View details for DOI 10.1088/1741-2552/ada1fe
View details for PubMedID 39705808
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VLSI Test and Trust Roundtable
IEEE DESIGN & TEST
2024; 41 (6): 84-94
View details for DOI 10.1109/MDAT.2024.3444745
View details for Web of Science ID 001343332400004
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Precise control of neural activity using dynamically optimized electrical stimulation.
eLife
2024; 13
Abstract
Neural implants have the potential to restore lost sensory function by electrically evoking the complex naturalistic activity patterns of neural populations. However, it can be difficult to predict and control evoked neural responses to simultaneous multi-electrode stimulation due to nonlinearity of the responses. We present a solution to this problem and demonstrate its utility in the context of a bidirectional retinal implant for restoring vision. A dynamically optimized stimulation approach encodes incoming visual stimuli into a rapid, greedily chosen, temporally dithered and spatially multiplexed sequence of simple stimulation patterns. Stimuli are selected to optimize the reconstruction of the visual stimulus from the evoked responses. Temporal dithering exploits the slow time scales of downstream neural processing, and spatial multiplexing exploits the independence of responses generated by distant electrodes. The approach was evaluated using an experimental laboratory prototype of a retinal implant: large-scale, high-resolution multi-electrode stimulation and recording of macaque and rat retinal ganglion cells ex vivo. The dynamically optimized stimulation approach substantially enhanced performance compared to existing approaches based on static mapping between visual stimulus intensity and current amplitude. The modular framework enabled parallel extensions to naturalistic viewing conditions, incorporation of perceptual similarity measures, and efficient implementation for an implantable device. A direct closed-loop test of the approach supported its potential use in vision restoration.
View details for DOI 10.7554/eLife.83424
View details for PubMedID 39508555
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Lossless Phonon Transition Through GaN-Diamond and Si-Diamond Interfaces
ADVANCED ELECTRONIC MATERIALS
2024
View details for DOI 10.1002/aelm.202400146
View details for Web of Science ID 001265392700001
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Future Design Direction for SRAM Data Array: Hierarchical Subarray With Active Interconnect
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
2024
View details for DOI 10.1109/TCSI.2024.3410518
View details for Web of Science ID 001252498300001
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EMBER: Efficient Multiple-Bits-Per-Cell Embedded RRAM Macro for High-Density Digital Storage
IEEE JOURNAL OF SOLID-STATE CIRCUITS
2024
View details for DOI 10.1109/JSSC.2024.3387566
View details for Web of Science ID 001205858500001
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Faulty Function Extraction for Defective Circuits
IEEE. 2024
View details for DOI 10.1109/ETS61313.2024.10567760
View details for Web of Science ID 001260970400042
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Efficient Ultra-Dense 3D IC Power Delivery and Cooling Using 3D Thermal Scaffolding
ASSOC COMPUTING MACHINERY. 2024
View details for DOI 10.1145/3676536.3676760
View details for Web of Science ID 001479882200073
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Cooling future system-on-chips with diamond inter-tiers
CELL REPORTS PHYSICAL SCIENCE
2023; 4 (12)
View details for DOI 10.1016/j.xcrp.2023.101686
View details for Web of Science ID 001144107300001
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Band-to-Band Tunneling Leakage Current Characterization and Projection in Carbon Nanotube Transistors.
ACS nano
2023
Abstract
Carbon nanotube (CNT) transistors demonstrate high mobility but also experience off-state leakage due to the small effective mass and band gap. The lower limit of off-current (IMIN) was measured in electrostatically doped CNT metal-oxide-semiconductor field-effect transistors (MOSFETs) across a range of band gaps (0.37 to 1.19 eV), supply voltages (0.5 to 0.7 V), and extension doping levels (0.2 to 0.8 carriers/nm). A nonequilibrium Green's function (NEGF) model confirms the dependence of IMIN on CNT band gap, supply voltage, and extension doping level. A leakage current design space across CNT band gap, supply voltage, and extension doping is projected based on the validated NEGF model for long-channel CNT MOSFETs to identify the appropriate device design choices. The optimal extension doping and CNT band gap design choice for a target off-current density are identified by including on-current projection in the leakage current design space. An extension doping level >0.5 carrier/nm is required for optimized on-current.
View details for DOI 10.1021/acsnano.3c04346
View details for PubMedID 37910857
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Micro/Nano Circuits and Systems Design and Design Automation: Challenges and Opportunities
PROCEEDINGS OF THE IEEE
2023; 111 (6): 561-574
View details for DOI 10.1109/JPROC.2023.3276941
View details for Web of Science ID 001012667300001
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An Exhaustive Approach to Detecting Transient Execution Side Channels in RTL Designs of Processors
IEEE TRANSACTIONS ON COMPUTERS
2023; 72 (1): 222-235
View details for DOI 10.1109/TC.2022.3152666
View details for Web of Science ID 000899952600018
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Thermal Scaffolding for Ultra-Dense 3D Integrated Circuits
IEEE. 2023
View details for DOI 10.1109/DAC56929.2023.10247815
View details for Web of Science ID 001073487300131
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EMBER: A 100 MHz, 0.86 mm<SUP>2</SUP>, Multiple-Bits-per-Cell RRAM Macro in 40 nm CMOS with Compact Peripherals and 1.0 pJ/bit Read Circuitry
IEEE. 2023: 469-472
View details for DOI 10.1109/ESSCIRC59616.2023.10268807
View details for Web of Science ID 001088613100118
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G-QED: Generalized QED Pre-silicon Verification beyond Non-Interfering Hardware Accelerators
IEEE. 2023
View details for DOI 10.1109/DAC56929.2023.10247903
View details for Web of Science ID 001073487300211
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Efficient Modeling and Calibration of Multi-Electrode Stimuli for Epiretinal Implants
IEEE. 2023
View details for DOI 10.1109/NER52421.2023.10123907
View details for Web of Science ID 001009053700189
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Partitioned Temporal Dithering for Efficient Epiretinal Electrical Stimulation
IEEE. 2023
View details for DOI 10.1109/NER52421.2023.10123787
View details for Web of Science ID 001009053700072
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Testbench on a Chip: A Yield Test Vehicle for Resistive Memory Devices
IEEE. 2023: 576-582
View details for DOI 10.1109/ISQED57927.2023.10129298
View details for Web of Science ID 001013619400081
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Ultra-Dense 3D Physical Design Unlocks New Architectural Design Points with Large Benefits
IEEE. 2023
View details for Web of Science ID 001027444200118
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Three-Dimensional Stacked Neural Network Accelerator Architectures for AR/VR Applications
IEEE MICRO
2022; 42 (6): 116-124
View details for DOI 10.1109/MM.2022.3202254
View details for Web of Science ID 000878171600027
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Extended Scale Length Theory for Low-Dimensional Field-Effect Transistors
IEEE TRANSACTIONS ON ELECTRON DEVICES
2022
View details for DOI 10.1109/TED.2022.3190464
View details for Web of Science ID 000829075200001
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CHIMERA: A 0.92-TOPS, 2.2-TOPS/W Edge AI Accelerator With 2-MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference
IEEE JOURNAL OF SOLID-STATE CIRCUITS
2022
View details for DOI 10.1109/JSSC.2022.3140753
View details for Web of Science ID 000750226200001
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PEPR: Pseudo-Exhaustive Physically-Aware Region Testing
IEEE COMPUTER SOC. 2022: 314-323
View details for DOI 10.1109/ITC50671.2022.00083
View details for Web of Science ID 000918580100035
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RADAR: A Fast and Energy-Efficient Programming Technique for Multiple Bits-Per-Cell RRAM Arrays
IEEE TRANSACTIONS ON ELECTRON DEVICES
2021; 68 (9): 4397-4403
View details for DOI 10.1109/TED.2021.3097975
View details for Web of Science ID 000686761500038
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Split-Chip Design to Prevent IP Reverse Engineering
IEEE DESIGN & TEST
2021; 38 (4): 109-118
View details for DOI 10.1109/MDAT.2020.3033255
View details for Web of Science ID 000678331400021
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Illusion of large on-chip memory by networked computing chips for neural network inference
NATURE ELECTRONICS
2021
View details for DOI 10.1038/s41928-020-00515-3
View details for Web of Science ID 000607033100001
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Automatic Identification of Axon Bundle Activation for Epiretinal Prosthesis
IEEE TRANSACTIONS ON NEURAL SYSTEMS AND REHABILITATION ENGINEERING
2021; 29: 2496-2502
Abstract
Retinal prostheses must be able to activate cells in a selective way in order to restore high-fidelity vision. However, inadvertent activation of far-away retinal ganglion cells (RGCs) through electrical stimulation of axon bundles can produce irregular and poorly controlled percepts, limiting artificial vision. In this work, we aim to provide an algorithmic solution to the problem of detecting axon bundle activation with a bi-directional epiretinal prostheses.The algorithm utilizes electrical recordings to determine the stimulation current amplitudes above which axon bundle activation occurs. Bundle activation is defined as the axonal stimulation of RGCs with unknown soma and receptive field locations, typically beyond the electrode array. The method exploits spatiotemporal characteristics of electrically-evoked spikes to overcome the challenge of detecting small axonal spikes.The algorithm was validated using large-scale, single-electrode and short pulse, ex vivo stimulation and recording experiments in macaque retina, by comparing algorithmically and manually identified bundle activation thresholds. For 88% of the electrodes analyzed, the threshold identified by the algorithm was within ±10% of the manually identified threshold, with a correlation coefficient of 0.95.This works presents a simple, accurate and efficient algorithm to detect axon bundle activation in epiretinal prostheses.The algorithm could be used in a closed-loop manner by a future epiretinal prosthesis to reduce poorly controlled visual percepts associated with bundle activation. Activation of distant cells via axonal stimulation will likely occur in other types of retinal implants and cortical implants, and the method may therefore be broadly applicable.
View details for DOI 10.1109/TNSRE.2021.3128486
View details for Web of Science ID 000730473200002
View details for PubMedID 34784278
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Spatially Patterned Bi-electrode Epiretinal Stimulation for Axon Avoidance at Cellular Resolution.
Journal of neural engineering
2021
Abstract
Epiretinal prostheses are designed to restore vision to people blinded by photoreceptor degenerative diseases by stimulating surviving retinal ganglion cells (RGCs), which carry visual signals to the brain. However, inadvertent stimulation of RGCs at their axons can result in non-focal visual percepts, limiting the quality of artificial vision. Theoretical work has suggested that axon activation can be avoided with current stimulation designed to minimize the second spatial derivative of the induced extracellular voltage along the axon. However, this approach has not been verified experimentally at the resolution of single cells.In this work, a custom multi-electrode array (512 electrodes, 10 μm diameter, 60 μm pitch) was used to stimulate and record RGCs in macaque retina ex vivo at single-cell, single-spike resolution. RGC activation thresholds resulting from bi-electrode stimulation, which consisted of bipolar currents simultaneously delivered through two electrodes straddling an axon, were compared to activation thresholds from traditional single-electrode stimulation.On average, across three retinal preparations, the bi-electrode stimulation strategy reduced somatic activation thresholds (~21%) while increasing axonal activation thresholds (~14%), thus favoring selective somatic activation. Furthermore, individual examples revealed rescued selective activation of somas that was not possible with any individual electrode.This work suggests that a bi-electrode epiretinal stimulation strategy can reduce inadvertent axonal activation at cellular resolution, for high-fidelity artificial vision.
View details for DOI 10.1088/1741-2552/ac3450
View details for PubMedID 34710857
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A Density Metric for Semiconductor Technology
PROCEEDINGS OF THE IEEE
2020; 108 (4): 478–82
View details for DOI 10.1109/JPROC.2020.2981715
View details for Web of Science ID 000528671200001
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Gap-free Processor Verification by S(2)QED and Property Generation
IEEE. 2020: 526–31
View details for Web of Science ID 000610549200096
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DECOY: DEflection-Driven HLS-Based Computation Partitioning for Obfuscating Intellectual PropertY
IEEE. 2020
View details for Web of Science ID 000628528400031
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A Formal Approach for Detecting Vulnerabilities to Transient Execution Attacks in Out-of-Order Processors
IEEE. 2020
View details for Web of Science ID 000628528400080
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A-QED Verification of Hardware Accelerators
IEEE. 2020
View details for Web of Science ID 000628528400220
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Hybrid Quick Error Detection: Validation and Debug of SoCs Through High-Level Synthesis
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
2019; 38 (7): 1345–58
View details for DOI 10.1109/TCAD.2018.2837103
View details for Web of Science ID 000472568000013
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Resistive RAM Endurance: Array-Level Characterization and Correction Techniques Targeting Deep Learning Applications
IEEE TRANSACTIONS ON ELECTRON DEVICES
2019; 66 (3): 1281–88
View details for DOI 10.1109/TED.2019.2894387
View details for Web of Science ID 000460970400022
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Low-Temperature Side Contact to Carbon Nanotube Transistors: Resistance Distributions Down to 10 nm Contact Length
NANO LETTERS
2019; 19 (2): 1083–89
Abstract
Carbon nanotube field-effect transistors (CNFETs) promise to improve the energy efficiency, speed, and transistor density of very large scale integration circuits owing to the intrinsic thin channel body and excellent charge transport properties of carbon nanotubes. Low-temperature fabrication (e.g., <400 °C) is a key enabler for the monolithic three-dimensional (3D) integration of CNFET digital logic into a device technology platform that overcomes memory bandwidth bottlenecks for data-abundant applications such as big-data analytics and machine learning. However, high contact resistance for short CNFET contacts has been a major roadblock to establishing CNFETs as a viable technology because the contact resistance, in series with the channel resistance, reduces the on-state current of CNFETs. Additionally, the variation in contact resistance remains unstudied for short contacts and will further degrade the energy efficiency and speed of CNFET circuits. In this work, we investigate by experiments the contact resistance and statistical variation of room-temperature fabricated CNFET contacts down to 10 nm contact lengths. These CNFET contacts are ∼15 nm shorter than the state-of-the-art Si CMOS "7 nm node" contact length, allowing for multiple generations of future scaling of the transistor-contacted gate pitch. For the 10 nm contacts, we report contact resistance values down to 6.5 kΩ per source/drain contact for a single carbon nanotube (CNT) with a median contact resistance of 18.2 kΩ. The 10 nm contacts reduce the CNFET current by as little as 13% at VDS = 0.7 V compared with the best reported 200 nm contacts to date, corroborated by results in this work. Our analysis of RC from 232 single-CNT CNFETs between the long-contact (e.g., 200 nm) and short-contact (e.g., 10 nm) regimes quantifies the resistance variation and projects the impact on CNFET current variability versus the number of CNT in the transistor. The resistance distribution reveals contact-length-dependent RC variations become significant below 20 nm contact length. However, a larger source of CNFET resistance variation is apparent at all contact lengths used in this work. To further investigate the origins of this contact-length-independent resistance variation, we analyze the variation of RC in arrays of identical CNFETs along a single CNT of constant diameter and observe the random occurrence of high RC, even on correlated CNFETs.
View details for DOI 10.1021/acs.nanolett.8b04370
View details for Web of Science ID 000459222300060
View details for PubMedID 30677297
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Optimization of Electrical Stimulation for a High-Fidelity Artificial Retina
IEEE. 2019: 714–18
View details for Web of Science ID 000469933200174
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Unlocking the Power of Formal Hardware Verification with CoSA and Symbolic QED
IEEE. 2019
View details for Web of Science ID 000524676400055
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Cross-Layer Resilience: Challenges, Insights, and the Road Ahead
ASSOC COMPUTING MACHINERY. 2019
View details for DOI 10.1145/3316781.3323474
View details for Web of Science ID 000482058200198
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A Data-Compressive Wired-OR Readout for Massively Parallel Neural Recording
IEEE. 2019
View details for Web of Science ID 000483076401065
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Resistive RAM With Multiple Bits Per Cell: Array-Level Demonstration of 3 Bits Per Cell
IEEE TRANSACTIONS ON ELECTRON DEVICES
2019; 66 (1): 641–46
View details for DOI 10.1109/TED.2018.2879788
View details for Web of Science ID 000454333500085
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A 43pJ/Cycle Non-Volatile Microcontroller with 4.7 mu s Shutdown/Wake-up Integrating 2.3-bit/Cell Resistive RAM and Resilience Techniques
IEEE. 2019: 226-+
View details for Web of Science ID 000463153600071
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The N3XT Approach to Energy-Efficient Abundant-Data Computing
PROCEEDINGS OF THE IEEE
2019; 107 (1): 19–48
View details for DOI 10.1109/JPROC.2018.2882603
View details for Web of Science ID 000454770800004
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Processor Hardware Security Vulnerabilities and their Detection by Unique Program Execution Checking
IEEE. 2019: 994–99
View details for Web of Science ID 000470666100185
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Symbolic QED Pre-silicon Verification for Automotive Microcontroller Cores: Industrial Case Study
IEEE. 2019: 1000–1005
View details for Web of Science ID 000470666100186
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Review of Methodologies for Pre- and Post-Silicon Analog Verification in Mixed-Signal SOCs
IEEE. 2019: 1006–9
View details for Web of Science ID 000470666100187
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Understanding Energy Efficiency Benefits of Carbon Nanotube Field-Effect Transistors for Digital VLSI
IEEE TRANSACTIONS ON NANOTECHNOLOGY
2018; 17 (6): 1259–69
View details for DOI 10.1109/TNANO.2018.2871841
View details for Web of Science ID 000449979300026
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Hyperdimensional Computing Exploiting Carbon Nanotube FETs, Resistive RAM, and Their Monolithic 3D Integration
IEEE JOURNAL OF SOLID-STATE CIRCUITS
2018; 53 (11): 3183–96
View details for DOI 10.1109/JSSC.2018.2870560
View details for Web of Science ID 000449108400016
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ETISS-ML: A Multi-Level Instruction Set Simulator with RTL-level Fault Injection Support for the Evaluation of Cross-Layer Resiliency Techniques
IEEE. 2018: 609–12
View details for Web of Science ID 000435148800112
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Exploratory logic synthesis for multiple independent gate FETs
FUNCTIONALITY-ENHANCED DEVICES: AN ALTERNATIVE TO MOORE'S LAW
2018; 39: 255–72
View details for Web of Science ID 000479027300011
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TRIG: Hardware Accelerator for Inference-Based Applications and Experimental Demonstration Using Carbon Nanotube FETs
IEEE. 2018
View details for DOI 10.1145/3195970.3196132
View details for Web of Science ID 000446034500096
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Future Interconnect Materials and System Integration Strategies for Data-Intensive Applications
IEEE. 2018
View details for Web of Science ID 000469095300021
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Brain-Inspired Computing Exploiting Carbon Nanotube FETs and Resistive RAM: Hyperdimensional Computing Case Study
IEEE. 2018: 492-+
View details for Web of Science ID 000459205600205
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Coming Up N3XT, After 2D Scaling of Si CMOS
IEEE. 2018
View details for Web of Science ID 000451218703201
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Brain-Inspired Computing Exploiting Carbon Nanotube FETs and Resistive RAM: Hyperdimensional Computing Case Study
IEEE. 2018
View details for Web of Science ID 000432256300204
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Symbolic Quick Error Detection Using Symbolic Initial State for Pre-Silicon Verification
IEEE. 2018: 55–60
View details for Web of Science ID 000435148800010
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Resistive RAM-Centric Computing: Design and Modeling Methodology
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
2017; 64 (9): 2263–73
View details for DOI 10.1109/TCSI.2017.2709812
View details for Web of Science ID 000409058000005
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System-Level Effects of Soft Errors in Uncore Components
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
2017; 36 (9): 1497-1510
View details for DOI 10.1109/TCAD.2017.2651824
View details for Web of Science ID 000408149500007
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Three-dimensional integration of nanotechnologies for computing and data storage on a single chip
NATURE
2017; 547 (7661): 74-+
Abstract
The computing demands of future data-intensive applications will greatly exceed the capabilities of current electronics, and are unlikely to be met by isolated improvements in transistors, data storage technologies or integrated circuit architectures alone. Instead, transformative nanosystems, which use new nanotechnologies to simultaneously realize improved devices and new integrated circuit architectures, are required. Here we present a prototype of such a transformative nanosystem. It consists of more than one million resistive random-access memory cells and more than two million carbon-nanotube field-effect transistors-promising new nanotechnologies for use in energy-efficient digital logic circuits and for dense data storage-fabricated on vertically stacked layers in a single chip. Unlike conventional integrated circuit architectures, the layered fabrication realizes a three-dimensional integrated circuit architecture with fine-grained and dense vertical connectivity between layers of computing, data storage, and input and output (in this instance, sensing). As a result, our nanosystem can capture massive amounts of data every second, store it directly on-chip, perform in situ processing of the captured data, and produce 'highly processed' information. As a working prototype, our nanosystem senses and classifies ambient gases. Furthermore, because the layers are fabricated on top of silicon logic circuitry, our nanosystem is compatible with existing infrastructure for silicon-based technologies. Such complex nano-electronic systems will be essential for future high-performance and highly energy-efficient electronic systems.
View details for PubMedID 28682331
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Activation of ganglion cells and axon bundles using epiretinal electrical stimulation.
Journal of neurophysiology
2017: jn 00750 2016-?
Abstract
Epiretinal prostheses for treating blindness activate axon bundles, causing large, arc-shaped visual percepts that limit the quality of artificial vision. Improving the function of epiretinal prostheses therefore requires understanding and avoiding axon bundle activation. This paper introduces a method to detect axon bundle activation based on its electrical signature, and uses the method to test whether epiretinal stimulation can directly elicit spikes in individual retinal ganglion cells without activating nearby axon bundles. Combined electrical stimulation and recording from isolated primate retina were performed using a custom multi-electrode system (512 electrodes, 10 μm diameter, 60 μm pitch). Axon bundle signals were identified by their bi-directional propagation, speed, and increasing amplitude as a function of stimulation current. The threshold for bundle activation varied across electrodes and retinas, and was in the same range as the threshold for activating retinal ganglion cells near their somas. In the peripheral retina, 45% of electrodes that activated individual ganglion cells (17% of all electrodes) did so without activating bundles. This permitted selective activation of 21% of recorded ganglion cells (7% of all ganglion cells) over the array. In the central retina, 75% of electrodes that activated individual ganglion cells (16% of all electrodes) did so without activating bundles. The ability to selectively activate a subset of retinal ganglion cells without axon bundles suggests a possible novel architecture for future epiretinal prostheses.
View details for DOI 10.1152/jn.00750.2016
View details for PubMedID 28566464
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Hysteresis-Free Carbon Nanotube Field-Effect Transistors.
ACS nano
2017; 11 (5): 4785-4791
Abstract
While carbon nanotube (CNT) field-effect transistors (CNFETs) promise high-performance and energy-efficient digital systems, large hysteresis degrades these potential CNFET benefits. As hysteresis is caused by traps surrounding the CNTs, previous works have shown that clean interfaces that are free of traps are important to minimize hysteresis. Our previous findings on the sources and physics of hysteresis in CNFETs enabled us to understand the influence of gate dielectric scaling on hysteresis. To begin with, we validate through simulations how scaling the gate dielectric thickness results in greater-than-expected benefits in reducing hysteresis. Leveraging this insight, we experimentally demonstrate reducing hysteresis to <0.5% of the gate-source voltage sweep range using a very large-scale integration compatible and solid-state technology, simply by fabricating CNFETs with a thin effective oxide thickness of 1.6 nm. However, even with negligible hysteresis, large subthreshold swing is still observed in the CNFETs with multiple CNTs per transistor. We show that the cause of large subthreshold swing is due to threshold voltage variation between individual CNTs. We also show that the source of this threshold voltage variation is not explained solely by variations in CNT diameters (as is often ascribed). Rather, other factors unrelated to the CNTs themselves (i.e., process variations, random fixed charges at interfaces) are a significant factor in CNT threshold voltage variations and thus need to be further improved.
View details for DOI 10.1021/acsnano.7b01164
View details for PubMedID 28463503
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Invited: A Systems Approach to Computing in Beyond CMOS Fabrics
IEEE. 2017
View details for DOI 10.1145/3061639.3072943
View details for Web of Science ID 000424895400018
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Device-Architecture Co-Design for Hyperdimensional Computing with 3D Vertical Resistive Switching Random Access Memory (3D VRRAM)
IEEE. 2017
View details for Web of Science ID 000408991800057
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Introduction to the January Special Issue on the 2016 IEEE International Solid-State Circuits Conference
IEEE JOURNAL OF SOLID-STATE CIRCUITS
2017; 52 (1): 3-7
View details for DOI 10.1109/JSSC.2016.2635358
View details for Web of Science ID 000395641800001
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Cross-Layer Resilience in Low-Voltage Digital Systems: Key Insights
IEEE. 2017: 593–96
View details for DOI 10.1109/ICCD.2017.103
View details for Web of Science ID 000424789300093
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E-QED: Electrical Bug Localization During Post-silicon Validation Enabled by Quick Error Detection and Formal Methods
SPRINGER INTERNATIONAL PUBLISHING AG. 2017: 104–25
View details for DOI 10.1007/978-3-319-63390-9_6
View details for Web of Science ID 000431900900006
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Very Low Voltage (VLV) Design
IEEE. 2017: 601–4
View details for DOI 10.1109/ICCD.2017.105
View details for Web of Science ID 000424789300095
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Special Session Paper 3D Nanosystems Enable Embedded Abundant-Data Computing
IEEE. 2017
View details for DOI 10.1145/3125502.3125531
View details for Web of Science ID 000425920100014
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Symbolic Quick Error Detection for Pre-Silicon and Post-Silicon Validation: Frequently Asked Questions
IEEE DESIGN & TEST
2016; 33 (6): 55-62
View details for DOI 10.1109/MDAT.2016.2590987
View details for Web of Science ID 000393047000009
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Time-Based Sensor Interface Circuits in CMOS and Carbon Nanotube Technologies
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
2016; 63 (5): 577-586
View details for DOI 10.1109/TCSI.2016.2525098
View details for Web of Science ID 000379915500003
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TPAD: Hardware Trojan Prevention and Detection for Trusted Integrated Circuits
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
2016; 35 (4): 521-534
View details for DOI 10.1109/TCAD.2015.2474373
View details for Web of Science ID 000372995000001
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Hysteresis in Carbon Nanotube Transistors: Measurement and Analysis of Trap Density, Energy Level, and Spatial Distribution
ACS NANO
2016; 10 (4): 4599-4608
Abstract
We present a measurement technique, which we call the Pulsed Time-Domain Measurement, for characterizing hysteresis in carbon nanotube field-effect transistors, and demonstrate its applicability for a broad range of 1D and 2D nanomaterials beyond carbon nanotubes. The Pulsed Time-Domain Measurement enables the quantification (density, energy level, and spatial distribution) of charged traps responsible for hysteresis. A physics-based model of the charge trapping process for a carbon nanotube field-effect transistor is presented and experimentally validated using the Pulsed Time-Domain Measurement. Leveraging this model, we discover a source of traps (surface traps) unique to devices with low-dimensional channels such as carbon nanotubes and nanowires (beyond interface traps which exist in today's silicon field-effect transistors). The different charge trapping mechanisms for interface traps and surface traps are studied based on their temperature dependencies. Through these advances, we are able to quantify the interface trap density for carbon nanotube field-effect transistors (∼3 × 10(13) cm(-2) eV(-1) near midgap), and compare this against a range of previously studied dielectric/semiconductor interfaces.
View details for DOI 10.1021/acsnano.6b00792
View details for PubMedID 27002483
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Nano-Engineered Architectures for Ultra-Low Power Wireless Body Sensor Nodes
ASSOC COMPUTING MACHINERY. 2016
View details for DOI 10.1145/2968456.2968464
View details for Web of Science ID 000390612700023
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Transforming Nanodevices into Nanosystems: The N3XT 1,000X
IEEE. 2016: 6
View details for Web of Science ID 000386790400003
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Transforming Nanodevices to Next Generation Nanosystems
IEEE. 2016: 288–92
View details for Web of Science ID 000399143000038
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Cross-Layer Resilience
IEEE. 2016
View details for Web of Science ID 000387103500039
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CLEAR: Cross-Layer Exploration for Architecting Resilience Combining Hardware and Software Techniques to Tolerate Soft Errors in Processor Cores
ASSOC COMPUTING MACHINERY. 2016
View details for DOI 10.1145/2897937.2897996
View details for Web of Science ID 000390302500068
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Energy-Efficient Abundant-Data Computing: The N3XT 1,000x
COMPUTER
2015; 48 (12): 24-33
View details for Web of Science ID 000367689400005
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New Logic Synthesis as Nanotechnology Enabler
PROCEEDINGS OF THE IEEE
2015; 103 (11): 2168-2195
View details for DOI 10.1109/JPROC.2015.2460377
View details for Web of Science ID 000364032300017
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Rapid Co-Optimization of Processing and Circuit Design to Overcome Carbon Nanotube Variations
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
2015; 34 (7): 1082-1095
View details for DOI 10.1109/TCAD.2015.2415492
View details for Web of Science ID 000356496100004
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NSF expedition on variability-aware software: Recent results and contributions
IT-INFORMATION TECHNOLOGY
2015; 57 (3): 181–98
View details for DOI 10.1515/itit-2014-1085
View details for Web of Science ID 000219329700005
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<i>IEEE D</i>&<i>T</i> Roundtable to Cover ITC 2014 Panel on "Open Problems in Design, Verification, and Test: Why Is It (Not) Business as Usual?"
IEEE DESIGN & TEST
2015; 32 (3): 41-47
View details for DOI 10.1109/MDAT.2015.2417800
View details for Web of Science ID 000356168900005
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Monolithic 3D Integration: A Path From Concept To Reality
IEEE. 2015: 1197–1202
View details for Web of Science ID 000380393200221
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From Nanodevices to Nanosystems: The N3XT Information Technology
IEEE. 2015
View details for Web of Science ID 000370657300030
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Quick Error Detection Tests with Fast Runtimes for Effective Post-Silicon Validation and Debug
IEEE. 2015: 1168–73
View details for Web of Science ID 000380393200216
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Time-Based Sensor Interface Circuits in Carbon Nanotube Technology
IEEE. 2015: 2924–27
View details for Web of Science ID 000371471003052
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Efficient Soft Error Vulnerability Estimation of Complex Designs
IEEE. 2015: 103-108
View details for Web of Science ID 000380393200018
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Multiple Independent Gate FETs: How Many Gates Do We Need?
IEEE. 2015: 243-248
View details for Web of Science ID 000380442800055
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Efficient Metallic Carbon Nanotube Removal for Highly-Scaled Technologies
IEEE. 2015
View details for Web of Science ID 000380472500209
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Effective Post-Silicon Validation of System-on-Chips Using Quick Error Detection
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
2014; 33 (10): 1573-1590
View details for DOI 10.1109/TCAD.2014.2334301
View details for Web of Science ID 000344529700011
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Carbon nanotubes for high-performance logic
MRS BULLETIN
2014; 39 (8): 719-726
View details for DOI 10.1557/mrs.2014.164
View details for Web of Science ID 000341107900014
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Robust and Energy-Secure Systems
IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS
2014; 4 (2): 165-168
View details for DOI 10.1109/JETCAS.2014.2315885
View details for Web of Science ID 000337906000001
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Addressing failures in exascale computing
INTERNATIONAL JOURNAL OF HIGH PERFORMANCE COMPUTING APPLICATIONS
2014; 28 (2): 129-173
View details for DOI 10.1177/1094342014522573
View details for Web of Science ID 000336222700001
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System Level Benchmarking with Yield-Enhanced Standard Cell Library for Carbon Nanotube VLSI Circuits
ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS
2014; 10 (4)
View details for DOI 10.1145/2600073
View details for Web of Science ID 000336444700007
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Carbon Nanotube Circuit Integration up to Sub-20 nm Channel Lengths
ACS NANO
2014; 8 (4): 3434-3443
Abstract
Carbon nanotube (CNT) field-effect transistors (CNFETs) are a promising emerging technology projected to achieve over an order of magnitude improvement in energy-delay product, a metric of performance and energy efficiency, compared to silicon-based circuits. However, due to substantial imperfections inherent with CNTs, the promise of CNFETs has yet to be fully realized. Techniques to overcome these imperfections have yielded promising results, but thus far only at large technology nodes (1 μm device size). Here we demonstrate the first very large scale integration (VLSI)-compatible approach to realizing CNFET digital circuits at highly scaled technology nodes, with devices ranging from 90 nm to sub-20 nm channel lengths. We demonstrate inverters functioning at 1 MHz and a fully integrated CNFET infrared light sensor and interface circuit at 32 nm channel length. This demonstrates the feasibility of realizing more complex CNFET circuits at highly scaled technology nodes.
View details for DOI 10.1021/nn406301r
View details for Web of Science ID 000334990600034
View details for PubMedID 24654597
- Rethinking Error Injection for Effective Resilience 2014
- Sensor-to-Digital Interface Built Entirely with Carbon Nanotube FETs IEEE Journal on Solid-State Circuits, Special Issue on IEEE Intl. Solid-State Circuits Conf. 2014
- QED Post-Silicon Validation and Debug: Frequently Asked Questions 2014
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Advancements With Carbon Nanotube Digital Systems
IEEE. 2014: 319-321
View details for Web of Science ID 000356605200056
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The Resilience Wall: Cross-Layer Solution Strategies
IEEE. 2014
View details for Web of Science ID 000356616400075
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Monolithic 3D Integration of Logic and Memory: Carbon Nanotube FETs, Resistive RAM, and Silicon FETs
IEEE. 2014
View details for Web of Science ID 000370384800158
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QED Post-Silicon Validation and Debug Invited Abstract
IEEE. 2014: 62
View details for Web of Science ID 000380456800143
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Rethinking Error Injection for Effective Resilience
IEEE. 2014: 390-393
View details for Web of Science ID 000350791700073
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High-Performance Carbon Nanotube Field-Effect Transistors
IEEE. 2014
View details for Web of Science ID 000370384800202
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The Resilience Wall: Cross-Layer Solution Strategies
IEEE. 2014
View details for Web of Science ID 000358865800003
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Monolithic Three-Dimensional Integration of Carbon Nanotube FETs with Silicon CMOS
IEEE. 2014
View details for Web of Science ID 000380558800084
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Robust Design and Experimental Demonstrations of Carbon Nanotube Digital Circuits
36th Annual IEEE Custom Integrated Circuits Conference (CICC) - The Showcase for Integrated Circuit Design in the Heart of Silicon Valley
IEEE. 2014
View details for Web of Science ID 000349122300058
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QED Post-Silicon Validation and Debug: Frequently Asked Questions
19th Asia and South Pacific Design Automation Conference (ASP-DAC)
IEEE. 2014: 478–482
View details for Web of Science ID 000350791700088
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Sensor-to-Digital Interface Built Entirely With Carbon Nanotube FETs
IEEE JOURNAL OF SOLID-STATE CIRCUITS
2014; 49 (1): 190-201
View details for DOI 10.1109/JSSC.2013.2282092
View details for Web of Science ID 000329052700018
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Rethinking Error Injection for Effective Resilience
19th Asia and South Pacific Design Automation Conference (ASP-DAC)
IEEE. 2014: 390–393
View details for Web of Science ID 000350791700073
- System-Level Benchmarking with Yield-Enhanced Standard Cell Library for Carbon Nanotube VLSI Circuits ACM Journal on Emerging Technologies in Computing Systems 2014
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Carbon nanotube computer.
Nature
2013; 501 (7468): 526-530
Abstract
The miniaturization of electronic devices has been the principal driving force behind the semiconductor industry, and has brought about major improvements in computational power and energy efficiency. Although advances with silicon-based electronics continue to be made, alternative technologies are being explored. Digital circuits based on transistors fabricated from carbon nanotubes (CNTs) have the potential to outperform silicon by improving the energy-delay product, a metric of energy efficiency, by more than an order of magnitude. Hence, CNTs are an exciting complement to existing semiconductor technologies. Owing to substantial fundamental imperfections inherent in CNTs, however, only very basic circuit blocks have been demonstrated. Here we show how these imperfections can be overcome, and demonstrate the first computer built entirely using CNT-based transistors. The CNT computer runs an operating system that is capable of multitasking: as a demonstration, we perform counting and integer-sorting simultaneously. In addition, we implement 20 different instructions from the commercial MIPS instruction set to demonstrate the generality of our CNT computer. This experimental demonstration is the most complex carbon-based electronic system yet realized. It is a considerable advance because CNTs are prominent among a variety of emerging technologies that are being considered for the next generation of highly energy-efficient electronic systems.
View details for DOI 10.1038/nature12502
View details for PubMedID 24067711
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Carbon nanotube computer.
Nature
2013; 501 (7468): 526-530
Abstract
The miniaturization of electronic devices has been the principal driving force behind the semiconductor industry, and has brought about major improvements in computational power and energy efficiency. Although advances with silicon-based electronics continue to be made, alternative technologies are being explored. Digital circuits based on transistors fabricated from carbon nanotubes (CNTs) have the potential to outperform silicon by improving the energy-delay product, a metric of energy efficiency, by more than an order of magnitude. Hence, CNTs are an exciting complement to existing semiconductor technologies. Owing to substantial fundamental imperfections inherent in CNTs, however, only very basic circuit blocks have been demonstrated. Here we show how these imperfections can be overcome, and demonstrate the first computer built entirely using CNT-based transistors. The CNT computer runs an operating system that is capable of multitasking: as a demonstration, we perform counting and integer-sorting simultaneously. In addition, we implement 20 different instructions from the commercial MIPS instruction set to demonstrate the generality of our CNT computer. This experimental demonstration is the most complex carbon-based electronic system yet realized. It is a considerable advance because CNTs are prominent among a variety of emerging technologies that are being considered for the next generation of highly energy-efficient electronic systems.
View details for DOI 10.1038/nature12502
View details for PubMedID 24067711
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Laterally Actuated Platinum-Coated Polysilicon NEM Relays
JOURNAL OF MICROELECTROMECHANICAL SYSTEMS
2013; 22 (3): 768-778
View details for DOI 10.1109/JMEMS.2013.2244779
View details for Web of Science ID 000319827700029
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Combinational Logic Design Using Six-Terminal NEM Relays
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
2013; 32 (5): 653-666
View details for DOI 10.1109/TCAD.2012.2232707
View details for Web of Science ID 000318163800001
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Underdesigned and Opportunistic Computing in Presence of Hardware Variability
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
2013; 32 (1): 8-23
View details for DOI 10.1109/TCAD.2012.2223467
View details for Web of Science ID 000314676500002
- Carbon Nanotube Computer Nature (Cover Feature) 2013; 501 (7468)
- Rapid Exploration of Processing and Design Guidelines to Overcome Carbon Nanotube Variations 2013
- Self-Repair of Uncore Components in Robust System-on-Chips: An OpenSPARC T2 Case Study 2013
- Detection of Early-Life Failures in High-K Metal-Gate Transistors and Ultra Low-K Inter-Metal Dielectrics 2013
- Sascha: The Stanford Carbon Nanotube Controlled Handshaking Robot 2013
- Early-Life Failure Detection using SAT-Based ATPG 2013
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Self-Repair of Uncore Components in Robust System-on-Chips: An OpenSPARC T2 Case Study
IEEE. 2013
View details for Web of Science ID 000341376000032
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Carbon Nanotube Circuits: Opportunities and Challenges
ASSOC COMPUTING MACHINERY. 2013: 619–24
View details for Web of Science ID 000415129400121
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Quantitative Evaluation of Soft Error Injection Techniques for Robust System Design
IEEE COMPUTER SOC. 2013
View details for Web of Science ID 000325822100100
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Early-Life-Failure Detection using SAT-based ATPG
IEEE. 2013
View details for Web of Science ID 000341376000050
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Experimental Demonstration of a Fully Digital Capacitive Sensor Interface Built Entirely Using Carbon-Nanotube FETs
IEEE. 2013: 112–U897
View details for Web of Science ID 000366612300042
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Self-Repair of Uncore Components in Robust System-on-Chips: An OpenSPARC T2 Case Study
IEEE International Test Conference (ITC)
IEEE. 2013
View details for Web of Science ID 000341376000032
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Rapid Exploration of Processing and Design Guidelines to Overcome Carbon Nanotube Variations
50th ACM/EDAC/IEEE Design Automation Conference (DAC)
IEEE COMPUTER SOC. 2013
View details for Web of Science ID 000325822100104
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Sacha: the Stanford Carbon Nanotube Controlled Handshaking Robot
50th ACM/EDAC/IEEE Design Automation Conference (DAC)
IEEE COMPUTER SOC. 2013
View details for Web of Science ID 000325822100123
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Early-Life-Failure Detection using SAT-based ATPG
IEEE International Test Conference (ITC)
IEEE. 2013
View details for Web of Science ID 000341376000050
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Reliability of Graphene Interconnects and N-type Doping of Carbon Nanotube transistors
IEEE International Reliability Physics Symposium (IRPS)
IEEE. 2013
View details for Web of Science ID 000325097500105
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Quantitative Evaluation of Soft Error Injection Techniques for Robust System Design
50th ACM/EDAC/IEEE Design Automation Conference (DAC)
IEEE COMPUTER SOC. 2013
View details for Web of Science ID 000325822100100
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LATERALLY ACTUATED NANOELECTROMECHANICAL RELAYS WITH COMPLIANT, LOW RESISTANCE CONTACT
26th IEEE International Conference on Micro Electro Mechanical Systems (MEMS)
IEEE. 2013: 520–523
View details for Web of Science ID 000320549200133
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Monolithic Three-Dimensional Integration of Carbon Nanotube FET Complementary Logic Circuits
IEEE International Electron Devices Meeting (IEDM)
IEEE. 2013
View details for Web of Science ID 000346509500126
- Carbon Nanotube Circuits: Opportunities and Challenges 2013
- Reliability of Graphene Interconnects and N-type Doping of Carbon Nanotube Transistors 2013
- Underdesigned and Opportunistic Computing Keynote paper, IEEE Trans. CAD 2013
- Effective Post-Silicon Validation 2013
- Quantitative Evaluation of Soft Error Injection Techniques for Robust System Design 2013
- Experimental Demonstration of a Fully Digital Capacitive Sensor Interface Built Entirely using Carbon Nanotube FETs 2013
- Overcoming Post-Silicon Validation Challenges through Quick Error Detection (QED) 2013
- Monolithic Three-Dimensional Integration of Carbon Nanotube FET Complementary Logic Circuits 2013
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Flexible Control of Block Copolymer Directed Self-Assembly using Small, Topographical Templates: Potential Lithography Solution for Integrated Circuit Contact Hole Patterning
ADVANCED MATERIALS
2012; 24 (23): 3107-3114
View details for DOI 10.1002/adma.201200265
View details for Web of Science ID 000305121100015
View details for PubMedID 22550028
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Single-Tube Characterization Methodology for Experimental and Analytical Evaluation of Carbon Nanotube Synthesis
JAPANESE JOURNAL OF APPLIED PHYSICS
2012; 51 (4)
View details for DOI 10.1143/JJAP.51.04DB02
View details for Web of Science ID 000303928600009
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Robust Digital VLSI using Carbon Nanotubes
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
2012; 31 (4): 453-471
View details for DOI 10.1109/TCAD.2012.2187527
View details for Web of Science ID 000302177200001
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ERSA: Error Resilient System Architecture for Probabilistic Applications
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
2012; 31 (4): 546-558
View details for DOI 10.1109/TCAD.2011.2179038
View details for Web of Science ID 000302177200008
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Probabilistic Analysis of Gallager B Faulty Decoder
IEEE International Conference on Communications (ICC)
IEEE. 2012
View details for Web of Science ID 000312855707057
- Contact-Hole Patterning for Random Logic Circuits using Block Copolymer Directed Self-Assembly 2012
- Cooling Three-Dimesnional Integrated Circuits using Power Delivery Networks 2012
- The Device-to-System Spectrum -- A Tutorial on IC Design with Nanomaterials IEEE/ACM Design Automation and Test in Europe 2012
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Nano-Electro-Mechanical Relays for FPGA Routing: Experimental Demonstration and a Design Technique
IEEE. 2012: 1361–66
View details for Web of Science ID 000415126300278
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Cooling Three-Dimensional Integrated Circuits using Power Delivery Networks
IEEE International Electron Devices Meeting (IEDM)
IEEE. 2012
View details for Web of Science ID 000320615600083
- Nano-Electro-Mechanical Relays for FPGA Routing: Experimental Demonstration and a Design Technique 2012
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Nano-Electro-Mechanical (NEM) Relays and their Application to FPGA Routing
17th Asia and South Pacific Design Automation Conference (ASP-DAC)
IEEE. 2012: 639–639
View details for Web of Science ID 000309240000115
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Integration of Nanoelectromechanical Relays With Silicon nMOS
IEEE TRANSACTIONS ON ELECTRON DEVICES
2012; 59 (1): 255-258
View details for DOI 10.1109/TED.2011.2172946
View details for Web of Science ID 000298756100038
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Quick Detection of Difficult Bugs for Effective Post-Silicon Validation
49th ACM/EDAC/IEEE Design Automation Conference (DAC)
IEEE. 2012: 561–566
View details for Web of Science ID 000309256800081
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Bug Localization Techniques for Effective Post-Silicon Validation
17th Asia and South Pacific Design Automation Conference (ASP-DAC)
IEEE. 2012: 291–291
View details for Web of Science ID 000309240000047
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Wafer-Scale Fabrication and Characterization of Thin-Film Transistors with Polythiophene-Sorted Semiconducting Carbon Nanotube Networks
ACS NANO
2012; 6 (1): 451-458
Abstract
Semiconducting single-walled carbon nanotubes (SWCNTs) have great potential of becoming the channel material for future thin-film transistor technology. However, an effective sorting technique is needed to obtain high-quality semiconducting SWCNTs for optimal device performance. In our previous work, we reported a dispersion technique for semiconducting SWCNTs that relies on regioregular poly(3-dodecylthiophene) (rr-P3DDT) to form hybrid nanostructures. In this study, we demonstrate the scalability of those sorted CNT composite structures to form arrays of TFTs using standard lithographic techniques. The robustness of these CNT nanostructures was tested with Raman spectroscopy and atomic force microscope images. Important trends in device properties were extracted by means of electrical measurements for different CNT concentrations and channel lengths (L(c)). A statistical study provided an average mobility of 1 cm(2)/V·s and I(on)/I(off) as high as 10(6) for short channel lengths (L(c) = 1.5 μm) with 100% yield. This highlights the effectiveness of this sorting technique and its scalability for large-scale, flexible, and transparent display applications.
View details for DOI 10.1021/nn203771u
View details for PubMedID 22148677
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Contact Hole Patterning for Random Logic Circuits using Block Copolymer Directed Self-Assembly
Conference on Alternative Lithographic Technologies IV
SPIE-INT SOC OPTICAL ENGINEERING. 2012
View details for DOI 10.1117/12.912804
View details for Web of Science ID 000304816600019
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Characterization and Design of Logic Circuits in the Presence of Carbon Nanotube Density Variations
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
2011; 30 (8): 1103-1113
View details for DOI 10.1109/TCAD.2011.2121010
View details for Web of Science ID 000293709000002
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The Case for RAMCloud
COMMUNICATIONS OF THE ACM
2011; 54 (7): 121-130
View details for DOI 10.1145/1965724.1965751
View details for Web of Science ID 000293277800033
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Scalable Carbon Nanotube Computational and Storage Circuits Immune to Metallic and Mispositioned Carbon Nanotubes
IEEE TRANSACTIONS ON NANOTECHNOLOGY
2011; 10 (4): 744-750
View details for DOI 10.1109/TNANO.2010.2076323
View details for Web of Science ID 000292966400013
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Self-Tuning for Maximized Lifetime Energy-Efficiency in the Presence of Circuit Aging
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
2011; 30 (5): 760-773
View details for DOI 10.1109/TCAD.2010.2100531
View details for Web of Science ID 000289843900010
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Linear Increases in Carbon Nanotube Density Through Multiple Transfer Technique
NANO LETTERS
2011; 11 (5): 1881-1886
Abstract
We present a technique to increase carbon nanotube (CNT) density beyond the as-grown CNT density. We perform multiple transfers, whereby we transfer CNTs from several growth wafers onto the same target surface, thereby linearly increasing CNT density on the target substrate. This process, called transfer of nanotubes through multiple sacrificial layers, is highly scalable, and we demonstrate linear CNT density scaling up to 5 transfers. We also demonstrate that this linear CNT density increase results in an ideal linear increase in drain-source currents of carbon nanotube field effect transistors (CNFETs). Experimental results demonstrate that CNT density can be improved from 2 to 8 CNTs/μm, accompanied by an increase in drain-source CNFET current from 4.3 to 17.4 μA/μm.
View details for DOI 10.1021/nl200063x
View details for Web of Science ID 000290373000005
View details for PubMedID 21469727
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Hedgehog-responsive candidate cell of origin for diffuse intrinsic pontine glioma
PROCEEDINGS OF THE NATIONAL ACADEMY OF SCIENCES OF THE UNITED STATES OF AMERICA
2011; 108 (11): 4453-4458
Abstract
Diffuse intrinsic pontine gliomas (DIPGs) are highly aggressive tumors of childhood that are almost universally fatal. Our understanding of this devastating cancer is limited by a dearth of available tissue for study and by the lack of a faithful animal model. Intriguingly, DIPGs are restricted to the ventral pons and occur during a narrow window of middle childhood, suggesting dysregulation of a postnatal neurodevelopmental process. Here, we report the identification of a previously undescribed population of immunophenotypic neural precursor cells in the human and murine brainstem whose temporal and spatial distributions correlate closely with the incidence of DIPG and highlight a candidate cell of origin. Using early postmortem DIPG tumor tissue, we have established in vitro and xenograft models and find that the Hedgehog (Hh) signaling pathway implicated in many developmental and oncogenic processes is active in DIPG tumor cells. Modulation of Hh pathway activity has functional consequences for DIPG self-renewal capacity in neurosphere culture. The Hh pathway also appears to be active in normal ventral pontine precursor-like cells of the mouse, and unregulated pathway activity results in hypertrophy of the ventral pons. Together, these findings provide a foundation for understanding the cellular and molecular origins of DIPG, and suggest that the Hh pathway represents a potential therapeutic target in this devastating pediatric tumor.
View details for DOI 10.1073/pnas.1101657108
View details for PubMedID 21368213
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Robust System Design to Overcome CMOS Reliability Challenges
IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS
2011; 1 (1): 30-41
View details for DOI 10.1109/JETCAS.2011.2135630
View details for Web of Science ID 000208972300005
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Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
2011; 30 (1): 124-134
View details for DOI 10.1109/TCAD.2010.2065990
View details for Web of Science ID 000285517100011
- Carbon Nanotube Imperfection-Immune Digital VLSI: Frequently Asked Questions Updated 2011
- Robust System Design IPSJ Trans. System LSI Design Methodology 2011
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Carbon-based Nanomaterial for Nanoelectronics
3rd International Symposium on Graphene, Ge/III-V, Nanowires and Emerging Materials for Post-CMOS Applications / Symposium on Tutorials in Nanotechnology with focus on Dielectrics in Nanosystems
ELECTROCHEMICAL SOC INC. 2011: 259–69
View details for DOI 10.1149/1.3569919
View details for Web of Science ID 000309539300024
- Carbon Electronics – From Material Synthesis to Circuit Demonstration 2011
- Overcoming CMOS Reliability Challenges: From Devices to Circuits and Systems IEEE/ACM Design Automation and Test in Europe 2011
- Robust System Design to Overcome CMOS Reliability Challenges IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Special Issue on the IEEE CAS Forum on Emerging and Selected Topics 2011
- Carbon Nanotube Electronics – Materials, Devices, Circuits, Design, Modeling, and Performance Projection 2011
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Overcoming Carbon Nanotube Variations through Co-optimized Technology and Circuit Design
IEEE International Electron Devices Meeting (IEDM)
IEEE. 2011
View details for Web of Science ID 000300015300022
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Air-Stable Technique for Fabricating n-Type Carbon Nanotube FETs
IEEE International Electron Devices Meeting (IEDM)
IEEE. 2011
View details for Web of Science ID 000300015300127
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Carbon Nanotube Imperfection-Immune Digital VLSI: Frequently Asked Questions Updated Invited Paper
IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
IEEE. 2011: 227–230
View details for Web of Science ID 000299009100034
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Integration of Nanoelectromechanical (NEM) Relays with Silicon CMOS with Functional CMOS-NEM Circuit
IEEE International Electron Devices Meeting (IEDM)
IEEE. 2011
View details for Web of Science ID 000300015300177
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Carbon Nanotube Electronics - Materials, Devices, Circuits, Design, Modeling, and Performance Projection
IEEE International Electron Devices Meeting (IEDM)
IEEE. 2011
View details for Web of Science ID 000300015300126
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ACCNT: A Metallic-CNT-Tolerant Design Methodology for Carbon Nanotube VLSI: Analyses and Design Guidelines
IEEE TRANSACTIONS ON ELECTRON DEVICES
2010; 57 (9): 2284-2295
View details for DOI 10.1109/TED.2010.2053207
View details for Web of Science ID 000283138200031
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Post-Silicon Bug Localization for Processors Using IFRA
COMMUNICATIONS OF THE ACM
2010; 53 (2): 106-113
View details for DOI 10.1145/1646353.1646377
View details for Web of Science ID 000274029100021
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Efficient FPGAs using Nanoelectromechanical Relays
18th ACM International Symposium on Field-Programmable Gate Arrays
ASSOC COMPUTING MACHINERY. 2010: 273–282
View details for Web of Science ID 000285022000035
- Post-Silicon Validation: Opportunities, Challenges and Recent Advances 2010
- Carbon Nanotube Correlation: Promising Opportunity for CNFET Circuit Yield Enhancement 2010
- Carbon Nanotube Circuits: Living with Imperfections and Variations 2010
- Gate-Oxide Early-life Failure Identification using Delay Shifts 2010
- Imperfection-Immune Carbon Nanotube VLSI Circuits Nanoelectronic Circuit Design Springer. 2010: 1
- Characterization and Implementation of Fault-Tolerant Vertical Links for 3D Networks-on-Chip IEEE Trans. CAD 2010
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Carbon Nanotube Circuits: Living with Imperfections and Variations
IEEE. 2010: 1159–64
View details for Web of Science ID 000397468600224
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BLoG: Post-Silicon Bug Localization in Processors using Bug Localization Graphs
IEEE. 2010: 368–73
View details for Web of Science ID 000409973500070
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Carbon Nanotube Correlation: Promising Opportunity for CNFET Circuit Yield Enhancement
IEEE. 2010: 889–92
View details for Web of Science ID 000409973500172
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ERSA: Error Resilient System Architecture for Probabilistic Applications
IEEE. 2010: 1560-1565
View details for Web of Science ID 000397468600300
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Low-Cost Gate-Oxide Early-Life Failure Detection in Robust Systems
IEEE. 2010: 125-126
View details for DOI 10.1109/VLSIC.2010.5560326
View details for Web of Science ID 000287508300048
- Optimized Self-Tuning to Maximize Lifetime Energy-Efficiency in the Presence of Circuit Aging 2010
- BLoG: Post-Silicon Bug Localization in Processors using Bug Localization Graphs 2010
- ERSA: Error-Resilient System Architecture for Probabilistic Applications 2010
- LEAP: Layout Design through Error-Aware Placement for Soft-Error Resilient Sequential Cell Design 2010
- ACCNT - A Metallic-CNT-Tolerant Design Methodology for Carbon Nanotube VLSI: Analyses and Design Guidelines IEEE Trans. Electron Devices 2010
- Concurrent Autonomous Self-Test for Uncore Components in SoCs 2010
- Cross-Layer Resilience Challenges: Metrics and Optimization 2010
- Post-Silicon Bug Localization for Processors Research Highlight, Communications of the ACM 2010
- Scalable Carbon Nanotube Computational and Storage Circuits Immune to Metallic and Mis-positioned Carbon Nanotubes IEEE Trans. Nanotechnology 2010
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Low-Cost Gate-Oxide Early-Life Failure Detection in Robust Systems
Symposium on VLSI Circuits
IEEE. 2010: 125–126
View details for Web of Science ID 000287508300048
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TITANIUM NITRIDE SIDEWALL STRINGER PROCESS FOR LATERAL NANOELECTROMECHANICAL RELAYS
23rd IEEE International Conference on Micro Electro Mechanical Systems (MEMS 2010)
IEEE. 2010: 456–459
View details for Web of Science ID 000278416400112
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Robust System Design
23rd International Conference on VLSI Design/9th International Conference on Embedded Systems
IEEE COMPUTER SOC. 2010: 434–439
View details for Web of Science ID 000283803200074
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LEAP: Layout Design through Error-Aware Transistor Positioning for Soft-Error Resilient Sequential Cell Design
48TH Annual IEEE International Reliability Physics Symposium (IRPS)
IEEE. 2010: 203–212
View details for Web of Science ID 000287515600033
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Efficient Metallic Carbon Nanotube Removal Readily Scalable to Wafer-Level VLSI CNFET Circuits
Symposium on VLSI Technology (VLSIT)
IEEE. 2010: 237–238
View details for Web of Science ID 000287495500091
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QED: Quick Error Detection Tests for Effective Post-Silicon Validation
International Test Conference 2010
IEEE. 2010
View details for Web of Science ID 000287978200017
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Cross-Layer Error Resilience for Robust Systems
IEEE and ACM International Conference on Computer-Aided Design
IEEE. 2010: 177–180
View details for Web of Science ID 000287997600028
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Solution Assembly of Organized Carbon Nanotube Networks for Thin-Film Transistors
ACS NANO
2009; 3 (12): 4089-4097
Abstract
Ultrathin, transparent electronic materials consisting of solution-assembled nanomaterials that are directly integrated as thin-film transistors or conductive sheets may enable many new device structures. Applications ranging from disposable autonomous sensors to flexible, large-area displays and solar cells can dramatically expand the electronics market. With a practical, reliable method for controlling their electronic properties through solution assembly, submonolayer films of aligned single-walled carbon nanotubes (SWNTs) may provide a promising alternative for large-area, flexible electronics. Here, we report SWNT network TFTs (SWNTntTFTs) deposited from solution with controllable topology, on/off ratios averaging greater than 10(5), and an apparent mobility averaging 2 cm(2)/V.s, without any pre- or postprocessing steps. We employ a spin-assembly technique that results in chirality enrichment along with tunable alignment and density of the SWNTs by balancing the hydrodynamic force (spin rate) with the surface interaction force controlled by a chemically functionalized interface. This directed nanoscale assembly results in enriched semiconducting nanotubes yielding excellent TFT characteristics, which is corroborated with mu-Raman spectroscopy. Importantly, insight into the electronic properties of these SWNT networks as a function of topology is obtained.
View details for DOI 10.1021/nn900827v
View details for Web of Science ID 000272846000043
View details for PubMedID 19924882
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ACCNT-A Metallic-CNT-Tolerant Design Methodology for Carbon-Nanotube VLSI: Concepts and Experimental Demonstration
IEEE TRANSACTIONS ON ELECTRON DEVICES
2009; 56 (12): 2969-2978
View details for DOI 10.1109/TED.2009.2033168
View details for Web of Science ID 000271951700012
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Overcoming Early-Life Failure and Aging for Robust Systems
IEEE DESIGN & TEST OF COMPUTERS
2009; 26 (6): 28-39
View details for Web of Science ID 000271976500005
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Overcoming Early-Life Failure and Aging for Robust Systems
IEEE DESIGN & TEST OF COMPUTERS
2009; 26 (6): 28-39
View details for DOI 10.1109/MDT.2009.152
View details for Web of Science ID 000271976500005
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Post-Silicon Bug Localization in Processors Using Instruction Footprint Recording and Analysis (IFRA)
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
2009; 28 (10): 1545-1558
View details for DOI 10.1109/TCAD.2009.2030595
View details for Web of Science ID 000270036600009
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Probabilistic Analysis and Design of Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
2009; 28 (9): 1307-1320
View details for DOI 10.1109/TCAD.2009.2023197
View details for Web of Science ID 000269155200003
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Wafer-Scale Growth and Transfer of Aligned Single-Walled Carbon Nanotubes
IEEE TRANSACTIONS ON NANOTECHNOLOGY
2009; 8 (4): 498-504
View details for DOI 10.1109/TNANO.2009.2016562
View details for Web of Science ID 000268170900013
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Design Methodology and Protection Strategy for ESD-CDM Robust Digital System Design in 90-nm and 130-nm Technologies
IEEE TRANSACTIONS ON ELECTRON DEVICES
2009; 56 (2): 275-283
View details for DOI 10.1109/TED.2008.2010586
View details for Web of Science ID 000262816800017
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Testing for Transistor Aging
27th IEEE VLSI Test Symposium
IEEE COMPUTER SOC. 2009: 215–220
View details for DOI 10.1109/VTS.2009.56
View details for Web of Science ID 000271941000036
- Experimental Study of Gate-Oxide Early Life Failures 2009
- Circuit Aging Prediction for Low-Power Operation 2009
- ACCNT: A Metallic-CNT-Tolerant Design Methodology for Carbon Nanotube VLSI: Concepts and Experimental Demonstration IEEE Trans. Electron Devices 2009
- Overcoming Early-Life Failure and Aging Challenges for Robust System Design IEEE Design and Test of Computers, Special Issue on Design for Reliability and Robustness 2009
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Circuit Aging Prediction for Low-Power Operation
IEEE Custom Integrated Circuits Conference
IEEE. 2009: 427–430
View details for Web of Science ID 000275926300092
- Nanoelectromechanical (NEM) Relay Integrated with CMOS SRAM for Improved Stability and Low Leakage 2009
- Operating System Scheduling for Efficient On-line Self-Test in Robust Systems 2009
- Circuit Reliability: Modeling, Simulation and Resilient Design Solutions 2009
- From Nanodevices to Nanosystems: Promises and Challenges of IC Design with Nanomaterials 2009
- Imperfection-Immune VLSI Logic Circuits using Carbon Nanotube FETs 2009
- IFRA: Instruction Footprint Recording and Analysis for Post-Silicon Bug Localization in Processors IEEE Trans. CAD 2009
- Performance Benchmarking and Scalability of Carbon Nanotube Transistor Circuits IEEE Trans. Nanotechnology 2009
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Threshold Voltage and On-Off Ratio Tuning for Multiple-Tube Carbon Nanotube FETs
IEEE TRANSACTIONS ON NANOTECHNOLOGY
2009; 8 (1): 4-9
View details for DOI 10.1109/TNANO.2008.2004706
View details for Web of Science ID 000262861500002
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Imperfection-Immune VLSI Logic Circuits using Carbon Nanotube Field Effect Transistors
Design, Automation and Test in Europe Conference and Exhibition
IEEE. 2009: 436–441
View details for Web of Science ID 000273246700078
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Carbon Nanotube Circuits in the Presence of Carbon Nanotube Density Variations
46th ACM/IEEE Design Automation Conference (DAC 2009)
IEEE. 2009: 71–76
View details for Web of Science ID 000279394200016
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VMR: VLSI-Compatible Metallic Carbon Nanotube Removal for Imperfection-Immune Cascaded Multi-Stage Digital Logic Circuits using Carbon Nanotube FETs
IEEE International Electron Devices Meeting (IEDM 2009)
IEEE. 2009: 535–538
View details for Web of Science ID 000279343900139
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Digital VLSI Logic Technology using Carbon Nanotube FETs: Frequently Asked Questions
46th ACM/IEEE Design Automation Conference (DAC 2009)
IEEE. 2009: 304–309
View details for Web of Science ID 000279394200064
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IFRA: Post-Silicon Bug Localization in Processors
IEEE International High Level Design Validation and Test Workshop
IEEE. 2009: 154–159
View details for Web of Science ID 000278575200023
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EXPERIMENTAL STUDY OF GATE OXIDE EARLY-LIFE FAILURES
47th Annual IEEE International Reliability Physics Symposium
IEEE. 2009: 650–658
View details for Web of Science ID 000272068100104
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Test Chip Experiments at Stanford CRC
International Test Conference 2009
IEEE. 2009: 593–593
View details for Web of Science ID 000279591000069
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Circuit-Level Performance Benchmarking and Scalability Analysis of Carbon Nanotube Transistor Circuits
IEEE International Solid-State Circuits Conference (ISSCC)
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. 2009: 37–45
View details for DOI 10.1109/TNANO.2008.2006903
View details for Web of Science ID 000262861500007
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CMOS-Analogous Wafer-Scale Nanotube-on-Insulator Approach for Submicrometer Devices and Integrated Circuits Using Aligned Nanotubes
NANO LETTERS
2009; 9 (1): 189-197
Abstract
Massive aligned carbon nanotubes hold great potential but also face significant integration/assembly challenges for future beyond-silicon nanoelectronics. We report a wafer-scale processing of aligned nanotube devices and integrated circuits, including progress on essential technological components such as wafer-scale synthesis of aligned nanotubes, wafer-scale transfer of nanotubes to silicon wafers, metallic nanotube removal and chemical doping, and defect-tolerant integrated nanotube circuits. We have achieved synthesis of massive aligned nanotubes on complete 4 in. quartz and sapphire substrates, which were then transferred to 4 in. Si/SiO(2) wafers. CMOS analogous fabrication was performed to yield transistors and circuits with features down to 0.5 mum, with high current density approximately 20 muA/mum and good on/off ratios. In addition, chemical doping has been used to build fully integrated complementary inverter with a gain approximately 5, and a defect-tolerant design has been employed for NAND and NOR gates. This full-wafer approach could serve as a critical foundation for future integrated nanotube circuits.
View details for DOI 10.1021/nl802756u
View details for Web of Science ID 000262519100035
View details for PubMedID 19086836
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A Metallic-CNT-Tolerant Carbon Nanotube Technology Using Asymmetrically-Correlated CNTs (ACCNT)
Symposium on VLSI Technology
JAPAN SOCIETY APPLIED PHYSICS. 2009: 182–183
View details for Web of Science ID 000275651200071
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Monolithic Three-Dimensional Integrated Circuits using Carbon Nanotube FETs and Interconnects
IEEE International Electron Devices Meeting (IEDM 2009)
IEEE. 2009: 539–542
View details for Web of Science ID 000279343900140
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Solution Assembly of Transistor Arrays Based on Sorted Nanotube Networks for Large-scale Flexible Electronic Applications
47th Annual Symposium of the Society-for-Information-Display
SOC INFORMATION DISPLAY. 2009: 877–879
View details for Web of Science ID 000272997600227
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Design methods for misaligned and mispositioned carbon-nanotube immune circuits
Symposium on VLSI Technology
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. 2008: 1725–36
View details for DOI 10.1109/TCAD.2008.2003278
View details for Web of Science ID 000259789400003
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Device study, chemical doping, and logic circuits based on transferred aligned single-walled carbon nanotubes
APPLIED PHYSICS LETTERS
2008; 93 (3)
View details for DOI 10.1063/1.2956677
View details for Web of Science ID 000257968700062
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The search for alternative computational paradigms
IEEE DESIGN & TEST OF COMPUTERS
2008; 25 (4): 334-343
View details for Web of Science ID 000257911000009
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The search for alternative computational paradigms
IEEE DESIGN & TEST OF COMPUTERS
2008; 25 (4): 334-343
View details for DOI 10.1109/MDT.2008.113
View details for Web of Science ID 000257911000009
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A joint search for gravitational wave bursts with AURIGA and LIGO
CLASSICAL AND QUANTUM GRAVITY
2008; 25 (9)
View details for DOI 10.1088/0264-9381/25/9/095004
View details for Web of Science ID 000255897000005
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Historical perspective on scan compression
IEEE DESIGN & TEST OF COMPUTERS
2008; 25 (2): 114-120
View details for Web of Science ID 000254642000003
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Historical perspective on scan compression
IEEE DESIGN & TEST OF COMPUTERS
2008; 25 (2): 114-120
View details for DOI 10.1109/MDT.2008.40
View details for Web of Science ID 000254642000003
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Integrated wafer-scale growth and transfer of directional carbon nanotubes and misaligned-carbon-nanotube-immune logic structures
Symposium on VLSI Technology
IEEE. 2008: 159–160
View details for Web of Science ID 000259442500078
- Design Guidelines for Metallic-Carbon-Nanotube-Tolerant Circuits 2008
- Imperfection-Immune Carbon Nanotube VLSI Logic Circuits 2008
- Soft Errors: System Effects, Protection Techniques and Case Studies Design Automation and Test in Europe 2008
- Historical Perspective of Scan Compression IEEE Design and Test of Computers 2008
- Soft Errors: Technology Trends, System Effects and Protection Techniques 2008
- Design Methods for Misaligned and Mis-positioned Carbon-Nanotube-Immune Circuits IEEE Trans. Computer-Aided Design 2008
- Globally Optimized Robust Systems to Overcome Scaled CMOS Challenges 2008
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CASP: Concurrent Autonomous chip self-test using Stored test Patterns
IEEE. 2008: 764-+
View details for Web of Science ID 000257940700131
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Circuit failure prediction for robust system design in scaled CMOS
IEEE, ELECTRON DEVICES SOC & RELIABILITY GROUP. 2008: 524-+
View details for DOI 10.1109/RELPHY.2008.4558940
View details for Web of Science ID 000257615900087
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Soft error resilient system design through error correction
SPRINGER. 2008: 143-+
View details for Web of Science ID 000251566700009
- Optimized Circuit Failure Prediction for Aging: Practicality and Promise 2008
- A Low-overhead Fault Tolerance Scheme for TSV-based 3D Network-on-Chip Links 2008
- Soft Errors: System Effects, Protection Techniques and Case Studies 2008
- VAST: Virtualization Assisted Concurrent Autonomous Self-Test 2008
- In Search of Alternative Computational Paradigms IEEE Design and Test of Computers 2008
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Circuit failure prediction for robust system design in scaled CMOS
46th Annual IEEE International Reliability Physics Symposium
IEEE, ELECTRON DEVICES SOC & RELIABILITY GROUP. 2008: 524–531
View details for Web of Science ID 000257615900087
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Soft error resilient system design through error correction
14th International Conference on Very Large Scale Integration of System on Chip
SPRINGER. 2008: 143–156
View details for Web of Science ID 000251566700009
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Globally optimized robust systems to overcome scaled CMOS reliability challenges
Design, Automation and Test in Europe Conference and Exhibition (DATE 08)
IEEE. 2008: 820–825
View details for Web of Science ID 000257940700141
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CASP: Concurrent Autonomous chip self-test using Stored test Patterns
Design, Automation and Test in Europe Conference and Exhibition (DATE 08)
IEEE. 2008: 764–769
View details for Web of Science ID 000257940700131
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Integrated wafer-scale growth and transfer of directional carbon nanotubes and misaligned-carbon-nanotube-immune logic structures
Symposium on VLSI Technology
IEEE. 2008: 205–206
View details for Web of Science ID 000259116200077
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Design guidelines for metallic-carbon-nanotube-tolerant digital logic circuits
Design, Automation and Test in Europe Conference and Exhibition (DATE 08)
IEEE. 2008: 888–893
View details for Web of Science ID 000257940700153
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Gate-oxide early life failure prediction
26th IEEE VLSI Test Symposium
IEEE COMPUTER SOC. 2008: 111–118
View details for DOI 10.1109/VTS.2008.55
View details for Web of Science ID 000256250900016
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IFRA: Instruction Footprint Recording and Analysis for post-silicon bug localization in processors
45th ACM/IEEE Design Automation Conference
IEEE. 2008: 373–378
View details for Web of Science ID 000258930200077
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Application-dependent delay testing of FPGAs
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
2007; 26 (3): 553-563
View details for DOI 10.1109/TCAD.2006.882503
View details for Web of Science ID 000244471200013
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Macro-model for post-breakdown 90nm and 130nm transistors and its applications in predicting chip-level function failure after ESD-CDM events
45th Annual IEEE International Reliability Physics Symposium
IEEE. 2007: 78–85
View details for Web of Science ID 000246989600013
- Design of Imperfection-Immune Carbon Nanotube Field Effect Transistor Circuits 2007
- Verification Guided Soft Error Resilience 2007
- Soft Errors: Technology Trends, System Effects and Protection Techniques 2007
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Erratic bit errors in latches
IEEE. 2007: 445-+
View details for DOI 10.1109/RELPHY.2007.369931
View details for Web of Science ID 000246989600072
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Macro-model for post-breakdown 90nm and 130nm transistors and its applications in predicting chip-level function failure after ESD-CDM events
IEEE. 2007: 78-+
View details for DOI 10.1109/RELPHY.2007.369872
View details for Web of Science ID 000246989600013
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Circuit failure prediction to overcome scaled CMOS reliability challenges
IEEE. 2007: 1000-1002
View details for Web of Science ID 000255939900110
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Built-in soft error resilience for robust system design
IEEE. 2007: 263-+
View details for Web of Science ID 000250332300064
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Verification-guided soft error resilience
Design, Automation and Test in Europe Conference and Exhibition (DATE 07)
IEEE. 2007: 1442–1447
View details for Web of Science ID 000252175700246
- California Scan: A Scan Architecture to Utilize Don't Care Bits in Test Patterns 2007
- Marco-model for Post-breakdown 90nm and 130nm Transistors and its Applications in Predicting Chip-level Function Failure after ESD-CDM Events 2007
- Soft Errors: Technology Trends, System Effects and Protection Techniques 2007
- Carbon Nanotube Transistor Circuits: Circuit-level Performance Benchmarking and Design Options for Living with Imperfections 2007
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California scan architecture for high quality and low power testing
IEEE International Test Conference
IEEE. 2007: 687–696
View details for Web of Science ID 000255939900075
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Automated design of misaligned-carbon-nanotube-immune circuits
44th ACM/IEEE Design Automation Conference
IEEE. 2007: 958–961
View details for Web of Science ID 000249725800191
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Built-in soft error resilience for robust system design
IEEE International Conference on Integrated Circuit Design and Technology
IEEE. 2007: 263–268
View details for Web of Science ID 000250332300064
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Circuit failure prediction enables robust system design resilient to aging and wearout
13th IEEE International On-Line Testing Symposium
IEEE COMPUTER SOC. 2007: 123–123
View details for Web of Science ID 000248534400021
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Erratic bit errors in latches
45th Annual IEEE International Reliability Physics Symposium
IEEE. 2007: 445–451
View details for Web of Science ID 000246989600072
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Circuit failure prediction and its application to transistor aging
25th IEEE VLSI Test Symposium
IEEE COMPUTER SOC. 2007: 277–284
View details for Web of Science ID 000246798100036
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Soft errors: Technology trends, system effects, and protection techniques
13th IEEE International On-Line Testing Symposium
IEEE COMPUTER SOC. 2007: 4–4
View details for Web of Science ID 000248534400001
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Circuit failure prediction to overcome scaled CMOS reliability challenges
IEEE International Test Conference
IEEE. 2007: 1000–1002
View details for Web of Science ID 000255939900110
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Sequential element design with built-in soft error resilience
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
2006; 14 (12): 1368-1378
View details for DOI 10.1109/TVLSI.2006.887832
View details for Web of Science ID 000243554300007
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XPAND: An efficient test stimulus compression technique
IEEE TRANSACTIONS ON COMPUTERS
2006; 55 (2): 163-173
View details for Web of Science ID 000234095200007
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Test compression for FPGAs
IEEE International Test Conference
IEEE. 2006: 540–548
View details for Web of Science ID 000245118400060
- Soft Errors: Technology Trends, System Effects and Protection Techniques 2006
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Test compression for FPGAs
IEEE. 2006: 540-+
View details for Web of Science ID 000245118400060
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Signature analyzer design for yield learning support
IEEE. 2006: 255-+
View details for Web of Science ID 000245118400029
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Combinational logic soft error correction
IEEE. 2006: 824-+
View details for Web of Science ID 000245118400092
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How to safeguard your sensitive data
IEEE COMPUTER SOC. 2006: 199-211
View details for Web of Science ID 000242572700018
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Radiation-induced soft error rates of advanced CMOS bulk devices
44th Annual IEEE International Reliability Physics Symposium
IEEE. 2006: 217–225
View details for Web of Science ID 000240855800035
- Comparison of Test Metrics: Stuck-at, N-Detect and Gate-Exhaustive 2006
- XPAND: An Efficient Test Stimulus Compression Technique IEEE Trans. Computers, Special Issue on System-on-Chip Design and Test 2006
- Radiation Induced Soft Error Rates of Advanced CMOS Bulk Devices 2006
- Designing Circuits with Carbon Nanotubes: Open Questions and Some Directions 2006
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Signature analyzer design for yield learning support
IEEE International Test Conference
IEEE. 2006: 255–264
View details for Web of Science ID 000245118400029
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Combinational logic soft error correction
IEEE International Test Conference
IEEE. 2006: 824–832
View details for Web of Science ID 000245118400092
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Soft error resilient system design through error correction
International Conference on Very Large Scale Integration and System-on-Chip
IFIP-INT FEDERATION INFORMATION PROCESSING. 2006: 332–337
View details for Web of Science ID 000243523900058
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How to safeguard your sensitive data
25th IEEE Symposium on Reliable Distributed Systems
IEEE COMPUTER SOC. 2006: 199–211
View details for Web of Science ID 000242572700018
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Application-independent testing of FPGA interconnects
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
2005; 24 (11): 1774-1783
View details for DOI 10.1109/TCAD.2005.852452
View details for Web of Science ID 000232971600010
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X-tolerant test response compaction
10th IEEE European Test Symposium (ETS 2005)
IEEE COMPUTER SOC. 2005: 566–74
View details for Web of Science ID 000233030500011
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Carbon nanotube synthesis, characteristics, and microbattery applications
3rd Conference on Thin Films and Nanomaterials for Energy Conversion and Storage
ELSEVIER SCIENCE SA. 2005: 363–68
View details for DOI 10.1016/j.mseb.2004.05.049
View details for Web of Science ID 000227056500020
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Optimized reseeding by seed ordering and encoding
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
2005; 24 (2): 264-270
View details for DOI 10.1109/TCAD.2004.840550
View details for Web of Science ID 000226478700010
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Robust system design with built-in soft-error resilience
COMPUTER
2005; 38 (2): 43-?
View details for Web of Science ID 000227169900013
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Response compaction with any number of unknowns using a new LFSR architecture
42nd Design Automation Conference
IEEE COMPUTER SOC. 2005: 117–122
View details for Web of Science ID 000230430300024
- Test Response Compression with Any Number of Unknowns 2005
- Robust Platform Design in Sub-65nm Technologies 2005
- Fault Diagnosis with X-Compact 2005
- Logic Soft Errors in Sub-65nm Technologies: Design and CAD Challenges 2005
- Recent Advances in Hardware-Level Reliability Support for Transient Errors IEEE MICRO, Special Issue on the Reliability-Aware Microarchitectures 2005
- Application Independent Testing of FPGA Interconnects IEEE Trans. CAD 2005
- Robust System Design with Built-In Soft Error Resilience IEEE Computer 2005; 38 (2): 43-52
- Testing Nanometer Integrated Circuits: Myths, Reality and the Road Ahead 2005
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Robust platform design in advanced VLSI technologies
IEEE Custom Integrated Circuits Conference
IEEE. 2005: 23–30
View details for Web of Science ID 000234406600004
- Logic Soft Errors: A Major Barrier to Robust Platform Design 2005
- DFT Assisted Built-In Soft Error Resilience 2005
- Built-In Soft Error Resilience Techniques 2005
- Built-In Soft Error Resilience Structures 2005
- Gate Exhaustive Testing 2005
- Enabling Yield Analysis with X-Compact 2005
- Robust System Design from Unreliable Components 2005
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Efficient design diversity estimation for combinational circuits
IEEE TRANSACTIONS ON COMPUTERS
2004; 53 (11): 1483-1492
View details for Web of Science ID 000223872800011
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Reconfigurable architecture for autonomous self-repair
IEEE DESIGN & TEST OF COMPUTERS
2004; 21 (3): 228-240
View details for Web of Science ID 000221577000011
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Techniques and algorithms for fault grading of FPGA interconnect test configurations
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
2004; 23 (2): 261-272
View details for DOI 10.1109/TCAD.2003.822112
View details for Web of Science ID 000188604300007
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X-tolerant signature analysis
35th International Test Conference
IEEE. 2004: 432–441
View details for Web of Science ID 000225277600046
- ELF-MURPHY Data on Defects and Test Sets 2004
- Elimination of System Test from Production Test Flow 2004
- Defect and Fault Tolerance for Reconfigurable Molecular Computing 2004
- Delay Defect Screening using Process Monitor Structures 2004
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ELF-Murphy data on defects and test sets
22nd IEEE VLSI Test Symsposium
IEEE COMPUTER SOC. 2004: 16–22
View details for Web of Science ID 000221539900002
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Delay defect screening using process monitor structures
22nd IEEE VLSI Test Symsposium
IEEE COMPUTER SOC. 2004: 43–48
View details for Web of Science ID 000221539900006
- Fault-Tolerance Encyclopedia on Computer Science and Engineering CRC Press. 2004: 1
- XPAND: Test Stimulus Compression for Intel Designs 2004
- X-Compact: An Efficient Response Compaction Technique IEEE Trans. Computer-Aided Design 2004; 23 (`3): 421-432
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Speed clustering of integrated circuits
35th International Test Conference
IEEE. 2004: 1128–1137
View details for Web of Science ID 000225277600124
- Xpand + X-Compact: What did we Learn? 2004
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Defect and fault tolerance of reconfigurable molecular computing
12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
IEEE COMPUTER SOC. 2004: 176–185
View details for Web of Science ID 000225131700017
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Interconnect delay testing of designs on programmable logic devices
35th International Test Conference
IEEE. 2004: 635–644
View details for Web of Science ID 000225277600068
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Test data compression
IEEE DESIGN & TEST OF COMPUTERS
2003; 20 (2): 76-87
View details for Web of Science ID 000181420400015
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X-codes: Error control with unknowable inputs
IEEE International Symposium on Information Theory
IEEE. 2003: 102–102
View details for Web of Science ID 000186112600102
- XMAX: X-Tolerant Architecture for Maximal Test Compression 2003
- Design for Guaranteed Test Stimulus Compression 2003
- Analysis of X-Compact for Intel ASIC Designs 2003
- H-DFT: A Hybrid DFT Architecture for Low-Cost High Quality Structural Testing 2003
- Soft Errors in Digital Logic 2003
- Robust System Design Hotchips 2003
- Delay Defect Characteristics and Testing Strategies IEEE Design and Test of Computers, Special Issue on Speed Test and Speed Binning of Complex ICs 2003; 20 (5): 8-16
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Automatic configuration generation for FPGA interconnect testing
21st IEEE VLSI Test Symposium
IEEE COMPUTER SOC. 2003: 134–139
View details for Web of Science ID 000183013100018
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BIST reseeding with very few seeds
21st IEEE VLSI Test Symposium
IEEE COMPUTER SOC. 2003: 69–74
View details for Web of Science ID 000183013100009
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Efficient seed utilization for reseeding based compression
21st IEEE VLSI Test Symposium
IEEE COMPUTER SOC. 2003: 232–237
View details for Web of Science ID 000183013100030
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A design diversity metric and analysis of redundant systems
IEEE TRANSACTIONS ON COMPUTERS
2002; 51 (5): 498-510
View details for Web of Science ID 000175244500005
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(EDI)-I-4: Error detection by diverse data and duplicated instructions
IEEE TRANSACTIONS ON COMPUTERS
2002; 51 (2): 180-199
View details for Web of Science ID 000173677100007
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Test vector compression using EDA-ATE synergies
20th IEEE VLSI Test Symposium (VTS 02)
IEEE COMPUTER SOC. 2002: 97–102
View details for Web of Science ID 000176201400016
- Dependable Reconfigurable Computing: Design Diversity and Self-Repair 2002
- X-Compact: An Efficient Response Compaction Technique for Test Cost Reduction 2002
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Design for testability and testing of IEEE 1149.1 tap controller
20th IEEE VLSI Test Symposium (VTS 02)
IEEE COMPUTER SOC. 2002: 247–252
View details for Web of Science ID 000176201400040
- Efficient Response Compaction 2002
- Design for Testability and Testing of IEEE 1149.1 TAP Controller 2002
- Packet Based Test Vector Compression Techniques 2002
- ED4I: Error Detection by Diverse Data and Duplicated Instructions IEEE Trans. on Computers, Special Issue on Fault-Tolerant Embedded Systems 2002; 51 (2): 180-199
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Testing digital circuits with constraints
17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
IEEE COMPUTER SOC. 2002: 195–203
View details for Web of Science ID 000179481000021
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Packet-based input test data compression techniques
International Test Conference
IEEE. 2002: 154–163
View details for Web of Science ID 000180001500025
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Fault grading FPGA interconnect test configurations
International Test Conference
IEEE. 2002: 608–617
View details for Web of Science ID 000180001500077
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Design diversity for concurrent error detection in sequential logic circuits
19th IEEE VLSI Test Symposium (VTS 2001)
IEEE COMPUTER SOC. 2001: 178–183
View details for Web of Science ID 000169368600026
- Fast Run-Time Fault Location for Dependable FPGA Applications 2001
- An Evaluation of Pseudo-Random Testing for Detecting Real Defects 2001
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Techniques for estimation of design diversity for combinational logic circuits
International Conference on Dependable Systems and Networks (DSN 2001)
IEEE COMPUTER SOC. 2001: 25–34
View details for Web of Science ID 000171088900003
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Design of redundant systems protected against common-mode failures
19th IEEE VLSI Test Symposium (VTS 2001)
IEEE COMPUTER SOC. 2001: 190–195
View details for Web of Science ID 000169368600028
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Fast run-time fault location in dependable FPGA-based applications
DFT/IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
IEEE COMPUTER SOC. 2001: 206–214
View details for Web of Science ID 000174007800026
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Diversity techniques for concurrent error detection
IEEE 2nd International Symposium on Quality Electronic Design (ISQED 2001)
IEEE COMPUTER SOC. 2001: 249–250
View details for Web of Science ID 000168102000038
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Efficient multiplexer synthesis techniques
IEEE DESIGN & TEST OF COMPUTERS
2000; 17 (4): 90-97
View details for Web of Science ID 000166137600010
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Common-mode failures in redundant VLSI systems: A survey
IEEE TRANSACTIONS ON RELIABILITY
2000; 49 (3): 285-295
View details for Web of Science ID 000167886800005
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Dependable computing and online testing in adaptive and configurable systems
IEEE DESIGN & TEST OF COMPUTERS
2000; 17 (1): 29-41
View details for Web of Science ID 000085569300010
- Fault Escapes in Duplex Systems 2000
- Dependable Computing and On-Line Testing in Adaptive and Reconfigurable Systems IEEE Design and Test of Computers, Special Issue on Reconfigurable Computing 2000; 17 (1): 29-41
- DUDES: A Fault Abstraction and Collapsing Framework for Asynchronous Circuits 2000
- WORD VOTER: A New Voter Design for Triple Modular Redundant Systems 2000
- Efficient Multiplexer Synthesis IEEE Design and Test of Computers 2000; 17 (4): 90-97
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Which concurrent error detection scheme to choose?
International Test Conference
IEEE. 2000: 985–994
View details for Web of Science ID 000166038000115
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Combinational logic synthesis for diversity in duplex systems
International Test Conference
IEEE. 2000: 179–188
View details for Web of Science ID 000166038000023
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An output encoding problem and a solution technique
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
1999; 18 (6): 761-768
View details for Web of Science ID 000080532200007
- A Design Diversity Metric and Reliability Analysis For Redundant Systems 1999
- Fault-Tolerance Projects at Stanford CRC 1999
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VLSI architecture of a cellular automata machine
COMPUTERS & MATHEMATICS WITH APPLICATIONS
1997; 33 (5): 79-94
View details for Web of Science ID A1997WT19300008
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An output encoding problem and a solution technique
1997 IEEE/ACM International Conference on Computer-Aided Design (ICCAD 97)
I E E E, COMPUTER SOC PRESS. 1997: 304–307
View details for Web of Science ID A1997BK01U00045
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Scan synthesis for one-hot signals
International Test Conference 1997 (ITC)
IEEE. 1997: 714–722
View details for Web of Science ID 000071293600090