Subhasish Mitra

William E. Ayer Professor of Electrical Engineering and Professor of Computer Science

Web page: http://web.stanford.edu/people/subh

Bio

Subhasish Mitra holds the William E. Ayer Endowed Chair Professorship in the Departments of Electrical Engineering and Computer Science at Stanford University. He directs the Stanford Robust Systems Group, serves on the leadership team of the Microelectronics Commons AI Hardware Hub funded by the US CHIPS and Science Act, leads the Computation Focus Area of the Stanford SystemX Alliance, and is the Associate Chair (Faculty Affairs) of Computer Science. His research ranges across Robust Computing, NanoSystems, Electronic Design Automation (EDA), and Neurosciences. Results from his research group have influenced almost every contemporary electronic system and have inspired significant government and research initiatives in multiple countries. He has held several international academic appointments — the Carnot Chair of Excellence in NanoSystems at CEA-LETI in France, Invited Professor at EPFL in Switzerland, and Visiting Professor at the University of Tokyo in Japan. Prof. Mitra also has consulted for major technology companies including AMD (XIlinx), Cisco, Google, Intel, Merck (EMD Electronics), and Samsung.

In the field of Robust Computing, he has created many key approaches for circuit failure prediction, on-line diagnostics, QED system validation, soft error resilience, and X-Compact test compression. Their adoption by industry is growing rapidly, in markets ranging from cloud computing to automotive systems, under various names (System Lifecycle Management, Predictive Health Monitoring, In-System Test Architecture, In-field Scan). His X-Compact approach has proven essential to cost-effective manufacturing and high-quality testing of almost all 21st century systems. X-Compact and its derivatives enabled billions of dollars of cost savings across the industry.

In the field of NanoSystems, with his students and collaborators, he demonstrated several firsts: the first NanoSystems hardware among all beyond-silicon nanotechnologies for energy-efficient computing (the carbon nanotube computer), the first 3D NanoSystem with computation immersed in data storage, the first published end-to-end computing systems using resistive memories (Resistive RAM-based non-volatile computing systems delivering 10-fold energy efficiency versus embedded flash), and the first monolithic 3D integration combining heterogeneous logic and memory technologies in a silicon foundry. These received wide recognition: cover of NATURE, several Highlights to the US Congress, and highlight as "important scientific breakthrough" by news organizations worldwide.

Prof. Mitra's honors include the Harry H. Goode Memorial Award (by IEEE Computer Society for outstanding contributions in the information processing field), Newton Technical Impact Award in EDA (test-of-time honor by ACM SIGDA and IEEE CEDA), the University Researcher Award (by Semiconductor Industry Association and Semiconductor Research Corporation to recognize lifetime research contributions), the EDAA Achievement Award (by European Design and Automation Association, given to individuals who made outstanding contributions to electronic design, automation and testing in their life), the Intel Achievement Award (Intel’s highest honor), and the Distinguished Alumnus Award from the Indian Institute of Technology, Kharagpur. He and his students have published over 15 award-winning papers across 5 topic areas (technology, circuits, EDA, test, verification) at major venues including the Design Automation Conference, International Electron Devices Meeting, International Solid-State Circuits Conference, International Test Conference, Symposia on VLSI Technology/VLSI Circuits, and Formal Methods in Computer-Aided Design. Stanford undergraduates have honored him several times "for being important to them." He is a Fellow of the Association for Computing Machinery (ACM) and the Institute of Electrical and Electronics Engineers (IEEE), and a Foreign Member of Academia Europaea.

Academic Appointments

Professor, Electrical Engineering
Professor, Computer Science
Member, Bio-X
Member, Wu Tsai Human Performance Alliance
Member, Wu Tsai Neurosciences Institute

Administrative Appointments

Associate Chair, Faculty Affairs, Department of Computer Science, Stanford University (2021 - Present)

Honors & Awards

Achievement Award, lifetime honor for outstanding contributions to design/design automation/testing, European Design and Automation Association (EDAA) (2025)
Roger A. Haken Best Student Paper Award, IEEE International Electron Devices Meeting (with Stanford advisee) (2024)
Top Picks in Hardware Security, IEEE (2024)
Best Student Paper Award, Symposium on VLSI Technology (with Stanford advisees) (2023)
Top Picks in Test and Reliability, IEEE (2023)
William E. Ayer Endowed Chair Professorship, Stanford University (2023)
Distinguished Alumnus Award, Indian Institute of Technology, Kharagpur (2022)
Harry H. Goode Memorial Award, IEEE Computer Society (2022)
Best Student Paper Award, Symposium on VLSI Circuits (with Stanford advisees) (2021)
Foerign Member, Academia Europaea (2021)
University Researcher Award for lifetime research contributions to the U.S. semiconductor industry, Jointly by Semiconductor Industry Association (SIA) and Semiconductor Research Corporation (SRC) (2021)
Honorable Mention Paper, Formal Methods in Computer-Aided Design (2020)
Humboldt Prize (Humboldt Research Award), Alexander von Humboldt Foundation, Germany (2019)
Faculty Research Award, Google (2018)
Ten Year Retrospective Most Influential Paper Award, IEEE International Conference on Computer-Aided Design (2018)
Carnot Chair of Excellence in NanoSystems, CEA-LETI, Grenoble, France (2017-2020)
Best of SELSE, IEEE International Conference on Dependable Systems and Networks (2016)
Special recognition for carbon nanotube research, SEMI, the global microelectronics industry association (2016)
Best Paper Award, IEEE International Test Conference (2015)
Technical Excellence Award, Semiconductor Research Corporation (SRC) (2015)
A. Richard Newton Technical Impact Award in Electronic Design Automation (test of time honor), ACM SIGDA & IEEE CEDA (2014)
Fellow, Association for Computing Machinery (ACM) (2014)
Fellow, Institute of Electrical and Electronics Engineers (IEEE) (2013)
Jack Raper Award for Outstanding Technology Directions Paper, IEEE International Solid-State Circuits Conference (2013)
Kavli Foundation Fellow, United States National Academy of Sciences (2013)
World Economic Forum Young Scientist, World Economic Forum (2013)
Chambers Faculty Scholar, Stanford School of Engineering (2011)
Best Paper Award, IEEE VLSI Test Symposium (2010)
Best Student Paper Award, IEEE International Test Conference (with Stanford advsees) (2010)
Research Highlight, Communications of the ACM (2010)
Honored by graduating seniors as a Stanford professor who had been important to them, Stanford University School of Engineering (2009-2021)
Invited Participant, National Academy of Engineering, US Frontiers of Engineering Symposium (2009)
Okawa Foundation Research Grant, Okawa Foundation for Information and Telecommunications, Japan (2009)
Best Paper Award, ACM/IEEE Design Automation Conference (2008)
Best Student Paper Award, Symposium on VLSI Technology (with Stanford advisees) (2008)
Outstanding New Faculty Award, ACM SIGDA (2008)
Presidential Early Career Award for Scientists and Engineers (PECASE), The White House, the United States government (2008)
IBM Faculty Award, IBM (2006, 2007, 2008)
Terman Fellow, Stanford University (2006)
Best Paper Award, Intel Design and Test Technology Conference (2005)
Divisional Recognition award (for Breakthrough Soft Error Protection Technology), Intel Corporation (2005)
Donald O. Pederson Outstanding Paper Award, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2005)
Inaugural S. Seshu Scholar Lecturer, Coordinated Science Laboratory, University of Illinois at Urbana-Champaign (2005)
Intel Achievement Award, Intel’s highest corporate honor, Intel Corporation (For the development and deployment of a breakthrough test compression technology) (2004)
Divisional Recognition award, Intel Corporation (For Development and Proliferation of Industry Leading Response Compactor Design) (2002)
Silver medal recipient for highest rank among all M. Tech students, Indian Institute of Technology, Kharagpur (1996)
Cadence Fellowship, Indian Institute of Technology, Kharagpur (1994-1996)
Gold medals for Rank 1 in engineering during all four years of undergraduate study, Jadavpur University, India (1994)

Program Affiliations

Stanford SystemX Alliance

Contact

Academic
subh@stanford.edu
University - Faculty Department: Electrical Engineering Position: Wiiliam E. Ayer Professor
- 353 Jane Stanford Way
- Gates 411
- Stanford, California 94305
University - Faculty Department: Computer Science Position: William E. Ayer Professor
- 353 Jane Stanford Way
- Gates 411
- Stanford, California 94305

Administrator Maria Hu Administrative Associate mariasal@stanford.edu
- (650) 723-1458 (office)

Additional Info

Mail Code: 9030
ORCID:
https://orcid.org/0000-0002-5572-5194

All Publications

CLEAR Cross-Layer Resilience: A Retrospective IEEE DESIGN & TEST Cheng, E., Cho, H., Mirkhani, S., Szafaryn, L., Abraham, J., Bose, P., Cher, C., Lilja, K., Skadron, K., Stan, M., Mitra, S. 2025; 42 (3): 74-85

View details for DOI 10.1109/MDAT.2024.3483028

View details for Web of Science ID 001471147300009
Monolithic 3-D Integration of Diverse Memories: Resistive Switching (RRAM) and Gain Cell (GC) Memory Integrated on Si CMOS IEEE TRANSACTIONS ON ELECTRON DEVICES Liu, S., Radway, R. M., Wang, X., Moro, F., Nodin, J., Jana, K., Yan, L., Du, S., Upton, L. R., Chen, W., Kang, J., Chen, J., Li, H., Andrieu, F., Vianello, E., Raina, P., Mitra, S., Wong, H. 2025

View details for DOI 10.1109/TED.2025.3556113

View details for Web of Science ID 001480280000001
Three-Independent-Gate Transistors: The Swiss Army Knife of Devices [Special Section on 2025 IEEE Kirchhoff Award] IEEE CIRCUITS AND SYSTEMS MAGAZINE Cadareanu, P., Mitra, S., Amaru, L., Gaillardon, P. 2025; 25 (2): 17-22

View details for DOI 10.1109/MCAS.2025.3531819

View details for Web of Science ID 001492691500008
Omni 3D: BEOL-Compatible 3-D Logic With Omnipresent Power, Signal, and Clock IEEE TRANSACTIONS ON ELECTRON DEVICES Choi, S., Gilardi, C., Gutwin, P., Radway, R. M., Srimani, T., Mitra, S. 2025; 72 (4): 2038-2045

View details for DOI 10.1109/TED.2025.3537955

View details for Web of Science ID 001457760300047
MINOTAUR: A Posit-Based 0.42-0.50-TOPS/W Edge Transformer Inference and Training Accelerator IEEE JOURNAL OF SOLID-STATE CIRCUITS Prabhu, K., Radway, R. M., Yu, J., Bartolone, K., Giordano, M., Peddinghaus, F., Urman, Y., Khwa, W., Chih, Y., Chang, M., Mitra, S., Raina, P. 2025; 60 (4): 1311-1323

View details for DOI 10.1109/JSSC.2025.3545731

View details for Web of Science ID 001456403900020
Understanding responses to multi-electrode epiretinal stimulation using a biophysical model. Journal of neural engineering Vilkhu, R., Vasireddy, P., Kish, K. E., Gogliettino, A. R., Lotlikar, A., Hottowy, P., Dabrowski, W., Sher, A., Litke, A. M., Mitra, S., Chichilnisky, E. J. 2024

Abstract

Neural interfaces are designed to evoke specific patterns of electrical activity in populations of neurons by stimulating with many electrodes. However, currents passed simultaneously through multiple electrodes often combine nonlinearly to drive neural responses, making evoked responses difficult to predict and control. This response nonlinearity could arise from the interaction of many excitable sites in each cell, any of which can produce a spike. However, this multi-site activation hypothesis is difficult to verify experimentally.We developed a biophysical model to study retinal ganglion cell (RGC) responses to multi-electrode stimulation and validated it using data collected from ex vivo preparations of the macaque retina using a microelectrode array (512 electrodes; 30µm pitch; 10µm diameter).First, the model was validated by using it to reproduce essential empirical findings from single-electrode recording and stimulation, including recorded spike voltage waveforms at multiple locations and sigmoidal responses to injected current. Then, stimulation with two electrodes was modeled to test how the positioning of the electrodes relative to the cell affected the degree of response nonlinearity. Currents passed through pairs of electrodes positioned near the cell body or far from the axon (>40 µm) exhibited approximately linear summation in evoking spikes. Currents passed through pairs of electrodes close to the axon summed linearly when their locations along the axon were similar, and nonlinearly otherwise. Over a range of electrode placements, several localized spike initiation sites were observed, and the number of these sites covaried with the degree of response nonlinearity. Similar trends were observed for three-electrode stimuli. All of these trends in the simulation were consistent with experimental observations.These findings support the multi-site activation hypothesis for nonlinear activation of neurons, providing a biophysical interpretation of previous experimental results and potentially enabling more efficient use of multi-electrode stimuli in future neural implants.

View details for DOI 10.1088/1741-2552/ada1fe

View details for PubMedID 39705808
VLSI Test and Trust Roundtable IEEE DESIGN & TEST Karri, R., Rajski, J., Aitken, R., Mitra, S., Tehranipoor, M. M. 2024; 41 (6): 84-94

View details for DOI 10.1109/MDAT.2024.3444745

View details for Web of Science ID 001343332400004
Precise control of neural activity using dynamically optimized electrical stimulation. eLife Shah, N. P., Phillips, A. J., Madugula, S., Lotlikar, A., Gogliettino, A. R., Hays, M. R., Grosberg, L., Brown, J., Dusi, A., Tandon, P., Hottowy, P., Dabrowski, W., Sher, A., Litke, A. M., Mitra, S., Chichilnisky, E. J. 2024; 13

Abstract

Neural implants have the potential to restore lost sensory function by electrically evoking the complex naturalistic activity patterns of neural populations. However, it can be difficult to predict and control evoked neural responses to simultaneous multi-electrode stimulation due to nonlinearity of the responses. We present a solution to this problem and demonstrate its utility in the context of a bidirectional retinal implant for restoring vision. A dynamically optimized stimulation approach encodes incoming visual stimuli into a rapid, greedily chosen, temporally dithered and spatially multiplexed sequence of simple stimulation patterns. Stimuli are selected to optimize the reconstruction of the visual stimulus from the evoked responses. Temporal dithering exploits the slow time scales of downstream neural processing, and spatial multiplexing exploits the independence of responses generated by distant electrodes. The approach was evaluated using an experimental laboratory prototype of a retinal implant: large-scale, high-resolution multi-electrode stimulation and recording of macaque and rat retinal ganglion cells ex vivo. The dynamically optimized stimulation approach substantially enhanced performance compared to existing approaches based on static mapping between visual stimulus intensity and current amplitude. The modular framework enabled parallel extensions to naturalistic viewing conditions, incorporation of perceptual similarity measures, and efficient implementation for an implantable device. A direct closed-loop test of the approach supported its potential use in vision restoration.

View details for DOI 10.7554/eLife.83424

View details for PubMedID 39508555
Lossless Phonon Transition Through GaN-Diamond and Si-Diamond Interfaces ADVANCED ELECTRONIC MATERIALS Malakoutian, M., Woo, K., Rich, D., Mandia, R., Zheng, X., Kasperovich, A., Saraswat, D., Soman, R., Jo, Y., Pfeifer, T., Hwang, T., Aller, H., Kim, J., Lyu, J., Mabrey, J., Rodriguez, T., Pomeroy, J., Hopkins, P. E., Graham, S., Smith, D. J., Mitra, S., Cho, K., Kuball, M., Chowdhury, S. 2024

View details for DOI 10.1002/aelm.202400146

View details for Web of Science ID 001265392700001
Future Design Direction for SRAM Data Array: Hierarchical Subarray With Active Interconnect IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS Liu, H., Gilardi, C., Salahuddin, S. M., Pei, Z., Schuddinck, P., Xiang, Y., Weckx, P., Hellings, G., Bardon, M., Ryckaert, J., Pan, C., Mitra, S., Catthoor, F. 2024

View details for DOI 10.1109/TCSI.2024.3410518

View details for Web of Science ID 001252498300001
EMBER: Efficient Multiple-Bits-Per-Cell Embedded RRAM Macro for High-Density Digital Storage IEEE JOURNAL OF SOLID-STATE CIRCUITS Levy, A., Upton, L. R., Scott, M. D., Rich, D., Khwa, W., Chih, Y., Chang, M., Mitra, S., Murmann, B., Raina, P. 2024

View details for DOI 10.1109/JSSC.2024.3387566

View details for Web of Science ID 001205858500001
Faulty Function Extraction for Defective Circuits Nigh, C., Purdy, R., Li, W., Mitra, S., Blanton, R. D., IEEE IEEE. 2024

View details for DOI 10.1109/ETS61313.2024.10567760

View details for Web of Science ID 001260970400042
Efficient Ultra-Dense 3D IC Power Delivery and Cooling Using 3D Thermal Scaffolding Rich, D., Srimani, T., Malakoutian, M., Chowdhury, S., Mitra, S., ACM ASSOC COMPUTING MACHINERY. 2024

View details for DOI 10.1145/3676536.3676760

View details for Web of Science ID 001479882200073
Cooling future system-on-chips with diamond inter-tiers CELL REPORTS PHYSICAL SCIENCE Malakoutian, M., Kasperovich, A., Rich, D., Woo, K., Perez, C., Soman, R., Saraswat, D., Kim, J., Noshin, M., Chen, M., Vaziri, S., Bao, X., Shih, C., Woon, W., Asheghi, M., Goodson, K. E., Liao, S., Mitra, S., Chowdhury, S. 2023; 4 (12)

View details for DOI 10.1016/j.xcrp.2023.101686

View details for Web of Science ID 001144107300001
Band-to-Band Tunneling Leakage Current Characterization and Projection in Carbon Nanotube Transistors. ACS nano Lin, Q., Gilardi, C., Su, S. K., Zhang, Z., Chen, E., Bandaru, P., Kummel, A., Radu, I., Mitra, S., Pitner, G., Wong, H. P. 2023

Abstract

Carbon nanotube (CNT) transistors demonstrate high mobility but also experience off-state leakage due to the small effective mass and band gap. The lower limit of off-current (IMIN) was measured in electrostatically doped CNT metal-oxide-semiconductor field-effect transistors (MOSFETs) across a range of band gaps (0.37 to 1.19 eV), supply voltages (0.5 to 0.7 V), and extension doping levels (0.2 to 0.8 carriers/nm). A nonequilibrium Green's function (NEGF) model confirms the dependence of IMIN on CNT band gap, supply voltage, and extension doping level. A leakage current design space across CNT band gap, supply voltage, and extension doping is projected based on the validated NEGF model for long-channel CNT MOSFETs to identify the appropriate device design choices. The optimal extension doping and CNT band gap design choice for a target off-current density are identified by including on-current projection in the leakage current design space. An extension doping level >0.5 carrier/nm is required for optimized on-current.

View details for DOI 10.1021/acsnano.3c04346

View details for PubMedID 37910857
Micro/Nano Circuits and Systems Design and Design Automation: Challenges and Opportunities PROCEEDINGS OF THE IEEE Cauwenberghs, G., Cong, J., Hu, X., Joshi, S., Mitra, S., Porod, W., Wong, H. 2023; 111 (6): 561-574

View details for DOI 10.1109/JPROC.2023.3276941

View details for Web of Science ID 001012667300001
An Exhaustive Approach to Detecting Transient Execution Side Channels in RTL Designs of Processors IEEE TRANSACTIONS ON COMPUTERS Fadiheh, M., Wezel, A., Mueller, J., Bormann, J., Ray, S., Fung, J. M., Mitra, S., Stoffel, D., Kunz, W. 2023; 72 (1): 222-235

View details for DOI 10.1109/TC.2022.3152666

View details for Web of Science ID 000899952600018
Thermal Scaffolding for Ultra-Dense 3D Integrated Circuits Rich, D., Kasperovich, A., Malakoutian, M., Radway, R. M., Hagiwara, S., Yoshikawa, T., Chowdhury, S., Mitra, S., IEEE IEEE. 2023

View details for DOI 10.1109/DAC56929.2023.10247815

View details for Web of Science ID 001073487300131
EMBER: A 100 MHz, 0.86 mm2, Multiple-Bits-per-Cell RRAM Macro in 40 nm CMOS with Compact Peripherals and 1.0 pJ/bit Read Circuitry Upton, L. R., Levy, A., Scott, M. D., Rich, D., Khwa, W., Chih, Y., Chang, M., Mitra, S., Raina, P., Murmann, B., IEEE IEEE. 2023: 469-472

View details for DOI 10.1109/ESSCIRC59616.2023.10268807

View details for Web of Science ID 001088613100118
G-QED: Generalized QED Pre-silicon Verification beyond Non-Interfering Hardware Accelerators Chattopadhyay, S., Devarajegowda, K., Zhao, B., Lonsing, F., D'Agostino, B. A., Vavelidou, I., Bhatt, V. D., Prebeck, S., Ecker, W., Trippel, C., Barrett, C., Mitra, S., IEEE IEEE. 2023

View details for DOI 10.1109/DAC56929.2023.10247903

View details for Web of Science ID 001073487300211
Efficient Modeling and Calibration of Multi-Electrode Stimuli for Epiretinal Implants Vasireddy, P. K., Gogliettino, A. R., Brown, J. B., Vilkhu, R. S., Madugula, S. S., Phillips, A. J., Mitra, S., Hottowy, P., Sher, A., Litke, A., Shah, N. P., Chichilnisky, E. J., IEEE IEEE. 2023

View details for DOI 10.1109/NER52421.2023.10123907

View details for Web of Science ID 001009053700189
Partitioned Temporal Dithering for Efficient Epiretinal Electrical Stimulation Lotlikar, A., Shah, N. P., Gogliettino, A. R., Vilkhu, R., Madugula, S., Grosberg, L., Hottowy, P., Sher, A., Litke, A., Chichilnisky, E. J., Mitra, S., IEEE IEEE. 2023

View details for DOI 10.1109/NER52421.2023.10123787

View details for Web of Science ID 001009053700072
Testbench on a Chip: A Yield Test Vehicle for Resistive Memory Devices Upton, L. R., Lallement, G., Scott, M. D., Taylor, J., Radway, R. M., Rich, D., Nelson, M., Mitra, S., Murmann, B., IEEE IEEE. 2023: 576-582

View details for DOI 10.1109/ISQED57927.2023.10129298

View details for Web of Science ID 001013619400081
Ultra-Dense 3D Physical Design Unlocks New Architectural Design Points with Large Benefits Srimani, T., Radway, R. M., Kim, J., Prabhu, K., Rich, D., Gilardi, C., Raina, P., Shulaker, M., Lim, S., Mitra, S., IEEE IEEE. 2023

View details for Web of Science ID 001027444200118
Three-Dimensional Stacked Neural Network Accelerator Architectures for AR/VR Applications IEEE MICRO Yang, L., Radway, R., Chen, Y., Wu, T., Liu, H., Ansari, E., Chandra, V., Mitra, S., Beigne, E. 2022; 42 (6): 116-124

View details for DOI 10.1109/MM.2022.3202254

View details for Web of Science ID 000878171600027
Extended Scale Length Theory for Low-Dimensional Field-Effect Transistors IEEE TRANSACTIONS ON ELECTRON DEVICES Gilardi, C., Bennett, R. A., Yoon, Y., Pop, E., Wong, H., Mitra, S. 2022

View details for DOI 10.1109/TED.2022.3190464

View details for Web of Science ID 000829075200001
CHIMERA: A 0.92-TOPS, 2.2-TOPS/W Edge AI Accelerator With 2-MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference IEEE JOURNAL OF SOLID-STATE CIRCUITS Prabhu, K., Gural, A., Khan, Z. F., Radway, R. M., Giordano, M., Koul, K., Doshi, R., Kustin, J. W., Liu, T., Lopes, G. B., Turbiner, V., Khwa, W., Chih, Y., Chang, M., Lallement, G., Murmann, B., Mitra, S., Raina, P. 2022

View details for DOI 10.1109/JSSC.2022.3140753

View details for Web of Science ID 000750226200001
PEPR: Pseudo-Exhaustive Physically-Aware Region Testing Li, W., Nigh, C., Duvalsaint, D., Mitra, S., Blanton, R. D., IEEE Comp Soc IEEE COMPUTER SOC. 2022: 314-323

View details for DOI 10.1109/ITC50671.2022.00083

View details for Web of Science ID 000918580100035
RADAR: A Fast and Energy-Efficient Programming Technique for Multiple Bits-Per-Cell RRAM Arrays IEEE TRANSACTIONS ON ELECTRON DEVICES Le, B. Q., Levy, A., Wu, T. F., Radway, R. M., Hsieh, E., Zheng, X., Nelson, M., Raina, P., Wong, H., Wong, S., Mitra, S. 2021; 68 (9): 4397-4403

View details for DOI 10.1109/TED.2021.3097975

View details for Web of Science ID 000686761500038
Split-Chip Design to Prevent IP Reverse Engineering IEEE DESIGN & TEST Pagliarini, S., Sweeney, J., Mai, K., Blanton, S., Pileggi, L., Mitra, S. 2021; 38 (4): 109-118

View details for DOI 10.1109/MDAT.2020.3033255

View details for Web of Science ID 000678331400021
Illusion of large on-chip memory by networked computing chips for neural network inference NATURE ELECTRONICS Radway, R. M., Bartolo, A., Jolly, P. C., Khan, Z. F., Le, B. Q., Tandon, P., Wu, T. F., Xin, Y., Vianello, E., Vivet, P., Nowak, E., Wong, H., Aly, M., Beigne, E., Wootters, M., Mitra, S. 2021

View details for DOI 10.1038/s41928-020-00515-3

View details for Web of Science ID 000607033100001
Automatic Identification of Axon Bundle Activation for Epiretinal Prosthesis IEEE TRANSACTIONS ON NEURAL SYSTEMS AND REHABILITATION ENGINEERING Tandon, P., Bhaskhar, N., Shah, N., Madugula, S., Grosberg, L., Fan, V. H., Hottowy, P., Sher, A., Litke, A. M., Chichilnisky, E. J., Mitra, S. 2021; 29: 2496-2502

Abstract

Retinal prostheses must be able to activate cells in a selective way in order to restore high-fidelity vision. However, inadvertent activation of far-away retinal ganglion cells (RGCs) through electrical stimulation of axon bundles can produce irregular and poorly controlled percepts, limiting artificial vision. In this work, we aim to provide an algorithmic solution to the problem of detecting axon bundle activation with a bi-directional epiretinal prostheses.The algorithm utilizes electrical recordings to determine the stimulation current amplitudes above which axon bundle activation occurs. Bundle activation is defined as the axonal stimulation of RGCs with unknown soma and receptive field locations, typically beyond the electrode array. The method exploits spatiotemporal characteristics of electrically-evoked spikes to overcome the challenge of detecting small axonal spikes.The algorithm was validated using large-scale, single-electrode and short pulse, ex vivo stimulation and recording experiments in macaque retina, by comparing algorithmically and manually identified bundle activation thresholds. For 88% of the electrodes analyzed, the threshold identified by the algorithm was within ±10% of the manually identified threshold, with a correlation coefficient of 0.95.This works presents a simple, accurate and efficient algorithm to detect axon bundle activation in epiretinal prostheses.The algorithm could be used in a closed-loop manner by a future epiretinal prosthesis to reduce poorly controlled visual percepts associated with bundle activation. Activation of distant cells via axonal stimulation will likely occur in other types of retinal implants and cortical implants, and the method may therefore be broadly applicable.

View details for DOI 10.1109/TNSRE.2021.3128486

View details for Web of Science ID 000730473200002

View details for PubMedID 34784278
Spatially Patterned Bi-electrode Epiretinal Stimulation for Axon Avoidance at Cellular Resolution. Journal of neural engineering Vilkhu, R. S., Madugula, S. S., Grosberg, L. E., Gogliettino, A. R., Hottowy, P., Dabrowski, W., Sher, A., Litke, A. M., Mitra, S., Chichilnisky, E. J. 2021

Abstract

Epiretinal prostheses are designed to restore vision to people blinded by photoreceptor degenerative diseases by stimulating surviving retinal ganglion cells (RGCs), which carry visual signals to the brain. However, inadvertent stimulation of RGCs at their axons can result in non-focal visual percepts, limiting the quality of artificial vision. Theoretical work has suggested that axon activation can be avoided with current stimulation designed to minimize the second spatial derivative of the induced extracellular voltage along the axon. However, this approach has not been verified experimentally at the resolution of single cells.In this work, a custom multi-electrode array (512 electrodes, 10 μm diameter, 60 μm pitch) was used to stimulate and record RGCs in macaque retina ex vivo at single-cell, single-spike resolution. RGC activation thresholds resulting from bi-electrode stimulation, which consisted of bipolar currents simultaneously delivered through two electrodes straddling an axon, were compared to activation thresholds from traditional single-electrode stimulation.On average, across three retinal preparations, the bi-electrode stimulation strategy reduced somatic activation thresholds (~21%) while increasing axonal activation thresholds (~14%), thus favoring selective somatic activation. Furthermore, individual examples revealed rescued selective activation of somas that was not possible with any individual electrode.This work suggests that a bi-electrode epiretinal stimulation strategy can reduce inadvertent axonal activation at cellular resolution, for high-fidelity artificial vision.

View details for DOI 10.1088/1741-2552/ac3450

View details for PubMedID 34710857
A Density Metric for Semiconductor Technology PROCEEDINGS OF THE IEEE Wong, H., Akarvardar, K., Antoniadis, D., Bokor, J., Hu, C., King-Liu, T., Mitra, S., Plummer, J. D., Salahuddin, S. 2020; 108 (4): 478–82

View details for DOI 10.1109/JPROC.2020.2981715

View details for Web of Science ID 000528671200001
Gap-free Processor Verification by S(2)QED and Property Generation Devarajegowda, K., Fadiheh, M., Singh, E., Barrett, C., Mitra, S., Ecker, W., Stoffel, D., Kunz, W., DiNatale, G., Bolchini, C., Vatajelu, E. I. IEEE. 2020: 526–31

View details for Web of Science ID 000610549200096
DECOY: DEflection-Driven HLS-Based Computation Partitioning for Obfuscating Intellectual PropertY Chen, J., Zaman, M., Makris, Y., Blanton, R., Mitra, S., Schafer, B., IEEE IEEE. 2020

View details for Web of Science ID 000628528400031
A Formal Approach for Detecting Vulnerabilities to Transient Execution Attacks in Out-of-Order Processors Fadiheh, M., Mueller, J., Brinkmannt, R., Mitra, S., Stoffel, D., Kunz, W., IEEE IEEE. 2020

View details for Web of Science ID 000628528400080
A-QED Verification of Hardware Accelerators Singh, E., Lonsing, F., Chattopadhyay, S., Strange, M., Wei, P., Zhang, X., Zhou, Y., Chen, D., Cong, J., Raina, P., Zhang, Z., Barrett, C., Mitra, S., IEEE IEEE. 2020

View details for Web of Science ID 000628528400220
Hybrid Quick Error Detection: Validation and Debug of SoCs Through High-Level Synthesis IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS Campbell, K., Lin, D., He, L., Yang, L., Gurumani, S. T., Rupnow, K., Mitra, S., Chen, D. 2019; 38 (7): 1345–58

View details for DOI 10.1109/TCAD.2018.2837103

View details for Web of Science ID 000472568000013
Resistive RAM Endurance: Array-Level Characterization and Correction Techniques Targeting Deep Learning Applications IEEE TRANSACTIONS ON ELECTRON DEVICES Grossi, A., Vianello, E., Sabry, M. M., Barlas, M., Grenouillet, L., Coignus, J., Beigne, E., Wu, T., Le, B. Q., Wootters, M. K., Zambelli, C., Nowak, E., Mitra, S. 2019; 66 (3): 1281–88

View details for DOI 10.1109/TED.2019.2894387

View details for Web of Science ID 000460970400022
Low-Temperature Side Contact to Carbon Nanotube Transistors: Resistance Distributions Down to 10 nm Contact Length NANO LETTERS Pitner, G., Hills, G., Llinas, J., Persson, K., Park, R., Bokor, J., Mitra, S., Wong, H. 2019; 19 (2): 1083–89

Abstract

Carbon nanotube field-effect transistors (CNFETs) promise to improve the energy efficiency, speed, and transistor density of very large scale integration circuits owing to the intrinsic thin channel body and excellent charge transport properties of carbon nanotubes. Low-temperature fabrication (e.g., <400 °C) is a key enabler for the monolithic three-dimensional (3D) integration of CNFET digital logic into a device technology platform that overcomes memory bandwidth bottlenecks for data-abundant applications such as big-data analytics and machine learning. However, high contact resistance for short CNFET contacts has been a major roadblock to establishing CNFETs as a viable technology because the contact resistance, in series with the channel resistance, reduces the on-state current of CNFETs. Additionally, the variation in contact resistance remains unstudied for short contacts and will further degrade the energy efficiency and speed of CNFET circuits. In this work, we investigate by experiments the contact resistance and statistical variation of room-temperature fabricated CNFET contacts down to 10 nm contact lengths. These CNFET contacts are ∼15 nm shorter than the state-of-the-art Si CMOS "7 nm node" contact length, allowing for multiple generations of future scaling of the transistor-contacted gate pitch. For the 10 nm contacts, we report contact resistance values down to 6.5 kΩ per source/drain contact for a single carbon nanotube (CNT) with a median contact resistance of 18.2 kΩ. The 10 nm contacts reduce the CNFET current by as little as 13% at VDS = 0.7 V compared with the best reported 200 nm contacts to date, corroborated by results in this work. Our analysis of RC from 232 single-CNT CNFETs between the long-contact (e.g., 200 nm) and short-contact (e.g., 10 nm) regimes quantifies the resistance variation and projects the impact on CNFET current variability versus the number of CNT in the transistor. The resistance distribution reveals contact-length-dependent RC variations become significant below 20 nm contact length. However, a larger source of CNFET resistance variation is apparent at all contact lengths used in this work. To further investigate the origins of this contact-length-independent resistance variation, we analyze the variation of RC in arrays of identical CNFETs along a single CNT of constant diameter and observe the random occurrence of high RC, even on correlated CNFETs.

View details for DOI 10.1021/acs.nanolett.8b04370

View details for Web of Science ID 000459222300060

View details for PubMedID 30677297
Optimization of Electrical Stimulation for a High-Fidelity Artificial Retina Shah, N. P., Madugula, S., Grosberg, L., Mena, G., Tandon, P., Hottowy, P., Sher, A., Litke, A., Mitra, S., Chichilnisky, E. J., IEEE IEEE. 2019: 714–18

View details for Web of Science ID 000469933200174
Unlocking the Power of Formal Hardware Verification with CoSA and Symbolic QED Lonsing, F., Ganesan, K., Mann, M., Nuthakki, S., Singh, E., Srouji, M., Yang, Y., Mitra, S., Barrett, C., IEEE IEEE. 2019

View details for Web of Science ID 000524676400055
Cross-Layer Resilience: Challenges, Insights, and the Road Ahead Cheng, E., Daniel-Mueller-Gritschneder, Abraham, J., Bose, P., Buyuktosunoglu, A., Chen, D., Cho, H., Li, Y., Sharif, U., Skadron, K., Stan, M., Schlichtmann, U., Mitra, S., ACM ASSOC COMPUTING MACHINERY. 2019

View details for DOI 10.1145/3316781.3323474

View details for Web of Science ID 000482058200198
A Data-Compressive Wired-OR Readout for Massively Parallel Neural Recording Muratore, D. G., Tandon, P., Wootters, M., Chichilnisky, E. J., Mitra, S., Murmann, B., IEEE IEEE. 2019

View details for Web of Science ID 000483076401065
Resistive RAM With Multiple Bits Per Cell: Array-Level Demonstration of 3 Bits Per Cell IEEE TRANSACTIONS ON ELECTRON DEVICES Le, B. Q., Grossi, A., Vianello, E., Wu, T., Lama, G., Beigne, E., Wong, H., Mitra, S. 2019; 66 (1): 641–46

View details for DOI 10.1109/TED.2018.2879788

View details for Web of Science ID 000454333500085
A 43pJ/Cycle Non-Volatile Microcontroller with 4.7 mu s Shutdown/Wake-up Integrating 2.3-bit/Cell Resistive RAM and Resilience Techniques Wu, T. F., Le, B. Q., Radway, R., Bartolo, A., Hwang, W., Jeong, S., Li, H., Tandon, P., Vianello, E., Vivet, P., Nowak, E., Wootters, M. K., Wong, H., Aly, M., Beigne, E., Mitra, S., Fujino, L. C., Anderson, J. H., Belostotski, L., Dunwell, D., Gaudet, Gulak, G., Haslett, J. W., Halupka, D., Smith, K. C. IEEE. 2019: 226-+

View details for Web of Science ID 000463153600071
The N3XT Approach to Energy-Efficient Abundant-Data Computing PROCEEDINGS OF THE IEEE Aly, M., Wu, T. F., Bartolo, A., Malviya, Y. H., Hwang, W., Hills, G., Markov, I., Wootters, M., Shulaker, M. M., Wong, H., Mitra, S. 2019; 107 (1): 19–48

View details for DOI 10.1109/JPROC.2018.2882603

View details for Web of Science ID 000454770800004
Processor Hardware Security Vulnerabilities and their Detection by Unique Program Execution Checking Fadiheh, M., Stoffel, D., Barrett, C., Mitra, S., Kunz, W., IEEE IEEE. 2019: 994–99

View details for Web of Science ID 000470666100185
Symbolic QED Pre-silicon Verification for Automotive Microcontroller Cores: Industrial Case Study Singh, E., Devarajegowda, K., Simon, S., Schnieder, R., Ganesan, K., Fadiheh, M., Stoffel, D., Kunz, W., Barrett, C., Ecker, W., Mitra, S., IEEE IEEE. 2019: 1000–1005

View details for Web of Science ID 000470666100186
Review of Methodologies for Pre- and Post-Silicon Analog Verification in Mixed-Signal SOCs Gielen, G., Xama, N., Ganesan, K., Mitra, S., IEEE IEEE. 2019: 1006–9

View details for Web of Science ID 000470666100187
Understanding Energy Efficiency Benefits of Carbon Nanotube Field-Effect Transistors for Digital VLSI IEEE TRANSACTIONS ON NANOTECHNOLOGY Hills, G., Bardon, M., Doornbos, G., Yakimets, D., Schuddinck, P., Baert, R., Jang, D., Mattii, L., Sherazi, S., Rodopoulos, D., Ritzenthaler, R., Lee, C., Thean, A., Radu, I., Spessot, A., Debacker, P., Catthoor, F., Raghavan, P., Shulaker, M. M., Wong, H., Mitra, S. 2018; 17 (6): 1259–69

View details for DOI 10.1109/TNANO.2018.2871841

View details for Web of Science ID 000449979300026
Hyperdimensional Computing Exploiting Carbon Nanotube FETs, Resistive RAM, and Their Monolithic 3D Integration IEEE JOURNAL OF SOLID-STATE CIRCUITS Wu, T. F., Li, H., Huang, P., Rahimi, A., Hills, G., Hodson, B., Hwang, W., Rabaey, J. M., Wong, H., Shulaker, M. M., Mitra, S. 2018; 53 (11): 3183–96

View details for DOI 10.1109/JSSC.2018.2870560

View details for Web of Science ID 000449108400016
ETISS-ML: A Multi-Level Instruction Set Simulator with RTL-level Fault Injection Support for the Evaluation of Cross-Layer Resiliency Techniques Mueller-Gritschneder, D., Dittrich, M., Weinzierl, J., Cheng, E., Mitra, S., Schlichtmann, U., IEEE IEEE. 2018: 609–12

View details for Web of Science ID 000435148800112
Exploratory logic synthesis for multiple independent gate FETs FUNCTIONALITY-ENHANCED DEVICES: AN ALTERNATIVE TO MOORE'S LAW Amaru, L., Gaillardon, P., Mitra, S., De Micheli, G., Gaillardon, P. E. 2018; 39: 255–72

View details for Web of Science ID 000479027300011
TRIG: Hardware Accelerator for Inference-Based Applications and Experimental Demonstration Using Carbon Nanotube FETs Hills, G., Bankman, D., Moons, B., Yang, L., Hillard, J., Kahng, A., Park, R., Verhelst, M., Murmann, B., Shulaker, M. M., Wong, H., Mitra, S., IEEE IEEE. 2018

View details for DOI 10.1145/3195970.3196132

View details for Web of Science ID 000446034500096
Future Interconnect Materials and System Integration Strategies for Data-Intensive Applications Apte, P., Salmon, T., Rice, R., Gerber, M., Beica, R., Calvert, J., Hemker, D., Dordi, Y., Ranjan, M., Ramalingam, S., Gandhi, J., Kaviani, A., Mitra, S., Wong, P., Lee, V., El-Sabry, M., IEEE IEEE. 2018

View details for Web of Science ID 000469095300021
Brain-Inspired Computing Exploiting Carbon Nanotube FETs and Resistive RAM: Hyperdimensional Computing Case Study Wu, T. F., Li, H., Huang, P., Rahimi, A., Rabaey, J. M., Wong, H., Shulaker, M. M., Mitra, S., IEEE IEEE. 2018: 492-+

View details for Web of Science ID 000459205600205
Coming Up N3XT, After 2D Scaling of Si CMOS Hwang, W., Wan, W., Mitra, S., Wong, H., IEEE IEEE. 2018

View details for Web of Science ID 000451218703201
Brain-Inspired Computing Exploiting Carbon Nanotube FETs and Resistive RAM: Hyperdimensional Computing Case Study Wu, T. F., Li, H., Huang, P., Rahimi, A., Rabaey, J. M., Wong, H., Shulaker, M. M., Mitra, S., IEEE IEEE. 2018

View details for Web of Science ID 000432256300204
Symbolic Quick Error Detection Using Symbolic Initial State for Pre-Silicon Verification Fadiheh, M., Urdahl, J., Nuthakki, S., Mitra, S., Barrett, C., Stoffel, D., Kunz, W., IEEE IEEE. 2018: 55–60

View details for Web of Science ID 000435148800010
Resistive RAM-Centric Computing: Design and Modeling Methodology IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS Li, H., Wu, T. F., Mitra, S., Wong, H. 2017; 64 (9): 2263–73

View details for DOI 10.1109/TCSI.2017.2709812

View details for Web of Science ID 000409058000005
System-Level Effects of Soft Errors in Uncore Components IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS Cho, H., Cheng, E., Shepherd, T., Cher, C., Mitra, S. 2017; 36 (9): 1497-1510

View details for DOI 10.1109/TCAD.2017.2651824

View details for Web of Science ID 000408149500007
Three-dimensional integration of nanotechnologies for computing and data storage on a single chip NATURE Shulaker, M. M., Hills, G., Park, R. S., Howe, R. T., Saraswat, K., Wong, H., Mitra, S. 2017; 547 (7661): 74-+

Abstract

The computing demands of future data-intensive applications will greatly exceed the capabilities of current electronics, and are unlikely to be met by isolated improvements in transistors, data storage technologies or integrated circuit architectures alone. Instead, transformative nanosystems, which use new nanotechnologies to simultaneously realize improved devices and new integrated circuit architectures, are required. Here we present a prototype of such a transformative nanosystem. It consists of more than one million resistive random-access memory cells and more than two million carbon-nanotube field-effect transistors-promising new nanotechnologies for use in energy-efficient digital logic circuits and for dense data storage-fabricated on vertically stacked layers in a single chip. Unlike conventional integrated circuit architectures, the layered fabrication realizes a three-dimensional integrated circuit architecture with fine-grained and dense vertical connectivity between layers of computing, data storage, and input and output (in this instance, sensing). As a result, our nanosystem can capture massive amounts of data every second, store it directly on-chip, perform in situ processing of the captured data, and produce 'highly processed' information. As a working prototype, our nanosystem senses and classifies ambient gases. Furthermore, because the layers are fabricated on top of silicon logic circuitry, our nanosystem is compatible with existing infrastructure for silicon-based technologies. Such complex nano-electronic systems will be essential for future high-performance and highly energy-efficient electronic systems.

View details for PubMedID 28682331
Activation of ganglion cells and axon bundles using epiretinal electrical stimulation. Journal of neurophysiology Grosberg, L. E., Ganesan, K., Goetz, G. A., Madugula, S. S., Bhaskhar, N., Fan, V., Li, P., Hottowy, P., Dabrowski, W., Sher, A., Litke, A. M., Mitra, S., Chichilnisky, E. J. 2017: jn 00750 2016-?

Abstract

Epiretinal prostheses for treating blindness activate axon bundles, causing large, arc-shaped visual percepts that limit the quality of artificial vision. Improving the function of epiretinal prostheses therefore requires understanding and avoiding axon bundle activation. This paper introduces a method to detect axon bundle activation based on its electrical signature, and uses the method to test whether epiretinal stimulation can directly elicit spikes in individual retinal ganglion cells without activating nearby axon bundles. Combined electrical stimulation and recording from isolated primate retina were performed using a custom multi-electrode system (512 electrodes, 10 μm diameter, 60 μm pitch). Axon bundle signals were identified by their bi-directional propagation, speed, and increasing amplitude as a function of stimulation current. The threshold for bundle activation varied across electrodes and retinas, and was in the same range as the threshold for activating retinal ganglion cells near their somas. In the peripheral retina, 45% of electrodes that activated individual ganglion cells (17% of all electrodes) did so without activating bundles. This permitted selective activation of 21% of recorded ganglion cells (7% of all ganglion cells) over the array. In the central retina, 75% of electrodes that activated individual ganglion cells (16% of all electrodes) did so without activating bundles. The ability to selectively activate a subset of retinal ganglion cells without axon bundles suggests a possible novel architecture for future epiretinal prostheses.

View details for DOI 10.1152/jn.00750.2016

View details for PubMedID 28566464
Hysteresis-Free Carbon Nanotube Field-Effect Transistors. ACS nano Park, R. S., Hills, G., Sohn, J., Mitra, S., Shulaker, M. M., Wong, H. P. 2017; 11 (5): 4785-4791

Abstract

While carbon nanotube (CNT) field-effect transistors (CNFETs) promise high-performance and energy-efficient digital systems, large hysteresis degrades these potential CNFET benefits. As hysteresis is caused by traps surrounding the CNTs, previous works have shown that clean interfaces that are free of traps are important to minimize hysteresis. Our previous findings on the sources and physics of hysteresis in CNFETs enabled us to understand the influence of gate dielectric scaling on hysteresis. To begin with, we validate through simulations how scaling the gate dielectric thickness results in greater-than-expected benefits in reducing hysteresis. Leveraging this insight, we experimentally demonstrate reducing hysteresis to <0.5% of the gate-source voltage sweep range using a very large-scale integration compatible and solid-state technology, simply by fabricating CNFETs with a thin effective oxide thickness of 1.6 nm. However, even with negligible hysteresis, large subthreshold swing is still observed in the CNFETs with multiple CNTs per transistor. We show that the cause of large subthreshold swing is due to threshold voltage variation between individual CNTs. We also show that the source of this threshold voltage variation is not explained solely by variations in CNT diameters (as is often ascribed). Rather, other factors unrelated to the CNTs themselves (i.e., process variations, random fixed charges at interfaces) are a significant factor in CNT threshold voltage variations and thus need to be further improved.

View details for DOI 10.1021/acsnano.7b01164

View details for PubMedID 28463503
Invited: A Systems Approach to Computing in Beyond CMOS Fabrics Patil, A., Shanbhag, N., Varshney, L., Pop, E., Wong, H., Mitra, S., Rabaey, J., Weldon, J., Pileggi, L., Manipatruni, S., Nikonov, D., Young, I., IEEE IEEE. 2017

View details for DOI 10.1145/3061639.3072943

View details for Web of Science ID 000424895400018
Device-Architecture Co-Design for Hyperdimensional Computing with 3D Vertical Resistive Switching Random Access Memory (3D VRRAM) Li, H., Wu, T. F., Mitra, S., Wong, H., IEEE IEEE. 2017

View details for Web of Science ID 000408991800057
Introduction to the January Special Issue on the 2016 IEEE International Solid-State Circuits Conference IEEE JOURNAL OF SOLID-STATE CIRCUITS Sylvester, D., Markovic, D., Genov, R., Kawasumi, A., Mitra, S. 2017; 52 (1): 3-7

View details for DOI 10.1109/JSSC.2016.2635358

View details for Web of Science ID 000395641800001
Cross-Layer Resilience in Low-Voltage Digital Systems: Key Insights Cheng, E., Abraham, J., Bose, P., Buyuktosunoglu, A., Campbell, K., Chen, D., Cher, C., Cho, H., Le, B., Lilja, K., Mirkhani, S., Skadron, K., Stan, M., Szafaryn, L., Vezyrtzis, C., Mitra, S., IEEE IEEE. 2017: 593–96

View details for DOI 10.1109/ICCD.2017.103

View details for Web of Science ID 000424789300093
E-QED: Electrical Bug Localization During Post-silicon Validation Enabled by Quick Error Detection and Formal Methods Singh, E., Barrett, C., Mitra, S., Majumdar, R., Kuncak SPRINGER INTERNATIONAL PUBLISHING AG. 2017: 104–25

View details for DOI 10.1007/978-3-319-63390-9_6

View details for Web of Science ID 000431900900006
Very Low Voltage (VLV) Design Bertran, R., Bose, P., Brooks, D., Burns, J., Buyuktosunoglu, A., Chandramoorthy, N., Cheng, E., Cochet, M., Eldridge, S., Friedman, D., Jacobson, H., Joshi, R., Mitra, S., Montoye, R., Paidimarri, A., Parida, P., Skadron, K., Stan, M., Swaminathan, K., Vega, A., Venkataramani, S., Vezyrtzis, C., Wei, G., Wellman, J., Ziegler, M., IEEE IEEE. 2017: 601–4

View details for DOI 10.1109/ICCD.2017.105

View details for Web of Science ID 000424789300095
Special Session Paper 3D Nanosystems Enable Embedded Abundant-Data Computing Hwang, W., Aly, M., Malviya, Y. H., Gao, M., Wu, T. F., Kozyrakis, C., Wong, H., Mitra, S., IEEE IEEE. 2017

View details for DOI 10.1145/3125502.3125531

View details for Web of Science ID 000425920100014
Symbolic Quick Error Detection for Pre-Silicon and Post-Silicon Validation: Frequently Asked Questions IEEE DESIGN & TEST Singh, E., Lin, D., Barrett, C., Mitra, S. 2016; 33 (6): 55-62

View details for DOI 10.1109/MDAT.2016.2590987

View details for Web of Science ID 000393047000009
Time-Based Sensor Interface Circuits in CMOS and Carbon Nanotube Technologies IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS Gielen, G., Van Rethy, J., Marin, J., Shulaker, M. M., Hills, G., Wong, H. P., Mitra, S. 2016; 63 (5): 577-586

View details for DOI 10.1109/TCSI.2016.2525098

View details for Web of Science ID 000379915500003
TPAD: Hardware Trojan Prevention and Detection for Trusted Integrated Circuits IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS Wu, T. F., Ganesan, K., Hu, Y. A., Wong, H. P., Wong, S., Mitra, S. 2016; 35 (4): 521-534

View details for DOI 10.1109/TCAD.2015.2474373

View details for Web of Science ID 000372995000001
Hysteresis in Carbon Nanotube Transistors: Measurement and Analysis of Trap Density, Energy Level, and Spatial Distribution ACS NANO Park, R. S., Shulaker, M. M., Hills, G., Liyanage, L. S., Lee, S., Tang, A., Mitra, S., Wong, H. P. 2016; 10 (4): 4599-4608

Abstract

We present a measurement technique, which we call the Pulsed Time-Domain Measurement, for characterizing hysteresis in carbon nanotube field-effect transistors, and demonstrate its applicability for a broad range of 1D and 2D nanomaterials beyond carbon nanotubes. The Pulsed Time-Domain Measurement enables the quantification (density, energy level, and spatial distribution) of charged traps responsible for hysteresis. A physics-based model of the charge trapping process for a carbon nanotube field-effect transistor is presented and experimentally validated using the Pulsed Time-Domain Measurement. Leveraging this model, we discover a source of traps (surface traps) unique to devices with low-dimensional channels such as carbon nanotubes and nanowires (beyond interface traps which exist in today's silicon field-effect transistors). The different charge trapping mechanisms for interface traps and surface traps are studied based on their temperature dependencies. Through these advances, we are able to quantify the interface trap density for carbon nanotube field-effect transistors (∼3 × 10(13) cm(-2) eV(-1) near midgap), and compare this against a range of previously studied dielectric/semiconductor interfaces.

View details for DOI 10.1021/acsnano.6b00792

View details for PubMedID 27002483
Nano-Engineered Architectures for Ultra-Low Power Wireless Body Sensor Nodes Braojos, R., Atienza, D., Aly, M., Wu, T. F., Wong, H., Mitra, S., Ansaloni, G., ACM ASSOC COMPUTING MACHINERY. 2016

View details for DOI 10.1145/2968456.2968464

View details for Web of Science ID 000390612700023
Transforming Nanodevices into Nanosystems: The N3XT 1,000X Mitra, S., IEEE IEEE. 2016: 6

View details for Web of Science ID 000386790400003
Transforming Nanodevices to Next Generation Nanosystems Shulaker, M., Hills, G., Wong, H., Mitra, S., Najjar, W., Gerstlauer, A. IEEE. 2016: 288–92

View details for Web of Science ID 000399143000038
Cross-Layer Resilience Mitra, S., IEEE IEEE. 2016

View details for Web of Science ID 000387103500039
CLEAR: Cross-Layer Exploration for Architecting Resilience Combining Hardware and Software Techniques to Tolerate Soft Errors in Processor Cores Cheng, E., Mirkhani, S., Szafaryn, L. G., Cher, C., Cho, H., Skadron, K., Stan, M. R., Lilja, K., Abraham, J. A., Bose, P., Mitra, S., ACM ASSOC COMPUTING MACHINERY. 2016

View details for DOI 10.1145/2897937.2897996

View details for Web of Science ID 000390302500068
Energy-Efficient Abundant-Data Computing: The N3XT 1,000x COMPUTER Aly, M. M., Gao, M., Hills, G., Lee, C., Pitner, G., Shulaker, M. M., Wu, T. F., Asheghi, M., Bokor, J., Franchetti, F., Goodson, K. E., Kozyrakis, C., Markov, I., Olukotun, K., Pileggi, L., Pop, E., Rabaey, J., Re, C., Wong, H. P., Mitra, S. 2015; 48 (12): 24-33

View details for Web of Science ID 000367689400005
New Logic Synthesis as Nanotechnology Enabler PROCEEDINGS OF THE IEEE Amaru, L., Gaillardon, P., Mitra, S., De Micheli, G. 2015; 103 (11): 2168-2195

View details for DOI 10.1109/JPROC.2015.2460377

View details for Web of Science ID 000364032300017
Rapid Co-Optimization of Processing and Circuit Design to Overcome Carbon Nanotube Variations IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS Hills, G., Zhang, J., Shulaker, M. M., Wei, H., Lee, C., Balasingam, A., Wong, H. P., Mitra, S. 2015; 34 (7): 1082-1095

View details for DOI 10.1109/TCAD.2015.2415492

View details for Web of Science ID 000356496100004
NSF expedition on variability-aware software: Recent results and contributions IT-INFORMATION TECHNOLOGY Wanner, L., Lai, L., Rahimi, A., Gottscho, M., Mercati, P., Huang, C., Sala, F., Agarwal, Y., Dolecek, L., Dutt, N., Gupta, P., Gupta, R., Jhala, R., Kumar, R., Lerner, S., Mitra, S., Nicolau, A., Rosing, T., Srivastava, M. B., Swanson, S., Sylvester, D., Zhou, Y. 2015; 57 (3): 181–98

View details for DOI 10.1515/itit-2014-1085

View details for Web of Science ID 000219329700005
IEEE D&T Roundtable to Cover ITC 2014 Panel on "Open Problems in Design, Verification, and Test: Why Is It (Not) Business as Usual?" IEEE DESIGN & TEST Mitra, S., Agarwala, S., Parekhji, R., Pateras, S., Senthinathan, R., Venkataraman, S., Puri, R. 2015; 32 (3): 41-47

View details for DOI 10.1109/MDAT.2015.2417800

View details for Web of Science ID 000356168900005
Monolithic 3D Integration: A Path From Concept To Reality Shulaker, M. M., Wu, T. F., Sabry, M. M., Wei, H., Wong, H., Mitra, S., IEEE IEEE. 2015: 1197–1202

View details for Web of Science ID 000380393200221
From Nanodevices to Nanosystems: The N3XT Information Technology Mitra, S., IEEE IEEE. 2015

View details for Web of Science ID 000370657300030
Quick Error Detection Tests with Fast Runtimes for Effective Post-Silicon Validation and Debug Lin, D., Eswaran, S., Kumar, S., Rentschler, E., Mitra, S., IEEE IEEE. 2015: 1168–73

View details for Web of Science ID 000380393200216
Time-Based Sensor Interface Circuits in Carbon Nanotube Technology Gielen, G., Van Rethy, J., Shulaker, M. M., Hills, G., Wong, H., Mitra, S., IEEE IEEE. 2015: 2924–27

View details for Web of Science ID 000371471003052
Efficient Soft Error Vulnerability Estimation of Complex Designs Mirkhani, S., Mitra, S., Cher, C., Abraham, J., IEEE IEEE. 2015: 103-108

View details for Web of Science ID 000380393200018
Multiple Independent Gate FETs: How Many Gates Do We Need? Amaru, L., Hills, G., Gaillardon, P., Mitra, S., De Micheli, G., IEEE IEEE. 2015: 243-248

View details for Web of Science ID 000380442800055
Efficient Metallic Carbon Nanotube Removal for Highly-Scaled Technologies Shulaker, M. M., Hills, G., Wu, T. F., Bao, Z., Wong, H., Mitra, S., IEEE IEEE. 2015

View details for Web of Science ID 000380472500209
Effective Post-Silicon Validation of System-on-Chips Using Quick Error Detection IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS Lin, D., Hong, T., Li, Y., Eswaran, S., Kumar, S., Fallah, F., Hakim, N., Gardner, D. S., Mitra, S. 2014; 33 (10): 1573-1590

View details for DOI 10.1109/TCAD.2014.2334301

View details for Web of Science ID 000344529700011
Carbon nanotubes for high-performance logic MRS BULLETIN Chen, Z., Wong, H. P., Mitra, S., Bol, A., Peng, L., Hills, G., Thissen, N. 2014; 39 (8): 719-726

View details for DOI 10.1557/mrs.2014.164

View details for Web of Science ID 000341107900014
Robust and Energy-Secure Systems IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS Vega, A., Sethumadhavan, S., Mitra, S. 2014; 4 (2): 165-168

View details for DOI 10.1109/JETCAS.2014.2315885

View details for Web of Science ID 000337906000001
Addressing failures in exascale computing INTERNATIONAL JOURNAL OF HIGH PERFORMANCE COMPUTING APPLICATIONS Snir, M., Wisniewski, R. W., Abraham, J. A., Adve, S. V., Bagchi, S., Balaji, P., Belak, J., Bose, P., Cappello, F., Carlson, B., Chien, A. A., Coteus, P., DeBardeleben, N. A., Diniz, P. C., Engelmann, C., Erez, M., Fazzari, S., Geist, A., Gupta, R., Johnson, F., Krishnamoorthy, S., Leyffer, S., Liberty, D., Mitra, S., Munson, T., Schreiber, R., Stearley, J., Van Hensbergen, E. 2014; 28 (2): 129-173

View details for DOI 10.1177/1094342014522573

View details for Web of Science ID 000336222700001
System Level Benchmarking with Yield-Enhanced Standard Cell Library for Carbon Nanotube VLSI Circuits ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS Bobba, S., Zhang, J., Gaillardon, P., Wong, H. P., Mitra, S., De Micheli, G. 2014; 10 (4)

View details for DOI 10.1145/2600073

View details for Web of Science ID 000336444700007
Carbon Nanotube Circuit Integration up to Sub-20 nm Channel Lengths ACS NANO Shulaker, M. M., Van Rethy, J., Wu, T. F., Liyanage, L. S., Wei, H., Li, Z., Pop, E., Gielen, G., Wong, H. P., Mitra, S. 2014; 8 (4): 3434-3443

Abstract

Carbon nanotube (CNT) field-effect transistors (CNFETs) are a promising emerging technology projected to achieve over an order of magnitude improvement in energy-delay product, a metric of performance and energy efficiency, compared to silicon-based circuits. However, due to substantial imperfections inherent with CNTs, the promise of CNFETs has yet to be fully realized. Techniques to overcome these imperfections have yielded promising results, but thus far only at large technology nodes (1 μm device size). Here we demonstrate the first very large scale integration (VLSI)-compatible approach to realizing CNFET digital circuits at highly scaled technology nodes, with devices ranging from 90 nm to sub-20 nm channel lengths. We demonstrate inverters functioning at 1 MHz and a fully integrated CNFET infrared light sensor and interface circuit at 32 nm channel length. This demonstrates the feasibility of realizing more complex CNFET circuits at highly scaled technology nodes.

View details for DOI 10.1021/nn406301r

View details for Web of Science ID 000334990600034

View details for PubMedID 24654597
Rethinking Error Injection for Effective Resilience Mirkhani, S., Cho, H., Mitra, S., Abraham, J. 2014
Sensor-to-Digital Interface Built Entirely with Carbon Nanotube FETs IEEE Journal on Solid-State Circuits, Special Issue on IEEE Intl. Solid-State Circuits Conf. Shulaker, M., Van Rethy, J., Hills, G., Wei, H., Chen, H., Gielen, G., Mitra, S. 2014
QED Post-Silicon Validation and Debug: Frequently Asked Questions Lin, D., Mitra, S. 2014
Advancements With Carbon Nanotube Digital Systems Shulaker, M., Hills, G., Wei, H., Chen, H., Patil, N., Wong, H., Mitra, S., IEEE IEEE. 2014: 319-321

View details for Web of Science ID 000356605200056
The Resilience Wall: Cross-Layer Solution Strategies Mitra, S., Bose, P., Cheng, E., Cher, C., Cho, H., Joshi, R., Kim, Y., Lefurgy, C. R., Li, Y., Rodbell, K. P., Skadron, K., Stathis, J., Szafaryn, L., IEEE IEEE. 2014

View details for Web of Science ID 000356616400075
Monolithic 3D Integration of Logic and Memory: Carbon Nanotube FETs, Resistive RAM, and Silicon FETs Shulaker, M. M., Wu, T. F., Pal, A., Zhao, L., Nishi, Y., Saraswat, K., Wong, H., Mitra, S., IEEE IEEE. 2014

View details for Web of Science ID 000370384800158
QED Post-Silicon Validation and Debug Invited Abstract Lin, D., Mitra, S., IEEE IEEE. 2014: 62

View details for Web of Science ID 000380456800143
Rethinking Error Injection for Effective Resilience Mirkhani, S., Cho, H., Mitra, S., Abraham, J. A., IEEE IEEE. 2014: 390-393

View details for Web of Science ID 000350791700073
High-Performance Carbon Nanotube Field-Effect Transistors Shulaker, M. M., Pitner, G., Hills, G., Giachino, M., Wong, H., Mitra, S., IEEE IEEE. 2014

View details for Web of Science ID 000370384800202
The Resilience Wall: Cross-Layer Solution Strategies Mitra, S., Bose, P., Cheng, E., Cher, C., Cho, H., Joshi, R., Kim, Y., Lefurgy, C. R., Li, Y., Rodbell, K. P., Skadron, K., Stathis, J., Szafaryn, L., IEEE IEEE. 2014

View details for Web of Science ID 000358865800003
Monolithic Three-Dimensional Integration of Carbon Nanotube FETs with Silicon CMOS Shulaker, M. M., Saraswat, K., Wong, H., Mitra, S., IEEE IEEE. 2014

View details for Web of Science ID 000380558800084
Robust Design and Experimental Demonstrations of Carbon Nanotube Digital Circuits 36th Annual IEEE Custom Integrated Circuits Conference (CICC) - The Showcase for Integrated Circuit Design in the Heart of Silicon Valley Hills, G., Shulaker, M., Wei, H., Chen, H., Wong, H. P., Mitra, S. IEEE. 2014

View details for Web of Science ID 000349122300058
QED Post-Silicon Validation and Debug: Frequently Asked Questions 19th Asia and South Pacific Design Automation Conference (ASP-DAC) Lin, D., Mitra, S. IEEE. 2014: 478–482

View details for Web of Science ID 000350791700088
Sensor-to-Digital Interface Built Entirely With Carbon Nanotube FETs IEEE JOURNAL OF SOLID-STATE CIRCUITS Shulaker, M. M., Van Rethy, J., Hills, G., Wei, H., Chen, H., Gielen, G., Wong, H. P., Mitra, S. 2014; 49 (1): 190-201

View details for DOI 10.1109/JSSC.2013.2282092

View details for Web of Science ID 000329052700018
Rethinking Error Injection for Effective Resilience 19th Asia and South Pacific Design Automation Conference (ASP-DAC) Mirkhani, S., Cho, H., Mitra, S., Abraham, J. A. IEEE. 2014: 390–393

View details for Web of Science ID 000350791700073
System-Level Benchmarking with Yield-Enhanced Standard Cell Library for Carbon Nanotube VLSI Circuits ACM Journal on Emerging Technologies in Computing Systems Bobba, S., Zhang, J., Gaillardon, P., E., Wong, H., S.P., Mitra, S., De Micheli, G. 2014
Carbon nanotube computer. Nature Shulaker, M. M., Hills, G., Patil, N., Wei, H., Chen, H., Wong, H. P., Mitra, S. 2013; 501 (7468): 526-530

Abstract

The miniaturization of electronic devices has been the principal driving force behind the semiconductor industry, and has brought about major improvements in computational power and energy efficiency. Although advances with silicon-based electronics continue to be made, alternative technologies are being explored. Digital circuits based on transistors fabricated from carbon nanotubes (CNTs) have the potential to outperform silicon by improving the energy-delay product, a metric of energy efficiency, by more than an order of magnitude. Hence, CNTs are an exciting complement to existing semiconductor technologies. Owing to substantial fundamental imperfections inherent in CNTs, however, only very basic circuit blocks have been demonstrated. Here we show how these imperfections can be overcome, and demonstrate the first computer built entirely using CNT-based transistors. The CNT computer runs an operating system that is capable of multitasking: as a demonstration, we perform counting and integer-sorting simultaneously. In addition, we implement 20 different instructions from the commercial MIPS instruction set to demonstrate the generality of our CNT computer. This experimental demonstration is the most complex carbon-based electronic system yet realized. It is a considerable advance because CNTs are prominent among a variety of emerging technologies that are being considered for the next generation of highly energy-efficient electronic systems.

View details for DOI 10.1038/nature12502

View details for PubMedID 24067711
Carbon nanotube computer. Nature Shulaker, M. M., Hills, G., Patil, N., Wei, H., Chen, H., Wong, H. P., Mitra, S. 2013; 501 (7468): 526-530

Abstract

The miniaturization of electronic devices has been the principal driving force behind the semiconductor industry, and has brought about major improvements in computational power and energy efficiency. Although advances with silicon-based electronics continue to be made, alternative technologies are being explored. Digital circuits based on transistors fabricated from carbon nanotubes (CNTs) have the potential to outperform silicon by improving the energy-delay product, a metric of energy efficiency, by more than an order of magnitude. Hence, CNTs are an exciting complement to existing semiconductor technologies. Owing to substantial fundamental imperfections inherent in CNTs, however, only very basic circuit blocks have been demonstrated. Here we show how these imperfections can be overcome, and demonstrate the first computer built entirely using CNT-based transistors. The CNT computer runs an operating system that is capable of multitasking: as a demonstration, we perform counting and integer-sorting simultaneously. In addition, we implement 20 different instructions from the commercial MIPS instruction set to demonstrate the generality of our CNT computer. This experimental demonstration is the most complex carbon-based electronic system yet realized. It is a considerable advance because CNTs are prominent among a variety of emerging technologies that are being considered for the next generation of highly energy-efficient electronic systems.

View details for DOI 10.1038/nature12502

View details for PubMedID 24067711
Laterally Actuated Platinum-Coated Polysilicon NEM Relays JOURNAL OF MICROELECTROMECHANICAL SYSTEMS Parsa, R., Lee, W. S., Shavezipur, M., Provine, J., Maboudian, R., Mitra, S., Wong, H. P., Howe, R. T. 2013; 22 (3): 768-778

View details for DOI 10.1109/JMEMS.2013.2244779

View details for Web of Science ID 000319827700029
Combinational Logic Design Using Six-Terminal NEM Relays IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS Lee, D., Lee, W. S., Chen, C., Fallah, F., Provine, J., Chong, S., Watkins, J., Howe, R. T., Wong, H. P., Mitra, S. 2013; 32 (5): 653-666

View details for DOI 10.1109/TCAD.2012.2232707

View details for Web of Science ID 000318163800001
Underdesigned and Opportunistic Computing in Presence of Hardware Variability IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS Gupta, P., Agarwal, Y., Dolecek, L., Dutt, N., Gupta, R. K., Kumar, R., Mitra, S., Nicolau, A., Rosing, T. S., Srivastava, M. B., Swanson, S., Sylvester, D. 2013; 32 (1): 8-23

View details for DOI 10.1109/TCAD.2012.2223467

View details for Web of Science ID 000314676500002
Carbon Nanotube Computer Nature (Cover Feature) Shulaker, M., Hills, G., Patil, N., Wei, H., Chen, H., Gielen, G., Mitra, S. 2013; 501 (7468)
Rapid Exploration of Processing and Design Guidelines to Overcome Carbon Nanotube Variations Hills, G., Shulaker, M., Zhang, J., Wong, H., S.P., Mitra, S. 2013
Self-Repair of Uncore Components in Robust System-on-Chips: An OpenSPARC T2 Case Study Li, Y., Cheng, E., Makar, S., Mitra, S. 2013
Detection of Early-Life Failures in High-K Metal-Gate Transistors and Ultra Low-K Inter-Metal Dielectrics Kim, Y., M., Seomun, J., Kim, H., O., Do, K., T., Choi, J., Y., Kim, K., S., Mitra, S. 2013
Sascha: The Stanford Carbon Nanotube Controlled Handshaking Robot Shulaker, M., Van Rethy, J., Hills, G., Chen, H., Gielen, G., Wong, H., S.P., Mitra, S. 2013
Early-Life Failure Detection using SAT-Based ATPG Sauer, M., Kim, Y., M., Seomun, J., Kim, H., O., Do, K., T., Choi, J., Y., Mitra, S. 2013
Self-Repair of Uncore Components in Robust System-on-Chips: An OpenSPARC T2 Case Study Li, Y., Cheng, E., Makar, S., Mitra, S., IEEE IEEE. 2013

View details for Web of Science ID 000341376000032
Carbon Nanotube Circuits: Opportunities and Challenges Wei, H., Shulaker, M., Hills, G., Chen, H., Lee, C., Liyanage, L., Zhang, J., Wong, H., Mitra, S., Preas, K. ASSOC COMPUTING MACHINERY. 2013: 619–24

View details for Web of Science ID 000415129400121
Quantitative Evaluation of Soft Error Injection Techniques for Robust System Design Cho, H., Mirkhani, S., Cher, C., Abraham, J. A., Mitra, S., IEEE IEEE COMPUTER SOC. 2013

View details for Web of Science ID 000325822100100
Early-Life-Failure Detection using SAT-based ATPG Sauer, M., Kim, Y., Seomun, J., Kim, H., Do, K., Choi, J., Kim, K., Mitra, S., Becker, B., IEEE IEEE. 2013

View details for Web of Science ID 000341376000050
Experimental Demonstration of a Fully Digital Capacitive Sensor Interface Built Entirely Using Carbon-Nanotube FETs Shulaker, M., Van Rethy, J., Hills, G., Chen, H., Gielen, G., Wong, H., Mitra, S., IEEE IEEE. 2013: 112–U897

View details for Web of Science ID 000366612300042
Self-Repair of Uncore Components in Robust System-on-Chips: An OpenSPARC T2 Case Study IEEE International Test Conference (ITC) Li, Y., Cheng, E., Makar, S., Mitra, S. IEEE. 2013

View details for Web of Science ID 000341376000032
Rapid Exploration of Processing and Design Guidelines to Overcome Carbon Nanotube Variations 50th ACM/EDAC/IEEE Design Automation Conference (DAC) Hills, G., Zhang, J., Mackin, C., Shulaker, M., Wei, H., Wong, H. P., Mitra, S. IEEE COMPUTER SOC. 2013

View details for Web of Science ID 000325822100104
Sacha: the Stanford Carbon Nanotube Controlled Handshaking Robot 50th ACM/EDAC/IEEE Design Automation Conference (DAC) Shulaker, M., Van Rethy, J., Hills, G., Chen, H., Gielen, G., Wong, H. P., Mitra, S. IEEE COMPUTER SOC. 2013

View details for Web of Science ID 000325822100123
Early-Life-Failure Detection using SAT-based ATPG IEEE International Test Conference (ITC) Sauer, M., Kim, Y. M., Seomun, J., Kim, H., Do, K., Choi, J. Y., Kim, K. S., Mitra, S., Becker, B. IEEE. 2013

View details for Web of Science ID 000341376000050
Reliability of Graphene Interconnects and N-type Doping of Carbon Nanotube transistors IEEE International Reliability Physics Symposium (IRPS) Liyanage, L. S., Chen, X., Wei, H., Chen, H., Mitra, S., Wong, H. P. IEEE. 2013

View details for Web of Science ID 000325097500105
Quantitative Evaluation of Soft Error Injection Techniques for Robust System Design 50th ACM/EDAC/IEEE Design Automation Conference (DAC) Cho, H., Mirkhani, S., Cher, C., Abraham, J. A., Mitra, S. IEEE COMPUTER SOC. 2013

View details for Web of Science ID 000325822100100
LATERALLY ACTUATED NANOELECTROMECHANICAL RELAYS WITH COMPLIANT, LOW RESISTANCE CONTACT 26th IEEE International Conference on Micro Electro Mechanical Systems (MEMS) Shavezipur, M., Lee, W. S., Harrison, K. L., Provine, J., Mitra, S., Wong, H. P., Howe, R. T. IEEE. 2013: 520–523

View details for Web of Science ID 000320549200133
Monolithic Three-Dimensional Integration of Carbon Nanotube FET Complementary Logic Circuits IEEE International Electron Devices Meeting (IEDM) Wei, H., Shulaker, M., Wong, H. P., Mitra, S. IEEE. 2013

View details for Web of Science ID 000346509500126
Carbon Nanotube Circuits: Opportunities and Challenges Wei, H., Shulaker, M., Hills, G., Chen, H., Li, C., Liyanage, L., Mitra, S. 2013
Reliability of Graphene Interconnects and N-type Doping of Carbon Nanotube Transistors Liyanage, L., S., Chen, X., Wei, H., Chen, H., Y., Mitra, S., Wong, H., S.P. 2013
Underdesigned and Opportunistic Computing Keynote paper, IEEE Trans. CAD Gupta, P., Srivastava, M., Agarwal, Y., Swanson, S., Sylvester, D., Kumar, R., Mitra, S. 2013
Effective Post-Silicon Validation Mitra, S. 2013
Quantitative Evaluation of Soft Error Injection Techniques for Robust System Design Cho, H., Mirkhani, S., Cher, C., Y., Abraham, J., A., Mitra, S. 2013
Experimental Demonstration of a Fully Digital Capacitive Sensor Interface Built Entirely using Carbon Nanotube FETs Shulaker, M., Van Rethy, J., Hills, G., Chen, H., Gielen, G., Wong, H., S.P., Mitra, S. 2013
Overcoming Post-Silicon Validation Challenges through Quick Error Detection (QED) Lin, D., Hong, T., Li, Y., Fallah, F., Gardner, D., S., Hakim, N., Mitra, S. 2013
Monolithic Three-Dimensional Integration of Carbon Nanotube FET Complementary Logic Circuits Wei, H., Shulaker, M., Wong, H., S.P., Mitra, S. 2013
Flexible Control of Block Copolymer Directed Self-Assembly using Small, Topographical Templates: Potential Lithography Solution for Integrated Circuit Contact Hole Patterning ADVANCED MATERIALS Yi, H., Bao, X., Zhang, J., Bencher, C., Chang, L., Chen, X., Tiberio, R., Conway, J., Dai, H., Chen, Y., Mitra, S., Wong, H. P. 2012; 24 (23): 3107-3114

View details for DOI 10.1002/adma.201200265

View details for Web of Science ID 000305121100015

View details for PubMedID 22550028
Single-Tube Characterization Methodology for Experimental and Analytical Evaluation of Carbon Nanotube Synthesis JAPANESE JOURNAL OF APPLIED PHYSICS Chen, H., Lin, A., Liyanage, L. S., Beasley, C., Patil, N., Wei, H., Mitra, S., Wong, H. P. 2012; 51 (4)

View details for DOI 10.1143/JJAP.51.04DB02

View details for Web of Science ID 000303928600009
Robust Digital VLSI using Carbon Nanotubes IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS Zhang, J., Lin, A., Patil, N., Wei, H., Wei, L., Wong, H. P., Mitra, S. 2012; 31 (4): 453-471

View details for DOI 10.1109/TCAD.2012.2187527

View details for Web of Science ID 000302177200001
ERSA: Error Resilient System Architecture for Probabilistic Applications IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS Cho, H., Leem, L., Mitra, S. 2012; 31 (4): 546-558

View details for DOI 10.1109/TCAD.2011.2179038

View details for Web of Science ID 000302177200008
Probabilistic Analysis of Gallager B Faulty Decoder IEEE International Conference on Communications (ICC) Yazdi, S. M., Cho, H., Sun, Y., Mitra, S., Dolecek, L. IEEE. 2012

View details for Web of Science ID 000312855707057
Contact-Hole Patterning for Random Logic Circuits using Block Copolymer Directed Self-Assembly Yi, H., Bao, X., Zhang, J., Tiberio, R., Conway, J., Chang, L., Mitra, S. 2012
Cooling Three-Dimesnional Integrated Circuits using Power Delivery Networks Wei, H., Wu, T., Sekar, D., Cronquist, B., Pease, F., Mitra, S. 2012
The Device-to-System Spectrum -- A Tutorial on IC Design with Nanomaterials IEEE/ACM Design Automation and Test in Europe Chen, D., Mitra, S., Pop, E., Shanbhag, N. 2012
Nano-Electro-Mechanical Relays for FPGA Routing: Experimental Demonstration and a Design Technique Chen, C., Lee, W., Parsa, R., Chong, S., Provine, J., Watt, J., Howe, R. T., Wong, H., Mitra, S., IEEE IEEE. 2012: 1361–66

View details for Web of Science ID 000415126300278
Cooling Three-Dimensional Integrated Circuits using Power Delivery Networks IEEE International Electron Devices Meeting (IEDM) Wei, H., Wu, T. F., Sekar, D., Cronquist, B., Pease, R. F., Mitra, S. IEEE. 2012

View details for Web of Science ID 000320615600083
Nano-Electro-Mechanical Relays for FPGA Routing: Experimental Demonstration and a Design Technique Chen, C., Lee, W., S., Parsa, R., Chong, S., Provine, J., Watt, J., Mitra, S. 2012
Nano-Electro-Mechanical (NEM) Relays and their Application to FPGA Routing 17th Asia and South Pacific Design Automation Conference (ASP-DAC) Chen, C., Lee, S., Provine, J., Chong, S., Parsa, R., Lee, D., Howe, R. T., Wong, H. P., Mitra, S. IEEE. 2012: 639–639

View details for Web of Science ID 000309240000115
Integration of Nanoelectromechanical Relays With Silicon nMOS IEEE TRANSACTIONS ON ELECTRON DEVICES Chong, S., Lee, B., Mitra, S., Howe, R. T., Wong, H. P. 2012; 59 (1): 255-258

View details for DOI 10.1109/TED.2011.2172946

View details for Web of Science ID 000298756100038
Quick Detection of Difficult Bugs for Effective Post-Silicon Validation 49th ACM/EDAC/IEEE Design Automation Conference (DAC) Lin, D., Hong, T., Fallah, F., Hakim, N., Mitra, S. IEEE. 2012: 561–566

View details for Web of Science ID 000309256800081
Bug Localization Techniques for Effective Post-Silicon Validation 17th Asia and South Pacific Design Automation Conference (ASP-DAC) Mitra, S., Lin, D., Hakim, N., Gardner, D. IEEE. 2012: 291–291

View details for Web of Science ID 000309240000047
Wafer-Scale Fabrication and Characterization of Thin-Film Transistors with Polythiophene-Sorted Semiconducting Carbon Nanotube Networks ACS NANO Liyanage, L. S., Lee, H., Patil, N., Park, S., Mitra, S., Bao, Z., Wong, H. P. 2012; 6 (1): 451-458

Abstract

Semiconducting single-walled carbon nanotubes (SWCNTs) have great potential of becoming the channel material for future thin-film transistor technology. However, an effective sorting technique is needed to obtain high-quality semiconducting SWCNTs for optimal device performance. In our previous work, we reported a dispersion technique for semiconducting SWCNTs that relies on regioregular poly(3-dodecylthiophene) (rr-P3DDT) to form hybrid nanostructures. In this study, we demonstrate the scalability of those sorted CNT composite structures to form arrays of TFTs using standard lithographic techniques. The robustness of these CNT nanostructures was tested with Raman spectroscopy and atomic force microscope images. Important trends in device properties were extracted by means of electrical measurements for different CNT concentrations and channel lengths (L(c)). A statistical study provided an average mobility of 1 cm(2)/V·s and I(on)/I(off) as high as 10(6) for short channel lengths (L(c) = 1.5 μm) with 100% yield. This highlights the effectiveness of this sorting technique and its scalability for large-scale, flexible, and transparent display applications.

View details for DOI 10.1021/nn203771u

View details for PubMedID 22148677
Contact Hole Patterning for Random Logic Circuits using Block Copolymer Directed Self-Assembly Conference on Alternative Lithographic Technologies IV Yi, H., Bao, X., Zhang, J., Tiberio, R., Conway, J., Chang, L., Mitra, S., Wong, H. P. SPIE-INT SOC OPTICAL ENGINEERING. 2012

View details for DOI 10.1117/12.912804

View details for Web of Science ID 000304816600019
Characterization and Design of Logic Circuits in the Presence of Carbon Nanotube Density Variations IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS Zhang, J., Patil, N. P., Hazeghi, A., Wong, H. P., Mitra, S. 2011; 30 (8): 1103-1113

View details for DOI 10.1109/TCAD.2011.2121010

View details for Web of Science ID 000293709000002
The Case for RAMCloud COMMUNICATIONS OF THE ACM Ousterhout, J., Agrawal, P., Erickson, D., Kozyrakis, C., Leverich, J., Mazieres, D., Mitra, S., Narayanan, A., Ongaro, D., Parulkar, G., Rosenblum, M., Rumble, S. M., Stratmann, E., Stutsman, R. 2011; 54 (7): 121-130

View details for DOI 10.1145/1965724.1965751

View details for Web of Science ID 000293277800033
Scalable Carbon Nanotube Computational and Storage Circuits Immune to Metallic and Mispositioned Carbon Nanotubes IEEE TRANSACTIONS ON NANOTECHNOLOGY Patil, N., Lin, A., Zhang, J. (., Wei, H., Anderson, K., Wong, H. P., Mitra, S. 2011; 10 (4): 744-750

View details for DOI 10.1109/TNANO.2010.2076323

View details for Web of Science ID 000292966400013
Self-Tuning for Maximized Lifetime Energy-Efficiency in the Presence of Circuit Aging IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS Mintarno, E., Skaf, J., Zheng, R., Velamala, J. B., Cao, Y., Boyd, S., Dutton, R. W., Mitra, S. 2011; 30 (5): 760-773

View details for DOI 10.1109/TCAD.2010.2100531

View details for Web of Science ID 000289843900010
Linear Increases in Carbon Nanotube Density Through Multiple Transfer Technique NANO LETTERS Shulaker, M. M., Wei, H., Patil, N., Provine, J., Chen, H., Wong, H. P., Mitra, S. 2011; 11 (5): 1881-1886

Abstract

We present a technique to increase carbon nanotube (CNT) density beyond the as-grown CNT density. We perform multiple transfers, whereby we transfer CNTs from several growth wafers onto the same target surface, thereby linearly increasing CNT density on the target substrate. This process, called transfer of nanotubes through multiple sacrificial layers, is highly scalable, and we demonstrate linear CNT density scaling up to 5 transfers. We also demonstrate that this linear CNT density increase results in an ideal linear increase in drain-source currents of carbon nanotube field effect transistors (CNFETs). Experimental results demonstrate that CNT density can be improved from 2 to 8 CNTs/μm, accompanied by an increase in drain-source CNFET current from 4.3 to 17.4 μA/μm.

View details for DOI 10.1021/nl200063x

View details for Web of Science ID 000290373000005

View details for PubMedID 21469727
Hedgehog-responsive candidate cell of origin for diffuse intrinsic pontine glioma PROCEEDINGS OF THE NATIONAL ACADEMY OF SCIENCES OF THE UNITED STATES OF AMERICA Monje, M., Mitra, S. S., Freret, M. E., Raveh, T. B., Kim, J., Masek, M., Attema, J. L., Li, G., Haddix, T., Edwards, M. S., Fisher, P. G., Weissman, I. L., Rowitch, D. H., Vogel, H., Wong, A. J., Beachy, P. A. 2011; 108 (11): 4453-4458

Abstract

Diffuse intrinsic pontine gliomas (DIPGs) are highly aggressive tumors of childhood that are almost universally fatal. Our understanding of this devastating cancer is limited by a dearth of available tissue for study and by the lack of a faithful animal model. Intriguingly, DIPGs are restricted to the ventral pons and occur during a narrow window of middle childhood, suggesting dysregulation of a postnatal neurodevelopmental process. Here, we report the identification of a previously undescribed population of immunophenotypic neural precursor cells in the human and murine brainstem whose temporal and spatial distributions correlate closely with the incidence of DIPG and highlight a candidate cell of origin. Using early postmortem DIPG tumor tissue, we have established in vitro and xenograft models and find that the Hedgehog (Hh) signaling pathway implicated in many developmental and oncogenic processes is active in DIPG tumor cells. Modulation of Hh pathway activity has functional consequences for DIPG self-renewal capacity in neurosphere culture. The Hh pathway also appears to be active in normal ventral pontine precursor-like cells of the mouse, and unregulated pathway activity results in hypertrophy of the ventral pons. Together, these findings provide a foundation for understanding the cellular and molecular origins of DIPG, and suggest that the Hh pathway represents a potential therapeutic target in this devastating pediatric tumor.

View details for DOI 10.1073/pnas.1101657108

View details for PubMedID 21368213
Robust System Design to Overcome CMOS Reliability Challenges IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS Mitra, S., Brelsford, K., Kim, Y. M., Lee, H. K., Li, Y. 2011; 1 (1): 30-41

View details for DOI 10.1109/JETCAS.2011.2135630

View details for Web of Science ID 000208972300005
Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS Loi, I., Angiolini, F., Fujita, S., Mitra, S., Benini, L. 2011; 30 (1): 124-134

View details for DOI 10.1109/TCAD.2010.2065990

View details for Web of Science ID 000285517100011
Carbon Nanotube Imperfection-Immune Digital VLSI: Frequently Asked Questions Updated Wei, H., Zhang, J., Wei, L., Patil, N., Lin, A., Shulaker, M., Mitra, S. 2011
Robust System Design IPSJ Trans. System LSI Design Methodology Mitra, S., Cho, H., Hong, T., Kim, Y., Lee, H., Leem, L. 2011
Carbon-based Nanomaterial for Nanoelectronics 3rd International Symposium on Graphene, Ge/III-V, Nanowires and Emerging Materials for Post-CMOS Applications / Symposium on Tutorials in Nanotechnology with focus on Dielectrics in Nanosystems Chen, X., Lin, A., Wei, L., Patil, N., Wei, H., Chen, H., Mitra, S., Wong, H. P. ELECTROCHEMICAL SOC INC. 2011: 259–69

View details for DOI 10.1149/1.3569919

View details for Web of Science ID 000309539300024
Carbon Electronics – From Material Synthesis to Circuit Demonstration Chen, H., Patil, N., Lin, A., Wei, L., Beasley, C., Zhang, J., Mitra, S. 2011
Overcoming CMOS Reliability Challenges: From Devices to Circuits and Systems IEEE/ACM Design Automation and Test in Europe Cao, Y., Gielen, G., Mitra, S., Nassif, S. 2011
Robust System Design to Overcome CMOS Reliability Challenges IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Special Issue on the IEEE CAS Forum on Emerging and Selected Topics Mitra, S., Brelsford, K., Kim, Y., Lee, K., Li, Y. 2011
Carbon Nanotube Electronics – Materials, Devices, Circuits, Design, Modeling, and Performance Projection Wong, H., S.P., Mitra, S., Akinwande, D., Beasley, C., Chai, Y., Chen, H. 2011
Overcoming Carbon Nanotube Variations through Co-optimized Technology and Circuit Design IEEE International Electron Devices Meeting (IEDM) Zhang, J., Patil, N., Wong, H. P., Mitra, S. IEEE. 2011

View details for Web of Science ID 000300015300022
Air-Stable Technique for Fabricating n-Type Carbon Nanotube FETs IEEE International Electron Devices Meeting (IEDM) Wei, H., Chen, H., Liyanage, L., Wong, H. P., Mitra, S. IEEE. 2011

View details for Web of Science ID 000300015300127
Carbon Nanotube Imperfection-Immune Digital VLSI: Frequently Asked Questions Updated Invited Paper IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Wei, H., Zhang, J., Wei, L., Patil, N., Lin, A., Shulaker, M. M., Chen, H., Wong, H. P., Mitra, S. IEEE. 2011: 227–230

View details for Web of Science ID 000299009100034
Integration of Nanoelectromechanical (NEM) Relays with Silicon CMOS with Functional CMOS-NEM Circuit IEEE International Electron Devices Meeting (IEDM) Chong, S., Lee, B., Parizi, K. B., Provine, J., Mitra, S., Howe, R. T., Wong, H. P. IEEE. 2011

View details for Web of Science ID 000300015300177
Carbon Nanotube Electronics - Materials, Devices, Circuits, Design, Modeling, and Performance Projection IEEE International Electron Devices Meeting (IEDM) Wong, H. P., Mitra, S., Akinwande, D., Beasley, C., Chai, Y., Chen, H., Chen, X., Close, G., Deng, J., Hazeghi, A., Liang, J., Lin, A., Liyanage, L. S., Luo, J., Parker, J., Patil, N., Shulaker, M., Wei, H., Wei, L., Zhang, J. IEEE. 2011

View details for Web of Science ID 000300015300126
ACCNT: A Metallic-CNT-Tolerant Design Methodology for Carbon Nanotube VLSI: Analyses and Design Guidelines IEEE TRANSACTIONS ON ELECTRON DEVICES Lin, A., Zhang, J., Patil, N., Wei, H., Mitra, S., Wong, H. P. 2010; 57 (9): 2284-2295

View details for DOI 10.1109/TED.2010.2053207

View details for Web of Science ID 000283138200031
Post-Silicon Bug Localization for Processors Using IFRA COMMUNICATIONS OF THE ACM Park, S., Mitra, S. 2010; 53 (2): 106-113

View details for DOI 10.1145/1646353.1646377

View details for Web of Science ID 000274029100021
Efficient FPGAs using Nanoelectromechanical Relays 18th ACM International Symposium on Field-Programmable Gate Arrays Chen, C., Parsa, R., Patil, N., Chong, S., Akarvardar, K., Provine, J., Lewis, D., Watt, J., Howe, R. T., Wong, H. P., Mitra, S. ASSOC COMPUTING MACHINERY. 2010: 273–282

View details for Web of Science ID 000285022000035
Post-Silicon Validation: Opportunities, Challenges and Recent Advances Mitra, S., Seshia, S., Nicolici, N. 2010
Carbon Nanotube Correlation: Promising Opportunity for CNFET Circuit Yield Enhancement Zhang, J., Bobba, S., Patil, N., Lin, A., Wong, H., S.P., De Micheli, G., Mitra, S. 2010
Carbon Nanotube Circuits: Living with Imperfections and Variations Zhang, J., Patil, N., Lin, A., Wong, H., S.P., Mitra, S. 2010
Gate-Oxide Early-life Failure Identification using Delay Shifts Kim, Y., Chen, T., Kameda, Y., Mizuno, M., Mitra, S. 2010
Imperfection-Immune Carbon Nanotube VLSI Circuits Nanoelectronic Circuit Design Patil, N., Lin, A., Zhang, J., Wei, H., Wong, H., S.P., Mitra, S. Springer. 2010: 1
Characterization and Implementation of Fault-Tolerant Vertical Links for 3D Networks-on-Chip IEEE Trans. CAD Loi, I., Angiolini, F., Mitra, S., Fujita, S., Benini, L. 2010
Carbon Nanotube Circuits: Living with Imperfections and Variations Zhang, J., Patil, N., Lin, A., Wong, H., Mitra, S., IEEE IEEE. 2010: 1159–64

View details for Web of Science ID 000397468600224
BLoG: Post-Silicon Bug Localization in Processors using Bug Localization Graphs Park, S., Bracy, A., Wang, H., Mitra, S., IEEE IEEE. 2010: 368–73

View details for Web of Science ID 000409973500070
Carbon Nanotube Correlation: Promising Opportunity for CNFET Circuit Yield Enhancement Zhang, J., Bobba, S., Patil, N., Lin, A., Wong, H., De Micheli, G., Mitra, S., IEEE IEEE. 2010: 889–92

View details for Web of Science ID 000409973500172
ERSA: Error Resilient System Architecture for Probabilistic Applications Leem, L., Cho, H., Bau, J., Jacobson, Q. A., Mitra, S., IEEE IEEE. 2010: 1560-1565

View details for Web of Science ID 000397468600300
Low-Cost Gate-Oxide Early-Life Failure Detection in Robust Systems Kim, Y., Kameda, Y., Kim, H., Mizuno, M., Mitra, S., IEEE IEEE. 2010: 125-126

View details for DOI 10.1109/VLSIC.2010.5560326

View details for Web of Science ID 000287508300048
Optimized Self-Tuning to Maximize Lifetime Energy-Efficiency in the Presence of Circuit Aging Mintarno, E., Cao, Y., Boyd, S., Dutton, R., Mitra, S. 2010
BLoG: Post-Silicon Bug Localization in Processors using Bug Localization Graphs Park, S., Bracy, A., C., Wang, H., Mitra, S. 2010
ERSA: Error-Resilient System Architecture for Probabilistic Applications Leem, L., Cho, H., Bau, J., Jacobson, Q., Mitra, S. 2010
LEAP: Layout Design through Error-Aware Placement for Soft-Error Resilient Sequential Cell Design Lee, H., Lilja, K., Bounasser, M., Relangi, P., Linscott, I., Inan, U., Mitra, S. 2010
ACCNT - A Metallic-CNT-Tolerant Design Methodology for Carbon Nanotube VLSI: Analyses and Design Guidelines IEEE Trans. Electron Devices Lin, A., Patil, N., Zhang, J., Wei, H., Mitra, S., Wong, H., S.P. 2010
Concurrent Autonomous Self-Test for Uncore Components in SoCs Li, Y., Gardner, D., Mitra, S. 2010
Cross-Layer Resilience Challenges: Metrics and Optimization Mitra, S., Brelsford, K., Sanda, P. 2010
Post-Silicon Bug Localization for Processors Research Highlight, Communications of the ACM Park, S., Mitra, S. 2010
Scalable Carbon Nanotube Computational and Storage Circuits Immune to Metallic and Mis-positioned Carbon Nanotubes IEEE Trans. Nanotechnology Patil, N., Lin, A., Zhang, J., Wei, H., Anderson, K., Wong, H., S.P., Mitra, S. 2010
Low-Cost Gate-Oxide Early-Life Failure Detection in Robust Systems Symposium on VLSI Circuits Kim, Y. M., Kameda, Y., Kim, H., Mizuno, M., Mitra, S. IEEE. 2010: 125–126

View details for Web of Science ID 000287508300048
TITANIUM NITRIDE SIDEWALL STRINGER PROCESS FOR LATERAL NANOELECTROMECHANICAL RELAYS 23rd IEEE International Conference on Micro Electro Mechanical Systems (MEMS 2010) Lee, D., Lee, W. S., Provine, J., Lee, J., Yoon, J., Howe, R. T., Mitra, S., Wong, H. P. IEEE. 2010: 456–459

View details for Web of Science ID 000278416400112
Robust System Design 23rd International Conference on VLSI Design/9th International Conference on Embedded Systems Mitra, S. IEEE COMPUTER SOC. 2010: 434–439

View details for Web of Science ID 000283803200074
LEAP: Layout Design through Error-Aware Transistor Positioning for Soft-Error Resilient Sequential Cell Design 48TH Annual IEEE International Reliability Physics Symposium (IRPS) Lee, H. K., Lilja, K., Bounasser, M., Relangi, P., Linscott, I. R., Inan, U. S., Mitra, S. IEEE. 2010: 203–212

View details for Web of Science ID 000287515600033
Efficient Metallic Carbon Nanotube Removal Readily Scalable to Wafer-Level VLSI CNFET Circuits Symposium on VLSI Technology (VLSIT) Wei, H., Patil, N., Zhang, J., Lin, A., Chen, H., Wong, H. P., Mitra, S. IEEE. 2010: 237–238

View details for Web of Science ID 000287495500091
QED: Quick Error Detection Tests for Effective Post-Silicon Validation International Test Conference 2010 Hong, T., Li, Y., Park, S., Mui, D., Lin, D., Kaleq, Z. A., Hakim, N., Naeimi, H., Gardner, D. S., Mitra, S. IEEE. 2010

View details for Web of Science ID 000287978200017
Cross-Layer Error Resilience for Robust Systems IEEE and ACM International Conference on Computer-Aided Design Leem, L., Cho, H., Lee, H., Kim, Y. M., Li, Y., Mitra, S. IEEE. 2010: 177–180

View details for Web of Science ID 000287997600028
Solution Assembly of Organized Carbon Nanotube Networks for Thin-Film Transistors ACS NANO LeMieux, M. C., Sok, S., Roberts, M. E., Opatkiewicz, J. P., Liu, D., Barman, S. N., Patil, N., Mitra, S., Bao, Z. 2009; 3 (12): 4089-4097

Abstract

Ultrathin, transparent electronic materials consisting of solution-assembled nanomaterials that are directly integrated as thin-film transistors or conductive sheets may enable many new device structures. Applications ranging from disposable autonomous sensors to flexible, large-area displays and solar cells can dramatically expand the electronics market. With a practical, reliable method for controlling their electronic properties through solution assembly, submonolayer films of aligned single-walled carbon nanotubes (SWNTs) may provide a promising alternative for large-area, flexible electronics. Here, we report SWNT network TFTs (SWNTntTFTs) deposited from solution with controllable topology, on/off ratios averaging greater than 10(5), and an apparent mobility averaging 2 cm(2)/V.s, without any pre- or postprocessing steps. We employ a spin-assembly technique that results in chirality enrichment along with tunable alignment and density of the SWNTs by balancing the hydrodynamic force (spin rate) with the surface interaction force controlled by a chemically functionalized interface. This directed nanoscale assembly results in enriched semiconducting nanotubes yielding excellent TFT characteristics, which is corroborated with mu-Raman spectroscopy. Importantly, insight into the electronic properties of these SWNT networks as a function of topology is obtained.

View details for DOI 10.1021/nn900827v

View details for Web of Science ID 000272846000043

View details for PubMedID 19924882
ACCNT-A Metallic-CNT-Tolerant Design Methodology for Carbon-Nanotube VLSI: Concepts and Experimental Demonstration IEEE TRANSACTIONS ON ELECTRON DEVICES Lin, A., Patil, N., Wei, H., Mitra, S., Wong, H. P. 2009; 56 (12): 2969-2978

View details for DOI 10.1109/TED.2009.2033168

View details for Web of Science ID 000271951700012
Overcoming Early-Life Failure and Aging for Robust Systems IEEE DESIGN & TEST OF COMPUTERS Li, Y., Kim, Y. M., Mintarno, E., Mitra, S., Gardner, D. S. 2009; 26 (6): 28-39

View details for Web of Science ID 000271976500005
Overcoming Early-Life Failure and Aging for Robust Systems IEEE DESIGN & TEST OF COMPUTERS Li, Y., Kim, Y., Mintarno, E., Mitra, S., Gardner, D. S. 2009; 26 (6): 28-39

View details for DOI 10.1109/MDT.2009.152

View details for Web of Science ID 000271976500005
Post-Silicon Bug Localization in Processors Using Instruction Footprint Recording and Analysis (IFRA) IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS Park, S., Hong, T., Mitra, S. 2009; 28 (10): 1545-1558

View details for DOI 10.1109/TCAD.2009.2030595

View details for Web of Science ID 000270036600009
Probabilistic Analysis and Design of Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS Zhang, J., Patil, N. P., Mitra, S. 2009; 28 (9): 1307-1320

View details for DOI 10.1109/TCAD.2009.2023197

View details for Web of Science ID 000269155200003
Wafer-Scale Growth and Transfer of Aligned Single-Walled Carbon Nanotubes IEEE TRANSACTIONS ON NANOTECHNOLOGY Patil, N., Lin, A., Myers, E. R., Ryu, K., Badmaev, A., Zhou, C., Wong, H. P., Mitra, S. 2009; 8 (4): 498-504

View details for DOI 10.1109/TNANO.2009.2016562

View details for Web of Science ID 000268170900013
Design Methodology and Protection Strategy for ESD-CDM Robust Digital System Design in 90-nm and 130-nm Technologies IEEE TRANSACTIONS ON ELECTRON DEVICES Chen, T. W., Ito, C., Loh, W., Wang, W., Doddapaneni, K., Mitra, S., Dutton, R. W. 2009; 56 (2): 275-283

View details for DOI 10.1109/TED.2008.2010586

View details for Web of Science ID 000262816800017
Testing for Transistor Aging 27th IEEE VLSI Test Symposium Baba, A. H., Mitra, S. IEEE COMPUTER SOC. 2009: 215–220

View details for DOI 10.1109/VTS.2009.56

View details for Web of Science ID 000271941000036
Experimental Study of Gate-Oxide Early Life Failures Chen, T., W., Kim, Y., M., Kim, K., Kameda, Y., Mizuno, M., Mitra, S. 2009
Circuit Aging Prediction for Low-Power Operation Mitra, S., Zheng et al., R. 2009
ACCNT: A Metallic-CNT-Tolerant Design Methodology for Carbon Nanotube VLSI: Concepts and Experimental Demonstration IEEE Trans. Electron Devices Lin, A., Patil, N., Wei, H., Mitra, S., Wong, H., S.P. 2009
Overcoming Early-Life Failure and Aging Challenges for Robust System Design IEEE Design and Test of Computers, Special Issue on Design for Reliability and Robustness Li, Y., Kim, Y., M., Mintarno, E., Gardner, D., Mitra, S. 2009
Circuit Aging Prediction for Low-Power Operation IEEE Custom Integrated Circuits Conference Zheng, R., Velamala, J., Reddy, V., Balakrishnan, V., Mintarno, E., Mitra, S., Krishnan, S., Cao, Y. IEEE. 2009: 427–430

View details for Web of Science ID 000275926300092
Nanoelectromechanical (NEM) Relay Integrated with CMOS SRAM for Improved Stability and Low Leakage Mitra, S., Chong et al., S. 2009
Operating System Scheduling for Efficient On-line Self-Test in Robust Systems Li, Y., Mutlu, O., Mitra, S. 2009
Circuit Reliability: Modeling, Simulation and Resilient Design Solutions Cao, Y., Roy, K., Patyra, M., Mitra, S. 2009
From Nanodevices to Nanosystems: Promises and Challenges of IC Design with Nanomaterials Chen, D., Chen, Y., De, A., Mitra, S., Parkin, S. 2009
Imperfection-Immune VLSI Logic Circuits using Carbon Nanotube FETs Mitra, S., Zhang, J., Patil, N., Wei, H. 2009
IFRA: Instruction Footprint Recording and Analysis for Post-Silicon Bug Localization in Processors IEEE Trans. CAD Park, S., Hong, T., Mitra, S. 2009
Performance Benchmarking and Scalability of Carbon Nanotube Transistor Circuits IEEE Trans. Nanotechnology Patil, N., Deng, J., Wong, H., S.P., Mitra, S. 2009
Threshold Voltage and On-Off Ratio Tuning for Multiple-Tube Carbon Nanotube FETs IEEE TRANSACTIONS ON NANOTECHNOLOGY Lin, A., Patil, N., Ryu, K., Badmaev, A., De Arco, L. G., Zhou, C., Mitra, S., Wong, H. P. 2009; 8 (1): 4-9

View details for DOI 10.1109/TNANO.2008.2004706

View details for Web of Science ID 000262861500002
Imperfection-Immune VLSI Logic Circuits using Carbon Nanotube Field Effect Transistors Design, Automation and Test in Europe Conference and Exhibition Mitra, S., Zhang, J., Patil, N., Wei, H. IEEE. 2009: 436–441

View details for Web of Science ID 000273246700078
Carbon Nanotube Circuits in the Presence of Carbon Nanotube Density Variations 46th ACM/IEEE Design Automation Conference (DAC 2009) Zhang, J., Patil, N., Hazeghi, A., Mitra, S. IEEE. 2009: 71–76

View details for Web of Science ID 000279394200016
VMR: VLSI-Compatible Metallic Carbon Nanotube Removal for Imperfection-Immune Cascaded Multi-Stage Digital Logic Circuits using Carbon Nanotube FETs IEEE International Electron Devices Meeting (IEDM 2009) Patil, N., Lin, A., Zhang, J., Wei, H., Anderson, K., Wong, H. P., Mitra, S. IEEE. 2009: 535–538

View details for Web of Science ID 000279343900139
Digital VLSI Logic Technology using Carbon Nanotube FETs: Frequently Asked Questions 46th ACM/IEEE Design Automation Conference (DAC 2009) Patil, N., Lin, A., Zhang, J., Wong, H. P., Mitra, S. IEEE. 2009: 304–309

View details for Web of Science ID 000279394200064
IFRA: Post-Silicon Bug Localization in Processors IEEE International High Level Design Validation and Test Workshop Park, S., Mitra, S. IEEE. 2009: 154–159

View details for Web of Science ID 000278575200023
EXPERIMENTAL STUDY OF GATE OXIDE EARLY-LIFE FAILURES 47th Annual IEEE International Reliability Physics Symposium Chen, T. W., Kim, Y. M., Kim, K., Kameda, Y., Mizuno, M., Mitra, S. IEEE. 2009: 650–658

View details for Web of Science ID 000272068100104
Test Chip Experiments at Stanford CRC International Test Conference 2009 Al-Yamani, A., Chang, J., Franco, P., Li, J., Ma, S., Mitra, S., Park, I., Tseng, C., Volkerink, E. IEEE. 2009: 593–593

View details for Web of Science ID 000279591000069
Circuit-Level Performance Benchmarking and Scalability Analysis of Carbon Nanotube Transistor Circuits IEEE International Solid-State Circuits Conference (ISSCC) Patil, N., Deng, J., Mitra, S., Wong, H. P. IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. 2009: 37–45

View details for DOI 10.1109/TNANO.2008.2006903

View details for Web of Science ID 000262861500007
CMOS-Analogous Wafer-Scale Nanotube-on-Insulator Approach for Submicrometer Devices and Integrated Circuits Using Aligned Nanotubes NANO LETTERS Ryu, K., Badmaev, A., Wang, C., Lin, A., Patil, N., Gomez, L., Kumar, A., Mitra, S., Wong, H. P., Zhou, C. 2009; 9 (1): 189-197

Abstract

Massive aligned carbon nanotubes hold great potential but also face significant integration/assembly challenges for future beyond-silicon nanoelectronics. We report a wafer-scale processing of aligned nanotube devices and integrated circuits, including progress on essential technological components such as wafer-scale synthesis of aligned nanotubes, wafer-scale transfer of nanotubes to silicon wafers, metallic nanotube removal and chemical doping, and defect-tolerant integrated nanotube circuits. We have achieved synthesis of massive aligned nanotubes on complete 4 in. quartz and sapphire substrates, which were then transferred to 4 in. Si/SiO(2) wafers. CMOS analogous fabrication was performed to yield transistors and circuits with features down to 0.5 mum, with high current density approximately 20 muA/mum and good on/off ratios. In addition, chemical doping has been used to build fully integrated complementary inverter with a gain approximately 5, and a defect-tolerant design has been employed for NAND and NOR gates. This full-wafer approach could serve as a critical foundation for future integrated nanotube circuits.

View details for DOI 10.1021/nl802756u

View details for Web of Science ID 000262519100035

View details for PubMedID 19086836
A Metallic-CNT-Tolerant Carbon Nanotube Technology Using Asymmetrically-Correlated CNTs (ACCNT) Symposium on VLSI Technology Lin, A., Patil, N., Wei, H., Mitra, S., Wong, H. P. JAPAN SOCIETY APPLIED PHYSICS. 2009: 182–183

View details for Web of Science ID 000275651200071
Monolithic Three-Dimensional Integrated Circuits using Carbon Nanotube FETs and Interconnects IEEE International Electron Devices Meeting (IEDM 2009) Wei, H., Patil, N., Lin, A., Wong, H. P., Mitra, S. IEEE. 2009: 539–542

View details for Web of Science ID 000279343900140
Solution Assembly of Transistor Arrays Based on Sorted Nanotube Networks for Large-scale Flexible Electronic Applications 47th Annual Symposium of the Society-for-Information-Display LeMieux, M. C., Roberts, M., Opatkiewicz, J., Bao, Z., Patil, N., Mitra, S. SOC INFORMATION DISPLAY. 2009: 877–879

View details for Web of Science ID 000272997600227
Design methods for misaligned and mispositioned carbon-nanotube immune circuits Symposium on VLSI Technology Patil, N., Deng, J., Lin, A., Wong, H. P., Mitra, S. IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. 2008: 1725–36

View details for DOI 10.1109/TCAD.2008.2003278

View details for Web of Science ID 000259789400003
Device study, chemical doping, and logic circuits based on transferred aligned single-walled carbon nanotubes APPLIED PHYSICS LETTERS Wang, C., Ryu, K., Badmaev, A., Patil, N., Lin, A., Mitra, S., Wong, H. P., Zhou, C. 2008; 93 (3)

View details for DOI 10.1063/1.2956677

View details for Web of Science ID 000257968700062
The search for alternative computational paradigms IEEE DESIGN & TEST OF COMPUTERS Shanbhag, N. R., Roychowdhury, J., Mitra, S., Jones, D., de Veciana, G., Orshansky, M., Rabaey, J. M., Marculescu, R. 2008; 25 (4): 334-343

View details for Web of Science ID 000257911000009
The search for alternative computational paradigms IEEE DESIGN & TEST OF COMPUTERS Shanbhag, N. R., Roychowdhury, J., Mitra, S., Jones, D., de Veciana, G., Orshansky, M., Rabaey, J. M., Marculescu, R. 2008; 25 (4): 334-343

View details for DOI 10.1109/MDT.2008.113

View details for Web of Science ID 000257911000009
A joint search for gravitational wave bursts with AURIGA and LIGO CLASSICAL AND QUANTUM GRAVITY Baggio, L., Bignotto, M., Bonaldi, M., Cerdonio, M., De Rosa, M., Falferi, P., Fattori, S., Fortini, P., Giusfredi, G., Inguscio, M., Liguori, N., Longo, S., Marin, F., Mezzena, R., Mion, A., Ortolan, A., Poggi, S., Prodi, G. A., Re, V., Salemi, F., Soranzo, G., Taffarello, L., Vedovato, G., Vinante, A., Vitale, S., Zendri, J. P., Abbott, B., Abbott, R., Adhikari, R., Agresti, J., Ajith, P., Allen, B., Amin, R., Anderson, S. B., Anderson, W. G., Arain, M., Araya, M., Armandula, H., Ashley, M., Aston, S., Aufmuth, P., Aulbert, C., Babak, S., Ballmer, S., Bantilan, H., Barish, B. C., Barker, C., Barker, D., Barr, B., Barriga, P., Barton, M. A., Bayer, K., Belczynski, K., Betzwieser, J., Beyersdorf, P. T., Bhawal, B., Bilenko, I. A., Billingsley, G., Biswas, R., Black, E., Blackburn, K., Blackburn, L., Blair, D., Bland, B., Bogenstahl, J., Bogue, L., Bork, R., Boschi, V., Bose, S., Brady, P. R., Braginsky, V. B., Brau, J. E., Brinkmann, M., Brooks, A., Brown, D. A., Bullington, A., Bunkowski, A., Buonanno, A., Burmeister, O., Busby, D., Butler, W. E., Byer, R. L., Cadonati, L., Cagnoli, G., Camp, J. B., Cannizzo, J., Cannon, K., Cantley, C. A., Cao, J., Cardenas, L., Carter, K., Casey, M. M., Castaldi, G., Cepeda, C., Chalkley, E., Charlton, P., Chatterji, S., Chelkowski, S., Chen, Y., Chiadini, F., Chin, D., Chin, E., Chow, J., Christensen, N., Clark, J., Cochrane, P., Cokelaer, T., Colacino, C. N., Coldwell, R., Conte, R., Cook, D., Corbitt, T., Coward, D., Coyne, D., Creighton, J. D., Creighton, T. D., Croce, R. P., Crooks, D. R., Cruise, A. M., Cumming, A., Dalrymple, J., D'Ambrosio, E., Danzmann, K., Davies, G., DeBbra, D., Degallaix, J., Degree, M., Demma, T., Dergachev, V., Desai, S., DeSalvo, R., Dhurandhar, S., Diaz, M., Dickson, J., Di Credico, A., Diederichs, G., Dietz, A., Doomes, E. E., Drever, R. W., Dumas, J., Dupuis, R. J., Dwyer, J. G., Ehrens, P., ESPINOZA, E., Etzel, T., Evans, M., Evans, T., Fairhurst, S., Fan, Y., Fazi, D., Fejer, M. M., Finn, L. S., Fiumara, V., Fotopoulos, N., Franzen, A., Franzen, K. Y., Freise, A., Frey, R., Fricke, T., Fritschel, P., Frolov, V. V., Fyffe, M., Galdi, V., Ganezer, K. S., Garofoli, J., Gholami, I., Giaime, J. A., Giampanis, S., Giardina, K. D., Goda, K., Goetz, E., Goggin, L. M., Gonzalez, G., Gossler, S., Grant, A., Gras, S., Gray, C., Gray, M., Greenhalgh, J., Gretarsson, A. M., Grosso, R., GROTE, H., Grunewald, S., Guenther, M., Gustafson, R., Hage, B., Hammer, D., Hanna, C., Hanson, J., Harms, J., Harry, G., Harstad, E., Hayler, T., Heefner, J., Heng, I. S., Heptonstall, A., Heurs, M., Hewitson, M., Hild, S., Hirose, E., Hoak, D., Hosken, D., Hough, J., Howell, E., Hoyland, D., Huttner, S. H., Ingram, D., Innerhofer, E., Ito, M., Itoh, Y., Ivanov, A., Jackrel, D., Johnson, B., Johnson, W. W., Jones, D. I., Jones, G., Jones, R., Ju, L., Kalmus, P., Kalogera, V., Kasprzyk, D., Katsavounidis, E., Kawabe, K., Kawamura, S., Kawazoe, F., Kells, W., Keppel, D. G., Khalili, F. Y., Kim, C., King, P., Kissel, J. S., Klimenko, S., Kokeyama, K., Kondrashov, V., Kopparapu, R. K., Kozak, D., Krishnan, B., Kwee, P., Lam, P. K., Landry, M., Lantz, B., Lazzarini, A., Lee, B., Lei, M., Leiner, J., Leonhardt, V., Leonor, I., Libbrecht, K., Lindquist, P., Lockerbie, N. A., Longo, M., Lormand, M., Lubinski, M., Lueck, H., Machenschalk, B., MacInnis, M., Mageswaran, M., Mailand, K., Malec, M., Mandic, V., Marano, S., Marka, S., Markowitz, J., Maros, E., Martin, I., Marx, J. N., Mason, K., Matone, L., Matta, V., Mavalvala, N., McCarthy, R., McClelland, D. E., McGuire, S. C., McHugh, M., McKenzie, K., McNabb, J. W., McWilliams, S., Meier, T., Melissinos, A., Mendell, G., Mercer, R. A., Meshkov, S., Messenger, C. J., Meyers, D., Mikhailov, E., Mitra, S., Mitrofanov, V. P., Mitselmakher, G., Mittleman, R., Miyakawa, O., Mohanty, S., Moreno, G., Mossavi, K., MowLowry, C., Moylan, A., Mudge, D., Mueller, G., Mukherjee, S., Mueller-Ebhardt, H., Munch, J., Murray, P., Myers, E., Myers, J., Nash, T., Newton, G., Nishizawa, A., Nocera, F., Numata, K., O'Reilly, B., O'Shaughnessy, R., Ottaway, D. J., Overmier, H., Owen, B. J., Pan, Y., Papa, M. A., Parameshwaraiah, V., Parameswariah, C., Patel, P., Pedraza, M., Penn, S., Pierro, V., Pinto, I. M., Pitkin, M., Pletsch, H., Plissi, M. V., Postiglione, F., Prix, R., Quetschke, V., Raab, F., Rabeling, D., Radkins, H., Rahkola, R., Rainer, N., Rakhmanov, M., Ramsunder, M., Rawlins, K., Ray-Majumder, S., Regimbau, T., Rehbein, H., Reid, S., Reitze, D. H., Ribichini, L., Riesen, R., Riles, K., Rivera, B., Robertson, N. A., Robinson, C., Robinson, E. L., Roddy, S., Rodriguez, A., Rogan, A. M., Rollins, J., Romano, J. D., Romie, J., Route, R., Rowan, S., Ruediger, A., Ruet, L., Russell, P., Ryan, K., Sakata, S., Samidi, M., de la Jordana, L. S., Sandberg, V., Sanders, G. H., Sannibale, V., Saraf, S., Sarin, P., Sathyaprakash, B. S., Sato, S., Saulson, P., Savage, R., Savov, P., Sazonov, A., Schediwy, S., Schilling, R., Schnabel, R., Schofield, R., Schutz, B. F., Schwinberg, P., Scott, S. M., Searle, A. C., Sears, B., Seifert, F., Sellers, D., Sengupta, A. S., Shawhan, P., Shoemaker, D. H., Sibley, A., Siemens, X., Sigg, D., Sinha, S., Sintes, A. M., Slagmolen, B. J., SLUTSKY, J., Smith, J. R., Smith, M. R., Somiya, K., Strain, K. A., Strom, D. M., Stuver, A., Summerscales, T. Z., Sun, K., Sung, M., Sutton, P. J., Takahashi, H., Tanner, D. B., Tarallo, M., Taylor, R., Taylor, R., Thacker, J., Thorne, K. A., Thorne, K. S., Thuering, A., Tinto, M., Tokmakov, K. V., Torres, C., Torrie, C., Traylor, G., Trias, M., Tyler, W., Ugolini, D., Ungarelli, C., Urbanek, K., Vahlbruch, H., Vallisneri, M., Van den Broeck, C., van Putten, M., Varvella, M., Vass, S., Vecchio, A., Veitch, J., Veitch, P., Villar, A., Vorvick, C., Vyachanin, S. P., Waldman, S. J., Wallace, L., Ward, H., Ward, R., Watts, K., Webber, D., Weidner, A., Weinert, M., Weinstein, A., Weiss, R., Wen, S., Wette, K., Whelan, J. T., Whitbeck, D. M., Whitcomb, S. E., Whiting, B. F., Wiley, S., Wilkinson, C., Willems, P. A., Williams, L., Willke, B., Wilmut, I., Winkler, W., Wipf, C. C., Wise, S., Wiseman, A. G., Woan, G., Woods, D., Wooley, R., Worden, J., Wu, W., Yakushin, I., Yamamoto, H., Yan, Z., Yoshida, S., Yunes, N., Zanolin, M., Zhang, J., Zhang, L., Zhao, C., Zotov, N., Zucker, M., zur Muehlen, H., Zweizig, J. 2008; 25 (9)

View details for DOI 10.1088/0264-9381/25/9/095004

View details for Web of Science ID 000255897000005
Historical perspective on scan compression IEEE DESIGN & TEST OF COMPUTERS Kapur, R., Mitra, S., Williams, T. W. 2008; 25 (2): 114-120

View details for Web of Science ID 000254642000003
Historical perspective on scan compression IEEE DESIGN & TEST OF COMPUTERS Kapur, R., Mitra, S., Williams, T. W. 2008; 25 (2): 114-120

View details for DOI 10.1109/MDT.2008.40

View details for Web of Science ID 000254642000003
Integrated wafer-scale growth and transfer of directional carbon nanotubes and misaligned-carbon-nanotube-immune logic structures Symposium on VLSI Technology Patil, N., Lin, A., Myers, E. R., Wong, H. P., Mitra, S. IEEE. 2008: 159–160

View details for Web of Science ID 000259442500078
Design Guidelines for Metallic-Carbon-Nanotube-Tolerant Circuits Zhang, J., Patil, N., Mitra, S. 2008
Imperfection-Immune Carbon Nanotube VLSI Logic Circuits Mitra, S., Patil, N., Zhang, J. 2008
Soft Errors: System Effects, Protection Techniques and Case Studies Design Automation and Test in Europe Mitra, S., Sanda, P. 2008
Historical Perspective of Scan Compression IEEE Design and Test of Computers Kapur, R., Mitra, S., Williams, T., W. 2008
Soft Errors: Technology Trends, System Effects and Protection Techniques Mitra, S., Sanda, P., Seifert, N. 2008
Design Methods for Misaligned and Mis-positioned Carbon-Nanotube-Immune Circuits IEEE Trans. Computer-Aided Design Patil, N., Deng, J., Lin, A., Wong, H., S.P., Mitra, S. 2008
Globally Optimized Robust Systems to Overcome Scaled CMOS Challenges Mitra, S. 2008
CASP: Concurrent Autonomous chip self-test using Stored test Patterns Li, Y., Makar, S., Mitra, S., IEEE IEEE. 2008: 764-+

View details for Web of Science ID 000257940700131
Circuit failure prediction for robust system design in scaled CMOS Mitra, S., IEEE, E. IEEE, ELECTRON DEVICES SOC & RELIABILITY GROUP. 2008: 524-+

View details for DOI 10.1109/RELPHY.2008.4558940

View details for Web of Science ID 000257615900087
Soft error resilient system design through error correction Mitra, S., Zhang, M., Seifert, N., Mak, T. M., Kim, K., DeMicheli, G., Mir, S., Reis, R. SPRINGER. 2008: 143-+

View details for Web of Science ID 000251566700009
Optimized Circuit Failure Prediction for Aging: Practicality and Promise Mitra, S., Agarwal et al., M. 2008
A Low-overhead Fault Tolerance Scheme for TSV-based 3D Network-on-Chip Links Mitra, S., Loi et al., I. 2008
Soft Errors: System Effects, Protection Techniques and Case Studies Mitra, S., Sanda, P. 2008
VAST: Virtualization Assisted Concurrent Autonomous Self-Test Inoue, H., Li, Y., Mitra, S. 2008
In Search of Alternative Computational Paradigms IEEE Design and Test of Computers Shanbhag, N., Mitra, S., de Veciana, G., Orshansky, M., Marculescu, R., Roychowdhury, J. 2008
Circuit failure prediction for robust system design in scaled CMOS 46th Annual IEEE International Reliability Physics Symposium Mitra, S. IEEE, ELECTRON DEVICES SOC & RELIABILITY GROUP. 2008: 524–531

View details for Web of Science ID 000257615900087
Soft error resilient system design through error correction 14th International Conference on Very Large Scale Integration of System on Chip Mitra, S., Zhang, M., Seifert, N., Mak, T. M., Kim, K. S. SPRINGER. 2008: 143–156

View details for Web of Science ID 000251566700009
Globally optimized robust systems to overcome scaled CMOS reliability challenges Design, Automation and Test in Europe Conference and Exhibition (DATE 08) Mitra, S. IEEE. 2008: 820–825

View details for Web of Science ID 000257940700141
CASP: Concurrent Autonomous chip self-test using Stored test Patterns Design, Automation and Test in Europe Conference and Exhibition (DATE 08) Li, Y., Makar, S., Mitra, S. IEEE. 2008: 764–769

View details for Web of Science ID 000257940700131
Integrated wafer-scale growth and transfer of directional carbon nanotubes and misaligned-carbon-nanotube-immune logic structures Symposium on VLSI Technology Patil, N., Lin, A., Myers, E. R., Wong, H. P., Mitra, S. IEEE. 2008: 205–206

View details for Web of Science ID 000259116200077
Design guidelines for metallic-carbon-nanotube-tolerant digital logic circuits Design, Automation and Test in Europe Conference and Exhibition (DATE 08) Zhang, J., Patil, N. P., Mitra, S. IEEE. 2008: 888–893

View details for Web of Science ID 000257940700153
Gate-oxide early life failure prediction 26th IEEE VLSI Test Symposium Chen, T. W., Kim, K., Kim, Y. M., Mitra, S. IEEE COMPUTER SOC. 2008: 111–118

View details for DOI 10.1109/VTS.2008.55

View details for Web of Science ID 000256250900016
IFRA: Instruction Footprint Recording and Analysis for post-silicon bug localization in processors 45th ACM/IEEE Design Automation Conference Park, S., Mitra, S. IEEE. 2008: 373–378

View details for Web of Science ID 000258930200077
Application-dependent delay testing of FPGAs IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS Tahoori, M. B., Mitra, S. 2007; 26 (3): 553-563

View details for DOI 10.1109/TCAD.2006.882503

View details for Web of Science ID 000244471200013
Macro-model for post-breakdown 90nm and 130nm transistors and its applications in predicting chip-level function failure after ESD-CDM events 45th Annual IEEE International Reliability Physics Symposium Chen, T. W., Ito, C., Loh, W., Wang, W., Mitra, S., Duttona, R. W. IEEE. 2007: 78–85

View details for Web of Science ID 000246989600013
Design of Imperfection-Immune Carbon Nanotube Field Effect Transistor Circuits Patil, N., Deng, J., Mitra, S., Wong, H., S.P. 2007
Verification Guided Soft Error Resilience Seshia, S., Li, W., Mitra, S. 2007
Soft Errors: Technology Trends, System Effects and Protection Techniques Mitra, S., Sanda, P., Lesea, A. 2007
Erratic bit errors in latches Relangi, P., Mitra, S., IEEE IEEE. 2007: 445-+

View details for DOI 10.1109/RELPHY.2007.369931

View details for Web of Science ID 000246989600072
Macro-model for post-breakdown 90nm and 130nm transistors and its applications in predicting chip-level function failure after ESD-CDM events Chen, T., Ito, C., Loh, W., Wang, W., Mitra, S., Duttona, R. W., IEEE IEEE. 2007: 78-+

View details for DOI 10.1109/RELPHY.2007.369872

View details for Web of Science ID 000246989600013
Circuit failure prediction to overcome scaled CMOS reliability challenges Mitra, S., Agarwal, M., IEEE IEEE. 2007: 1000-1002

View details for Web of Science ID 000255939900110
Built-in soft error resilience for robust system design Mitra, S., Zhang, M., Seifert, N., Mak, T. M., Kim, K., IEEE IEEE. 2007: 263-+

View details for Web of Science ID 000250332300064
Verification-guided soft error resilience Design, Automation and Test in Europe Conference and Exhibition (DATE 07) Seshia, S. A., Li, W., Mitra, S. IEEE. 2007: 1442–1447

View details for Web of Science ID 000252175700246
California Scan: A Scan Architecture to Utilize Don't Care Bits in Test Patterns Cho, K., Y., Mitra, S., McCluskey, E., J. 2007
Marco-model for Post-breakdown 90nm and 130nm Transistors and its Applications in Predicting Chip-level Function Failure after ESD-CDM Events Chen, T., W., Ito, C., Loh, W., Wang, W., Mitra, S., Dutton, R., W. 2007
Soft Errors: Technology Trends, System Effects and Protection Techniques Mitra, S., Sanda, P., Seifert, N. 2007
Carbon Nanotube Transistor Circuits: Circuit-level Performance Benchmarking and Design Options for Living with Imperfections Deng, J., Patil, N., Ryu, K., Badmaev, A., Zhou, C., Mitra, S. 2007
California scan architecture for high quality and low power testing IEEE International Test Conference Cho, K. Y., Mitra, S., McCluskey, E. J. IEEE. 2007: 687–696

View details for Web of Science ID 000255939900075
Automated design of misaligned-carbon-nanotube-immune circuits 44th ACM/IEEE Design Automation Conference Patil, N., Deng, J., Wong, H. P., Mitra, S. IEEE. 2007: 958–961

View details for Web of Science ID 000249725800191
Built-in soft error resilience for robust system design IEEE International Conference on Integrated Circuit Design and Technology Mitra, S., Zhang, M., Seifert, N., Mak, T. M., Kim, K. S. IEEE. 2007: 263–268

View details for Web of Science ID 000250332300064
Circuit failure prediction enables robust system design resilient to aging and wearout 13th IEEE International On-Line Testing Symposium Mitra, S. IEEE COMPUTER SOC. 2007: 123–123

View details for Web of Science ID 000248534400021
Erratic bit errors in latches 45th Annual IEEE International Reliability Physics Symposium Relangi, P., Mitra, S. IEEE. 2007: 445–451

View details for Web of Science ID 000246989600072
Circuit failure prediction and its application to transistor aging 25th IEEE VLSI Test Symposium Agarwal, M., Paul, B. C., Zhang, M., Mitra, S. IEEE COMPUTER SOC. 2007: 277–284

View details for Web of Science ID 000246798100036
Soft errors: Technology trends, system effects, and protection techniques 13th IEEE International On-Line Testing Symposium Mitra, S., Sanda, P., Seifert, N. IEEE COMPUTER SOC. 2007: 4–4

View details for Web of Science ID 000248534400001
Circuit failure prediction to overcome scaled CMOS reliability challenges IEEE International Test Conference Mitra, S., Agarwal, M. IEEE. 2007: 1000–1002

View details for Web of Science ID 000255939900110
Sequential element design with built-in soft error resilience IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS Zhang, M., Mitra, S., Mak, T. M., Seifert, N., Wang, N. J., Shi, Q., Kim, K. S., Shanbhag, N. R., Patel, S. J. 2006; 14 (12): 1368-1378

View details for DOI 10.1109/TVLSI.2006.887832

View details for Web of Science ID 000243554300007
XPAND: An efficient test stimulus compression technique IEEE TRANSACTIONS ON COMPUTERS Mitra, S., Kim, K. S. 2006; 55 (2): 163-173

View details for Web of Science ID 000234095200007
Test compression for FPGAs IEEE International Test Conference Tahoori, M. B., Mitra, S. IEEE. 2006: 540–548

View details for Web of Science ID 000245118400060
Soft Errors: Technology Trends, System Effects and Protection Techniques Mitra, S., Sanda, P., Seifert, N. 2006
Test compression for FPGAs Tahoori, M. B., Mitra, S., IEEE IEEE. 2006: 540-+

View details for Web of Science ID 000245118400060
Signature analyzer design for yield learning support Patil, N. P., Mitra, S., Lumetta, S. S., IEEE IEEE. 2006: 255-+

View details for Web of Science ID 000245118400029
Combinational logic soft error correction Mitra, S., Zhang, M., Waqas, S., Seifert, N., Gill, B., Kim, K., IEEE IEEE. 2006: 824-+

View details for Web of Science ID 000245118400092
How to safeguard your sensitive data Mungamuru, B., Garcia-Molina, H., Mitra, S., Kawada, S. IEEE COMPUTER SOC. 2006: 199-211

View details for Web of Science ID 000242572700018
Radiation-induced soft error rates of advanced CMOS bulk devices 44th Annual IEEE International Reliability Physics Symposium Seifert, N., Slankard, P., Kirsch, M., Narasimham, B., Zia, V., Brookreson, C., Vo, A., Mitra, S., Gill, B., Maiz, J. IEEE. 2006: 217–225

View details for Web of Science ID 000240855800035
Comparison of Test Metrics: Stuck-at, N-Detect and Gate-Exhaustive Guo, R., Mitra, S., Lee, J., Sivaraj, S., Ameen, M. 2006
XPAND: An Efficient Test Stimulus Compression Technique IEEE Trans. Computers, Special Issue on System-on-Chip Design and Test Mitra, S., Kim, K., S. 2006
Radiation Induced Soft Error Rates of Advanced CMOS Bulk Devices Seifert, N., Slankard, P., Kirsch, M., Narasimham, B., Zia, V., Brookreson, C., Mitra, S. 2006
Designing Circuits with Carbon Nanotubes: Open Questions and Some Directions Deng, J., Patil, N., P., Mitra, S., Wong, H., S.P. 2006
Signature analyzer design for yield learning support IEEE International Test Conference Patil, N. P., Mitra, S., Lumetta, S. S. IEEE. 2006: 255–264

View details for Web of Science ID 000245118400029
Combinational logic soft error correction IEEE International Test Conference Mitra, S., Zhang, M., Waqas, S., Seifert, N., Gill, B., Kim, K. S. IEEE. 2006: 824–832

View details for Web of Science ID 000245118400092
Soft error resilient system design through error correction International Conference on Very Large Scale Integration and System-on-Chip Mitra, S., Zhang, M., Seifert, N., Mak, T. M., Kim, K. S. IFIP-INT FEDERATION INFORMATION PROCESSING. 2006: 332–337

View details for Web of Science ID 000243523900058
How to safeguard your sensitive data 25th IEEE Symposium on Reliable Distributed Systems Mungamuru, B., Garcia-Molina, H., Mitra, S. IEEE COMPUTER SOC. 2006: 199–211

View details for Web of Science ID 000242572700018
Application-independent testing of FPGA interconnects IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS Tahoori, M. B., Mitra, S. 2005; 24 (11): 1774-1783

View details for DOI 10.1109/TCAD.2005.852452

View details for Web of Science ID 000232971600010
X-tolerant test response compaction 10th IEEE European Test Symposium (ETS 2005) Mitra, S., Mitzenmacher, M., Lumetta, S. S., Patil, N. IEEE COMPUTER SOC. 2005: 566–74

View details for Web of Science ID 000233030500011
Carbon nanotube synthesis, characteristics, and microbattery applications 3rd Conference on Thin Films and Nanomaterials for Energy Conversion and Storage Zhang, Z. J., Dewan, C., Kothari, S., Mitra, S., Teeters, D. ELSEVIER SCIENCE SA. 2005: 363–68

View details for DOI 10.1016/j.mseb.2004.05.049

View details for Web of Science ID 000227056500020
Optimized reseeding by seed ordering and encoding IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS Al-Yamani, A. A., Mitra, S., McCluskey, E. J. 2005; 24 (2): 264-270

View details for DOI 10.1109/TCAD.2004.840550

View details for Web of Science ID 000226478700010
Robust system design with built-in soft-error resilience COMPUTER Mitra, S., Seifert, N., Zhang, M., Shi, Q., Kim, K. S. 2005; 38 (2): 43-?

View details for Web of Science ID 000227169900013
Response compaction with any number of unknowns using a new LFSR architecture 42nd Design Automation Conference Volkerink, E. H., Mitra, S. IEEE COMPUTER SOC. 2005: 117–122

View details for Web of Science ID 000230430300024
Test Response Compression with Any Number of Unknowns Volkerink, E., Mitra, S. 2005
Robust Platform Design in Sub-65nm Technologies Leavins, D., J., Kim, K., S., Mitra, S., Rodriguez, E. 2005
Fault Diagnosis with X-Compact Stanojevic, Z., Guo, R., Mitra, S., Venkataraman, S. 2005
Logic Soft Errors in Sub-65nm Technologies: Design and CAD Challenges Mitra, S., Karnik, T., Seifert, N., Zhang, M. 2005
Recent Advances in Hardware-Level Reliability Support for Transient Errors IEEE MICRO, Special Issue on the Reliability-Aware Microarchitectures Iyer, R., K., Nakka, N., Kalbarczyk, Z., Mitra, S. 2005
Application Independent Testing of FPGA Interconnects IEEE Trans. CAD Tahoori, M., Mitra, S. 2005
Robust System Design with Built-In Soft Error Resilience IEEE Computer Mitra, S., Seifert, N., Zhang, M., Shi, Q., Kim, K., S. 2005; 38 (2): 43-52
Testing Nanometer Integrated Circuits: Myths, Reality and the Road Ahead Mitra, S., Blanton, S. 2005
Robust platform design in advanced VLSI technologies IEEE Custom Integrated Circuits Conference Leavins, D. J., Kim, K. S., Mitra, S., Rodriguez, E. J. IEEE. 2005: 23–30

View details for Web of Science ID 000234406600004
Logic Soft Errors: A Major Barrier to Robust Platform Design Mitra, S., Zhang, M., Mak, T., M., Seifert, N., Zia, V., Kim, K., S. 2005
DFT Assisted Built-In Soft Error Resilience Mak, T., M., Mitra, S., Zhang, M. 2005
Built-In Soft Error Resilience Techniques Mitra, S. 2005
Built-In Soft Error Resilience Structures Mitra, S., Kim, K., S., Mak, T., M., Seifert, N., Shipley, P., Zhang, M. 2005
Gate Exhaustive Testing Cho, K., Y., Mitra, S., McCluskey, E., J. 2005
Enabling Yield Analysis with X-Compact Stanojevic, Z., Guo, R., Mitra, S., Venkataraman, S. 2005
Robust System Design from Unreliable Components Mitra, S., Spainhower, L., Narayanan, V., Xie, Y. 2005
Efficient design diversity estimation for combinational circuits IEEE TRANSACTIONS ON COMPUTERS Mitra, S., Saxena, N. R., McCluskey, E. J. 2004; 53 (11): 1483-1492

View details for Web of Science ID 000223872800011
Reconfigurable architecture for autonomous self-repair IEEE DESIGN & TEST OF COMPUTERS Mitra, S., Huang, W. J., Saxena, N. R., Yu, S. Y., McCluskey, E. J. 2004; 21 (3): 228-240

View details for Web of Science ID 000221577000011
Techniques and algorithms for fault grading of FPGA interconnect test configurations IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS Taboori, M. B., Mitra, S. 2004; 23 (2): 261-272

View details for DOI 10.1109/TCAD.2003.822112

View details for Web of Science ID 000188604300007
X-tolerant signature analysis 35th International Test Conference Mitra, S., Lumetta, S. S., Mitzenmacher, M. IEEE. 2004: 432–441

View details for Web of Science ID 000225277600046
ELF-MURPHY Data on Defects and Test Sets McCluskey, E., J., Mitra et al., S. 2004
Elimination of System Test from Production Test Flow Johnson, P., Wu, D., Mitra, S., Venkataraman, S. 2004
Defect and Fault Tolerance for Reconfigurable Molecular Computing Tahoori, M., Mitra, S. 2004
Delay Defect Screening using Process Monitor Structures Mitra, S., Volkerink, E., McCluskey, E., J., Eichenberger, S. 2004
ELF-Murphy data on defects and test sets 22nd IEEE VLSI Test Symsposium McCluskey, E. J., Al-Yamani, A., Li, J. C., Tseng, C. W., Volkerink, E., Ferhani, F. F., Li, E., Mitra, S. IEEE COMPUTER SOC. 2004: 16–22

View details for Web of Science ID 000221539900002
Delay defect screening using process monitor structures 22nd IEEE VLSI Test Symsposium Mitra, S., Volkerink, E., McCluskey, E. J., Eichenberger, S. IEEE COMPUTER SOC. 2004: 43–48

View details for Web of Science ID 000221539900006
Fault-Tolerance Encyclopedia on Computer Science and Engineering McCluskey, E., J., Mitra, S. CRC Press. 2004: 1
XPAND: Test Stimulus Compression for Intel Designs Mitra, S., Kim, K., S. 2004
X-Compact: An Efficient Response Compaction Technique IEEE Trans. Computer-Aided Design Mitra, S., Kim, K., S. 2004; 23 (`3): 421-432
Speed clustering of integrated circuits 35th International Test Conference Brand, K. A., Mitra, S., Volkerink, E., McCluskey, E. J. IEEE. 2004: 1128–1137

View details for Web of Science ID 000225277600124
Xpand + X-Compact: What did we Learn? Mitra, S., Kim, K., S. 2004
Defect and fault tolerance of reconfigurable molecular computing 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Tahoori, M. B., Mitra, S. IEEE COMPUTER SOC. 2004: 176–185

View details for Web of Science ID 000225131700017
Interconnect delay testing of designs on programmable logic devices 35th International Test Conference Tahoori, M. B., Mitra, S. IEEE. 2004: 635–644

View details for Web of Science ID 000225277600068
Test data compression IEEE DESIGN & TEST OF COMPUTERS McCluskey, E. J., Burek, D., Koenemann, B., Mitra, S., Patel, J., Rajski, J., Waicukauski, J. 2003; 20 (2): 76-87

View details for Web of Science ID 000181420400015
X-codes: Error control with unknowable inputs IEEE International Symposium on Information Theory Lumetta, S. S., Mitra, S. IEEE. 2003: 102–102

View details for Web of Science ID 000186112600102
XMAX: X-Tolerant Architecture for Maximal Test Compression Mitra, S., Kim, K., S. 2003
Design for Guaranteed Test Stimulus Compression Mitra, S., Kim, K., S., Parrish, G., C. 2003
Analysis of X-Compact for Intel ASIC Designs Mitra, S., Kallepalli, S., Kim, K., S. 2003
H-DFT: A Hybrid DFT Architecture for Low-Cost High Quality Structural Testing Wu, D., Lin, M., Mitra et al., S. 2003
Soft Errors in Digital Logic Mitra, S., Nguyen, H., Tam, N., Kim, K., S. 2003
Robust System Design Hotchips Mitra, S. 2003
Delay Defect Characteristics and Testing Strategies IEEE Design and Test of Computers, Special Issue on Speed Test and Speed Binning of Complex ICs Kim, K., S., Mitra, S., Ryan, P., G. 2003; 20 (5): 8-16
Automatic configuration generation for FPGA interconnect testing 21st IEEE VLSI Test Symposium Tahoori, M. B., Mitra, S. IEEE COMPUTER SOC. 2003: 134–139

View details for Web of Science ID 000183013100018
BIST reseeding with very few seeds 21st IEEE VLSI Test Symposium Al-Yamani, A. A., Mitra, S., McCluskey, E. J. IEEE COMPUTER SOC. 2003: 69–74

View details for Web of Science ID 000183013100009
Efficient seed utilization for reseeding based compression 21st IEEE VLSI Test Symposium Volkerink, E. H., Mitra, S. IEEE COMPUTER SOC. 2003: 232–237

View details for Web of Science ID 000183013100030
A design diversity metric and analysis of redundant systems IEEE TRANSACTIONS ON COMPUTERS Mitra, S., Saxena, N. R., McCluskey, E. J. 2002; 51 (5): 498-510

View details for Web of Science ID 000175244500005
(EDI)-I-4: Error detection by diverse data and duplicated instructions IEEE TRANSACTIONS ON COMPUTERS Oh, N., Mitra, S., McCluskey, E. J. 2002; 51 (2): 180-199

View details for Web of Science ID 000173677100007
Test vector compression using EDA-ATE synergies 20th IEEE VLSI Test Symposium (VTS 02) Khoche, A., Volkerink, E., Rivoir, J., Mitra, S. IEEE COMPUTER SOC. 2002: 97–102

View details for Web of Science ID 000176201400016
Dependable Reconfigurable Computing: Design Diversity and Self-Repair Mitra, S., McCluskey, E., J. 2002
X-Compact: An Efficient Response Compaction Technique for Test Cost Reduction Mitra, S., Kim, K., S. 2002
Design for testability and testing of IEEE 1149.1 tap controller 20th IEEE VLSI Test Symposium (VTS 02) Mitra, S., McCluskey, E. J., Makar, S. IEEE COMPUTER SOC. 2002: 247–252

View details for Web of Science ID 000176201400040
Efficient Response Compaction Mitra, S., Kim, K., S. 2002
Design for Testability and Testing of IEEE 1149.1 TAP Controller Mitra, S., McCluskey, E., J., Makar, S. 2002
Packet Based Test Vector Compression Techniques Volkerink, E., Mitra, S., Khoche, A. 2002
ED4I: Error Detection by Diverse Data and Duplicated Instructions IEEE Trans. on Computers, Special Issue on Fault-Tolerant Embedded Systems Oh, N., S., Mitra, S., McCluskey, E., J. 2002; 51 (2): 180-199
Testing digital circuits with constraints 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Al-Yamani, A. A., Mitra, S., McCluskey, E. J. IEEE COMPUTER SOC. 2002: 195–203

View details for Web of Science ID 000179481000021
Packet-based input test data compression techniques International Test Conference Volkerink, E. H., Khoche, A., Mitra, S. IEEE. 2002: 154–163

View details for Web of Science ID 000180001500025
Fault grading FPGA interconnect test configurations International Test Conference Tahoori, M. B., Mitra, S., Toutounchi, S., McCluskey, E. J. IEEE. 2002: 608–617

View details for Web of Science ID 000180001500077
Design diversity for concurrent error detection in sequential logic circuits 19th IEEE VLSI Test Symposium (VTS 2001) Mitra, S., McCluskey, E. J. IEEE COMPUTER SOC. 2001: 178–183

View details for Web of Science ID 000169368600026
Fast Run-Time Fault Location for Dependable FPGA Applications Huang, W, J., Mitra, S., McCluskey, E., J. 2001
An Evaluation of Pseudo-Random Testing for Detecting Real Defects Tseng, C., W., Mitra, S., McCluskey, E., J., Davidson, S. 2001
Techniques for estimation of design diversity for combinational logic circuits International Conference on Dependable Systems and Networks (DSN 2001) Mitra, S., Saxena, N. R., McCluskey, E. J. IEEE COMPUTER SOC. 2001: 25–34

View details for Web of Science ID 000171088900003
Design of redundant systems protected against common-mode failures 19th IEEE VLSI Test Symposium (VTS 2001) Mitra, S., McCluskey, E. J. IEEE COMPUTER SOC. 2001: 190–195

View details for Web of Science ID 000169368600028
Fast run-time fault location in dependable FPGA-based applications DFT/IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Huang, W. J., Mitra, S., McCluskey, E. J. IEEE COMPUTER SOC. 2001: 206–214

View details for Web of Science ID 000174007800026
Diversity techniques for concurrent error detection IEEE 2nd International Symposium on Quality Electronic Design (ISQED 2001) Mitra, S., McCluskey, E. J. IEEE COMPUTER SOC. 2001: 249–250

View details for Web of Science ID 000168102000038
Efficient multiplexer synthesis techniques IEEE DESIGN & TEST OF COMPUTERS Mitra, S., Awa, L. J., McCluskey, E. J. 2000; 17 (4): 90-97

View details for Web of Science ID 000166137600010
Common-mode failures in redundant VLSI systems: A survey IEEE TRANSACTIONS ON RELIABILITY Mitra, S., Saxena, N. R., McCluskey, E. J. 2000; 49 (3): 285-295

View details for Web of Science ID 000167886800005
Dependable computing and online testing in adaptive and configurable systems IEEE DESIGN & TEST OF COMPUTERS Saxena, N. R., Fernandez-Gomez, S., Huang, W. J., Mitra, S., Yu, S. Y., McCluskey, E. J. 2000; 17 (1): 29-41

View details for Web of Science ID 000085569300010
Fault Escapes in Duplex Systems Mitra, S., Saxena, N., McCluskey, E., J. 2000
Dependable Computing and On-Line Testing in Adaptive and Reconfigurable Systems IEEE Design and Test of Computers, Special Issue on Reconfigurable Computing Saxena, M., R., Gomez, S., Huang, W., Mitra, S., Yu, S., McCluskey, E., J. 2000; 17 (1): 29-41
DUDES: A Fault Abstraction and Collapsing Framework for Asynchronous Circuits Shirvani, P., Mitra, S., Ebergen, J., Rocken, M. 2000
WORD VOTER: A New Voter Design for Triple Modular Redundant Systems Mitra, S., McCluskey, E., J. 2000
Efficient Multiplexer Synthesis IEEE Design and Test of Computers Mitra, S., Avra, L., J., McCluskey, E., J. 2000; 17 (4): 90-97
Which concurrent error detection scheme to choose? International Test Conference Mitra, S., McCluskey, E. J. IEEE. 2000: 985–994

View details for Web of Science ID 000166038000115
Combinational logic synthesis for diversity in duplex systems International Test Conference Mitra, S., McCluskey, E. J. IEEE. 2000: 179–188

View details for Web of Science ID 000166038000023
An output encoding problem and a solution technique IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS Mitra, S., Avra, L. J., McCluskey, E. J. 1999; 18 (6): 761-768

View details for Web of Science ID 000080532200007
A Design Diversity Metric and Reliability Analysis For Redundant Systems Mitra, S., Saxena, N., R., McCluskey, E., J. 1999
Fault-Tolerance Projects at Stanford CRC Shirvani, P., Mitra et al., S. 1999
VLSI architecture of a cellular automata machine COMPUTERS & MATHEMATICS WITH APPLICATIONS Khan, A. R., Choudhury, P. P., Dihidar, K., Mitra, S., Sarkar, P. 1997; 33 (5): 79-94

View details for Web of Science ID A1997WT19300008
An output encoding problem and a solution technique 1997 IEEE/ACM International Conference on Computer-Aided Design (ICCAD 97) Mitra, S., Avra, L. J., McCluskey, E. J. I E E E, COMPUTER SOC PRESS. 1997: 304–307

View details for Web of Science ID A1997BK01U00045
Scan synthesis for one-hot signals International Test Conference 1997 (ITC) Mitra, S., Avra, L. J., McCluskey, E. J. IEEE. 1997: 714–722

View details for Web of Science ID 000071293600090

Subhasish Mitra

William E. Ayer Professor of Electrical Engineering and Professor of Computer Science

Web page: http://web.stanford.edu/people/subh

Bio

Academic Appointments

Administrative Appointments

Honors & Awards

Program Affiliations

Contact

Additional Info

Links

All Publications

Abstract

Abstract

Abstract

Abstract

Abstract

Abstract

Abstract

Abstract

Abstract

Abstract

Abstract

Abstract

Abstract

Abstract

Abstract

Abstract

Abstract

Abstract