Christoforos Kozyrakis
Professor of Electrical Engineering and of Computer Science
Web page: https://web.stanford.edu/~kozyraki/
Bio
Christos Kozyrakis is a Professor of Electrical Engineering and Computer Science at Stanford University. His primary research areas are computer architecture and computer systems. His current work focuses on cloud computing, systems for machine learning, and machine learning for systems. Christos leads the MAST research group. He is also the faculty director of the Stanford Platform Lab.
Christos holds a BS degree from the University of Crete and a PhD degree from the University of California at Berkeley. He is a fellow of the ACM and the IEEE. He has received the ACM SIGARCH Maurice Wilkes Award, the ISCA Influential Paper Award, the NSF Career Award, the Okawa Foundation Research Grant, and faculty awards by IBM, Microsoft, and Google.
Honors & Awards
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Maurice Wilkes Award, ACM SIGARCH (2015)
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Fellow, ACM (2016)
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Fellow, IEEE (2014)
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Faculty Award, IBM (2006)
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Career Award, National Science Foundation (2006)
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Research Grant, Okawa Foundation (2005)
Boards, Advisory Committees, Professional Organizations
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Willard R. and Inez Kerr Bell faculty scholar, Stanford University (2009 - 2011)
Professional Education
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PhD, University of California at Berkeley, Computer Science (2002)
2024-25 Courses
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Independent Studies (20)
- Advanced Reading and Research
CS 499 (Aut, Win, Spr, Sum) - Advanced Reading and Research
CS 499P (Aut, Win, Spr, Sum) - Curricular Practical Training
CS 390A (Aut, Win, Spr, Sum) - Curricular Practical Training
CS 390B (Aut, Win, Spr, Sum) - Curricular Practical Training
CS 390C (Aut, Win, Spr, Sum) - Independent Project
CS 399 (Aut, Win, Spr, Sum) - Independent Project
CS 399P (Aut, Win, Spr, Sum) - Independent Work
CS 199 (Aut, Win, Spr, Sum) - Independent Work
CS 199P (Aut, Win, Spr, Sum) - Master's Thesis and Thesis Research
EE 300 (Aut, Win, Spr, Sum) - Part-time Curricular Practical Training
CS 390D (Aut, Win, Spr, Sum) - Programming Service Project
CS 192 (Aut, Win, Spr, Sum) - Senior Project
CS 191 (Aut, Win, Spr, Sum) - Special Studies and Reports in Electrical Engineering
EE 191 (Aut, Win, Spr, Sum) - Special Studies and Reports in Electrical Engineering
EE 391 (Aut, Win, Spr, Sum) - Special Studies and Reports in Electrical Engineering (WIM)
EE 191W (Aut, Win, Spr, Sum) - Special Studies or Projects in Electrical Engineering
EE 190 (Aut, Win, Spr, Sum) - Special Studies or Projects in Electrical Engineering
EE 390 (Aut, Win, Spr, Sum) - Supervised Undergraduate Research
CS 195 (Aut, Win, Spr, Sum) - Writing Intensive Senior Research Project
CS 191W (Aut, Win, Spr)
- Advanced Reading and Research
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Prior Year Courses
2023-24 Courses
- Cloud Computing Technology
CS 349D (Spr) - Digital Systems Architecture
EE 180 (Win)
2022-23 Courses
- An Intro to Making: What is EE
ENGR 40M (Spr) - Cloud Computing Technology
CS 349D (Spr) - Colloquium on Computer Systems
EE 380 (Win, Spr) - Digital Systems Architecture
EE 180 (Win)
2021-22 Courses
- Cloud Computing Technology
CS 349D (Aut) - Colloquium on Computer Systems
EE 380 (Win, Spr) - Computer Systems from the Ground Up
CS 107E (Spr) - Digital Systems Architecture
EE 180 (Win)
- Cloud Computing Technology
Stanford Advisees
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Doctoral Dissertation Reader (AC)
Daniel Mendoza, Travis Skare, Tony Wang -
Doctoral Dissertation Advisor (AC)
Timothy Chong, Athinagoras Skiadopoulos, Mark Zhao -
Master's Program Advisor
Andrew Bartolo, Joseph Chen, Prerit Choudhary, Yash Dalmia, Shafin Khan, Suresh Nambi, Esau Veliz, Yu-Wei Wang, Weixin Yu, Caterina Zampa -
Doctoral (Program)
Timothy Chong, Kathleen Feng, Swapnil Gandhi, Athinagoras Skiadopoulos, Pete Warden, Caleb Winston, Zhiqiang Xie, Mark Zhao
All Publications
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R<SUP>3</SUP>: Record-Replay-Retroaction for Database-Backed Applications
PROCEEDINGS OF THE VLDB ENDOWMENT
2023; 16 (11): 3085-3097
View details for DOI 10.14778/3611479.3611510
View details for Web of Science ID 001059181900032
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<i>Tectonic-Shift</i>: A Composite Storage Fabric for Large-Scale ML Training
USENIX ASSOC. 2023: 433-449
View details for Web of Science ID 001066454400029
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Honeycomb: Secure and Efficient GPU Executions via Static Validation
USENIX ASSOC. 2023: 155-172
View details for Web of Science ID 001066453900010
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Optimizing Video Analytics with Declarative Model Relationships
PROCEEDINGS OF THE VLDB ENDOWMENT
2022; 16 (3): 447-460
View details for DOI 10.14778/3570690.3570695
View details for Web of Science ID 000992398800006
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RAIL: Predictable, Low Tail Latency for NVMe Flash
ACM TRANSACTIONS ON STORAGE
2022; 18 (1)
View details for DOI 10.1145/3465406
View details for Web of Science ID 000765084700002
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Towards mu s Tail Latency and Terabit Ethernet: Disaggregating the Host Network Stack
ASSOC COMPUTING MACHINERY. 2022: 767-779
View details for DOI 10.1145/3544216.3544230
View details for Web of Science ID 000859320200051
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Understanding Data Storage and Ingestion for Large-Scale Deep Recommendation Model Training
ASSOC COMPUTING MACHINERY. 2022: 1042-1057
View details for DOI 10.1145/3470496.3533044
View details for Web of Science ID 000852702500072
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SOL: Safe On-Node Learning in Cloud Platforms
ASSOC COMPUTING MACHINERY. 2022: 622-634
View details for DOI 10.1145/3503222.3507704
View details for Web of Science ID 000810486300044
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ShEF: Shielded Enclaves for Cloud FPGAs
ASSOC COMPUTING MACHINERY. 2022: 1070-1085
View details for DOI 10.1145/3503222.3507733
View details for Web of Science ID 000810486300075
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RecShard: Statistical Feature-Based Memory Optimization for Industry-Scale Neural Recommendation
ASSOC COMPUTING MACHINERY. 2022: 344-358
View details for DOI 10.1145/3503222.3507777
View details for Web of Science ID 000810486300025
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DBOS: A DBMS-oriented Operating System
ASSOC COMPUTING MACHINERY. 2021: 21-30
View details for DOI 10.14778/3485450.3485454
View details for Web of Science ID 000742948400003
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RAMBO: Resource Allocation for Microservices Using Bayesian Optimization
IEEE COMPUTER ARCHITECTURE LETTERS
2021; 20 (1): 46–49
View details for DOI 10.1109/LCA.2021.3066142
View details for Web of Science ID 000639645100002
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INFaaS: Automated Model-less Inference Serving
USENIX ASSOC. 2021: 397-411
View details for Web of Science ID 000696708600026
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LLAMA: A Heterogeneous & Serverless Framework for Auto-Tuning Video Analytics Pipelines
ASSOC COMPUTING MACHINERY. 2021: 1-17
View details for DOI 10.1145/3472883.3486972
View details for Web of Science ID 000768717900001
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Faa$T: A Transparent Auto-Scaling Cache for Serverless Applications
ASSOC COMPUTING MACHINERY. 2021: 122-137
View details for DOI 10.1145/3472883.3486974
View details for Web of Science ID 000768717900009
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SmartHarvest: Harvesting Idle CPUs Safely and Efficiently in the Cloud
ASSOC COMPUTING MACHINERY. 2021: 1-16
View details for DOI 10.1145/3447786.3456225
View details for Web of Science ID 000744467200001
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AsmDB: Understanding and Mitigating Front-End Stalls in Warehouse-Scale Computers
IEEE MICRO
2020; 40 (3): 56–63
View details for DOI 10.1109/MM.2020.2986212
View details for Web of Science ID 000537951100008
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The Hot Chips Renaissance
IEEE MICRO
2020; 40 (2): 6–7
View details for DOI 10.1109/MM.2020.2977409
View details for Web of Science ID 000522189700002
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Leveraging application classes to save power in highly-utilized data centers
SoCC '20: ACM Symposium on Cloud Computing
2020
View details for DOI 10.1145/3419111.3421274
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RackSched: A Microsecond-Scale Scheduler for Rack-Scale Computers
USENIX ASSOC. 2020: 1225-1240
View details for Web of Science ID 000668979500069
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Classifying Memory Access Patterns for Prefetching
ASSOC COMPUTING MACHINERY. 2020: 513–26
View details for DOI 10.1145/3373376.3378498
View details for Web of Science ID 000541369300034
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Interstellar: Using Halide's Scheduling Language to Analyze DNN Accelerators
ASSOC COMPUTING MACHINERY. 2020: 369–83
View details for DOI 10.1145/3373376.3378514
View details for Web of Science ID 000541369300024
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Mind the Gap: A Case for Informed Request Scheduling at the NIC
ASSOC COMPUTING MACHINERY. 2019: 60–68
View details for DOI 10.1145/3365609.3365856
View details for Web of Science ID 000546009600008
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AsmDB: Understanding and Mitigating Front-End Stalls in Warehouse-Scale Computers
ASSOC COMPUTING MACHINERY. 2019: 462–73
View details for DOI 10.1145/3307650.3322234
View details for Web of Science ID 000521059600036
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A Case for Managed and Model-less Inference Serving
ASSOC COMPUTING MACHINERY. 2019: 184–91
View details for DOI 10.1145/3317550.3321443
View details for Web of Science ID 000474421800026
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From Laptop to Lambda: Outsourcing Everyday Jobs to Thousands of Transient Functional Containers
USENIX ASSOC. 2019: 475–88
View details for Web of Science ID 000489756800033
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TANGRAM: Optimized Coarse-Grained Dataflow for Scalable NN Accelerators
ASPLOS '19: Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems
2019: 807–20
View details for DOI 10.1145/3297858.3304014
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Centralized Core-granular Scheduling for Serverless Functions
SoCC '19: ACM Symposium on Cloud Computing
2019
View details for DOI 10.1145/3357223.3362709
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Shinjuku: Preemptive Scheduling for mu second-scale Tail Latency
USENIX ASSOC. 2019: 345–59
View details for Web of Science ID 000474428400023
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QuMan: Profile-based Improvement of Cluster Utilization
ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION
2018; 15 (3)
View details for DOI 10.1145/3210560
View details for Web of Science ID 000450962200001
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Amdahl's Law for Tail Latency
COMMUNICATIONS OF THE ACM
2018; 61 (8): 65–72
View details for DOI 10.1145/3232559
View details for Web of Science ID 000439630200019
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Plasticine: A Reconfigurable Accelerator for Parallel Patterns
IEEE MICRO
2018; 38 (3): 20–31
View details for Web of Science ID 000432316500004
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Uncovering the Security Implications of Cloud Multi-Tenancy with Bolt
IEEE MICRO
2018; 38 (3): 86–97
View details for Web of Science ID 000432316500011
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GraphP: Reducing Communication for PIM-based Graph Processing with Efficient Data Partition
IEEE. 2018: 544–57
View details for DOI 10.1109/HPCA.2018.00053
View details for Web of Science ID 000440297700043
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Making Pull-Based Graph Processing Performant
ASSOC COMPUTING MACHINERY. 2018: 246–60
View details for DOI 10.1145/3178487.3178506
View details for Web of Science ID 000446161100019
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Memory Hierarchy for Web Search
IEEE. 2018: 643–56
View details for DOI 10.1109/HPCA.2018.00061
View details for Web of Science ID 000440297700051
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The IX Operating System: Combining Low Latency, High Throughput and Efficiency in a Protected Dataplane (vol 34, pg 11, 2017)
ACM TRANSACTIONS ON COMPUTER SYSTEMS
2017; 35 (3)
View details for DOI 10.1145/3154292
View details for Web of Science ID 000419303500004
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TETRIS: Scalable and Efficient Neural Network Acceleration with 3D Memory
ACM SIGPLAN NOTICES
2017; 52 (4): 751-764
View details for DOI 10.1145/3037697.3037702
View details for Web of Science ID 000401540000053
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Bolt: I Know What You Did Last Summer... In the Cloud
ACM SIGPLAN NOTICES
2017; 52 (4): 599-613
View details for DOI 10.1145/3037697.3037703
View details for Web of Science ID 000401540000043
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ReFlex: Remote Flash approximate to Local Flash
ACM SIGPLAN NOTICES
2017; 52 (4): 345-359
View details for DOI 10.1145/3037697.3037732
View details for Web of Science ID 000401540000026
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Special Session Paper 3D Nanosystems Enable Embedded Abundant-Data Computing
IEEE. 2017
View details for DOI 10.1145/3125502.3125531
View details for Web of Science ID 000425920100014
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Persona: A High-Performance Bioinformatics Framework
USENIX ASSOC. 2017: 153–65
View details for Web of Science ID 000428763500012
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The IX Operating System: Combining Low Latency, High Throughput, and Efficiency in a Protected Dataplane
ACM TRANSACTIONS ON COMPUTER SYSTEMS
2017; 34 (4)
View details for DOI 10.1145/2997641
View details for Web of Science ID 000393569100002
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Security Implications of Data Mining in Cloud Scheduling
IEEE COMPUTER ARCHITECTURE LETTERS
2016; 15 (2): 109-112
View details for DOI 10.1109/LCA.2015.2461215
View details for Web of Science ID 000392095400011
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Improving Resource Efficiency at Scale with Heracles
ACM TRANSACTIONS ON COMPUTER SYSTEMS
2016; 34 (2)
View details for DOI 10.1145/2882783
View details for Web of Science ID 000375568100003
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Generating Configurable Hardware from Parallel Patterns
ACM SIGPLAN NOTICES
2016; 51 (4): 651-665
View details for DOI 10.1145/2872362.2872415
View details for Web of Science ID 000379415100048
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HCloud: Resource-Efficient Provisioning in Shared Cloud Systems
ACM SIGPLAN NOTICES
2016; 51 (4): 473-488
View details for DOI 10.1145/2872362.2872365
View details for Web of Science ID 000379415100035
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Energy-Efficient Abundant-Data Computing: The N3XT 1,000x
COMPUTER
2015; 48 (12): 24-33
View details for Web of Science ID 000367689400005
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Convolution Engine: Balancing Efficiency and Flexibility in Specialized Computing
COMMUNICATIONS OF THE ACM
2015; 58 (4): 85-93
View details for DOI 10.1145/2735841
View details for Web of Science ID 000351734500024
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QUALITY-OF-SERVICE-AWARE SCHEDULING IN HETEROGENEOUS DATACENTERS WITH PARAGON
IEEE MICRO
2014; 34 (3): 17-30
View details for Web of Science ID 000337895100004
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Quasar: Resource-Efficient and QoS-Aware Cluster Management
ACM SIGPLAN NOTICES
2014; 49 (4): 127-143
View details for DOI 10.1145/2541940.2541941
View details for Web of Science ID 000360535000010
- Dynamic Management of TurboMode in Modern Multi-core Chips 2014
- Quasar: Resource-Efficient and QoS-Aware Cluster Management 2014
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QoS-Aware Scheduling in Heterogeneous Datacenters with Paragon
ACM TRANSACTIONS ON COMPUTER SYSTEMS
2013; 31 (4)
View details for DOI 10.1145/2556583
View details for Web of Science ID 000329130800004
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Measuring and analyzing the energy use of enterprise computing systems
SUSTAINABLE COMPUTING-INFORMATICS & SYSTEMS
2013; 3 (3): 218-229
View details for DOI 10.1016/j.suscom.2013.01.009
View details for Web of Science ID 000209576200010
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Paragon: QoS-Aware Scheduling for Heterogeneous Datacenters
ACM SIGPLAN NOTICES
2013; 48 (4): 77-88
View details for Web of Science ID 000321213100007
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Guest Editors' Introduction SELECTED RESEARCH FROM HOT CHIPS 24
IEEE MICRO
2013; 33 (2): 6-7
View details for Web of Science ID 000316977900002
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The Netflix Challenge: Datacenter Edition
IEEE COMPUTER ARCHITECTURE LETTERS
2013; 12 (1): 29-32
View details for DOI 10.1109/L-CA.2012.10
View details for Web of Science ID 000320993000009
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iBench: Quantifying Interference for Datacenter Applications
IEEE International Symposium on Workload Characterization (IISWC)
IEEE. 2013: 23–33
View details for Web of Science ID 000349629200003
- ZSim: Fast and Accurate Microarchitectural Simulation of Thousand-Core Systems 2013
- iBench: Quantifying Interference for Datacenter Workloads 2013
- Convolution Engine: Balancing Efficiency and Flexibility in Specialized Computing 2013
- Measuring and analyzing the energy use of enterprise computing systems Sustainable Computing: Informatics and Systems 2013
- Resource Efficienct Computing for Warehouse-scale Datacenters 2013
- QoS-Aware Admission Control in Heterogeneous Datacenters 2013
- Enhanced Concurrency Control with Transactional NACKs 2013
- Locality-Aware Task Management for Unstructured Parallelism: A Quantitative Limit Study 2013
- QoS-Aware Scheduling in Heterogeneous Datacenters with Paragon ACM Transactions on Computer Systems (TOCS) 2013; 31 (4)
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Decoupling Datacenter Storage Studies from Access to Large-Scale Applications
IEEE COMPUTER ARCHITECTURE LETTERS
2012; 11 (2): 53-56
View details for DOI 10.1109/L-CA.2011.37
View details for Web of Science ID 000312559500007
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SCALABLE AND EFFICIENT FINE-GRAINED CACHE PARTITIONING WITH VANTAGE
IEEE MICRO
2012; 32 (3): 26-37
View details for Web of Science ID 000304792200005
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Hardware Acceleration of Transactional Memory on Commodity Systems
ACM SIGPLAN NOTICES
2012; 47 (4): 27-38
View details for DOI 10.1145/2248487.1950372
View details for Web of Science ID 000307565500004
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Improving System Energy Efficiency with Memory Rank Subsetting
ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION
2012; 9 (1)
View details for DOI 10.1145/2133382.2133386
View details for Web of Science ID 000302249400004
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Green Enterprise Computing Data: Assumptions and Realities
3rd International Green Computing Conference (IGCC)
IEEE. 2012
View details for Web of Science ID 000309942300020
- Dune: Safe User-level Access to Privileged CPU Features 2012
- ECHO: Recreating Network Traffic Maps for Datacenters of Tens of Thousands of Servers 2012
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A Case of System-level Hardware/Software Co-design and Co-verification of a Commodity Multi-Processor System with Custom Hardware
10th ACM International Conference on Hardware/Software-Codesign and System Synthesis
ASSOC COMPUTING MACHINERY. 2012: 513–519
View details for Web of Science ID 000320320800059
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SCD: A Scalable Coherence Directory with Flexible Sharer Set Encoding
18th IEEE International Symposium on High-Performance Computer Architecture (HPCA)
IEEE. 2012: 129–140
View details for Web of Science ID 000308957200011
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Towards Energy-Proportional Datacenter Memory with Mobile DRAM
39th Annual International Symposium on Computer Architecture (ISCA)
IEEE. 2012: 37–48
View details for Web of Science ID 000309010000004
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Understanding Sources of Inefficiency in General-Purpose Chips
COMMUNICATIONS OF THE ACM
2011; 54 (10): 85-93
View details for DOI 10.1145/2001269.2001291
View details for Web of Science ID 000296022500021
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The Case for RAMCloud
COMMUNICATIONS OF THE ACM
2011; 54 (7): 121-130
View details for DOI 10.1145/1965724.1965751
View details for Web of Science ID 000293277800033
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Hardware Acceleration of Transactional Memory on Commodity Systems
ACM SIGPLAN NOTICES
2011; 46 (3): 27-38
View details for DOI 10.1145/1961296.1950372
View details for Web of Science ID 000290854400004
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Vantage: Scalable and Efficient Fine-Grain Cache Partitioning
38th Annual International Symposium on Computer Architecture
ASSOC COMPUTING MACHINERY. 2011: 57–68
View details for Web of Science ID 000292709800006
- Storage I/O Generation and Replay for Datacenter Applications 2011
- Time and Cost-Efficient Modeling and Generation of Large-Scale TPCC/TPCE/TPCH 2011
- Phoenix++: Modular MapReduce for Shared-Memory Systems 2011
- Dynamic Fine-Grain Scheduling of Pipeline Parallelism 2011
- Accurate Modeling and Generation of Storage I/O for Datacenter Workloads 2011
- Understanding Sources of Inefficiency in General-Purpose Chips Communications of the ACM (CACM) 2011; 54 (10)
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Decoupling Datacenter Studies from Access to Large-Scale Applications: A Modeling Approach for Storage Workloads
IEEE International Symposium on Workload Characterization (IISWC)
IEEE. 2011: 51–60
View details for Web of Science ID 000299350700005
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SERVER ENGINEERING INSIGHTS FOR LARGE-SCALE ONLINE SERVICES
IEEE MICRO
2010; 30 (4): 8-19
View details for Web of Science ID 000280949100003
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An Analysis of On-Chip Interconnection Networks for Large-Scale Chip Multiprocessors
ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION
2010; 7 (1)
View details for DOI 10.1145/1756065.1736069
View details for Web of Science ID 000277924800004
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Flexible Architectural Support for Fine-Grain Scheduling
ACM SIGPLAN NOTICES
2010; 45 (3): 311-322
View details for Web of Science ID 000275926700026
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Understanding Sources of Inefficiency in General-Purpose Chips
37th International Symposium on Computer Architecture
ASSOC COMPUTING MACHINERY. 2010: 37–47
View details for Web of Science ID 000287049300005
- FARM: A Prototyping Environment for Tightly-Coupled, Heterogeneous Architectures 2010
- Tainting is Not Pointless ACM SIGOPS Operating Systems Review 2010; 44 (2)
- Making Nested Parallel Transactions Practical using Lightweight Hardware Support 2010
- EigenBench: A Simple Exploration Tool for Orthogonal TM Characteristics 2010
- The ZCache: Decoupling Ways and Associativity 2010
- Implementing and Evaluating a Model Checker for Transactional Memory Systems 2010
- Evaluating Bufferless Flow Control for On-Chip Networks 2010
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Implementing and Evaluating Nested Parallel Transactions in Software Transactional Memory
22nd ACM Symposium on Parallelism in Algorithms and Architectures
ASSOC COMPUTING MACHINERY. 2010: 253–262
View details for Web of Science ID 000281485500036
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Power Management of Datacenter Workloads Using Per-Core Power Gating
IEEE COMPUTER ARCHITECTURE LETTERS
2009; 8 (2): 48-51
View details for DOI 10.1109/L-CA.2009.46
View details for Web of Science ID 000207924800005
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HOT CHIPS TURNS 20
IEEE MICRO
2009; 29 (2): 4-5
View details for Web of Science ID 000264804100002
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Feedback-Directed Barrier Optimization in a Strongly Isolated STM
ACM SIGPLAN NOTICES
2009; 44 (1): 213-225
View details for Web of Science ID 000272013800020
- On the Energy (In)Efficiency of Hadoop Clusters 2009
- On the Energy (In)Efficiency of Hadoop Clusters 2009
- The Stanford Pervasive Parallelism Lab 2009
- Energy Dumpster Diving 2009
- Energy Dumpster Diving 2009
- Nemesis: Preventing Authentication & Access Control Vulnerabilities in Web Applications 2009
- The case for RAMClouds: scalable high-performance storage entirely in DRAM ACM SIGOPS Operating Systems Review 2009; 43 (4)
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Future Scaling of Processor-Memory Interfaces
Conference on High Performance Computing Networking, Storage and Analysis
IEEE. 2009
View details for Web of Science ID 000320136800015
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Decoupling Dynamic Information Flow Tracking with a Dedicated Coprocessor
39th Annual IEEE/IFIP International Conference on Dependable Systems and Networks
IEEE. 2009: 105–114
View details for Web of Science ID 000275174400012
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Phoenix Rebirth: Scalable MapReduce on a Large-Scale Shared-Memory System
IEEE International Symposium on Workload Characterization
IEEE COMPUTER SOC. 2009: 198–207
View details for Web of Science ID 000274997900021
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Fast Memory Snapshot for Concurrent Programming without Synchronization
ACM SIGARCH International Conference on Supercomputing
ASSOC COMPUTING MACHINERY. 2009: 117–125
View details for Web of Science ID 000268247500012
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A Memory System Design Framework: Creating Smart Memories
36th Annual International Symposium on Computer Architecture
ASSOC COMPUTING MACHINERY. 2009: 406–417
View details for Web of Science ID 000268225000037
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Comparative Evaluation of Memory Models for Chip Multiprocessors
ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION
2008; 5 (3)
View details for DOI 10.1145/1455650.1455651
View details for Web of Science ID 000261844300001
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Transactional memory
COMMUNICATIONS OF THE ACM
2008; 51 (7): 80-88
View details for DOI 10.1145/1364782.1364800
View details for Web of Science ID 000257116300019
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Improving Software Concurrency with Hardware-assisted Memory Snapshot
20th ACM Symposium on Parallelism in Algorithms and Architectures
ASSOC COMPUTING MACHINERY. 2008: 363–363
View details for Web of Science ID 000266217200050
- Hardware Enforcement of Application Security Policies 2008
- A Comparison of High-Level Full-System Power Models 2008
- Real-World Buffer Overflow Protection for Userspace and Kernelspace 2008
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Thread-Safe Dynamic Binary Translation using Transactional Memory
14th International Symposium on High-Performance Computer Architecture
IEEE. 2008: 256–266
View details for Web of Science ID 000263593200024
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ASeD: Availability, Security, and Debugging Support using Transactional Memory
20th ACM Symposium on Parallelism in Algorithms and Architectures
ASSOC COMPUTING MACHINERY. 2008: 366–366
View details for Web of Science ID 000266217200053
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STAMP: Stanford Transactional Applications for Multi-Processing
IEEE International Symposium on Workload Characterization
IEEE. 2008: 31–42
View details for Web of Science ID 000263063500004
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Models and metrics to enable energy-efficiency optimizations
COMPUTER
2007; 40 (12): 39-?
View details for Web of Science ID 000251428300011
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RAMP: Research accelerator for multiple processors
Hot Chips 18 Conference
IEEE COMPUTER SOC. 2007: 46–57
View details for Web of Science ID 000247913200007
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Towards Soft Optimization Techniques for Parallel Cognitive Applications
19th Annual Symposium on Parallelism in Algorithms and Architectures
ASSOC COMPUTING MACHINERY. 2007: 59–60
View details for Web of Science ID 000266371200009
- The OpenTM Transactional Application Programming Interface 2007
- RAMP: Research Accelerator for Multiple Processors IEEE Micro 2007; 27 (2)
- A Low Power Front-end for Embedded Processors using a Block-aware Instruction Set 2007
- JouleSort: A Balanced Energy-Efficiency Benchmark 2007
- Raksha: A Flexible Architecture for Software Security 2007
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Raksha: A Flexible Information Flow Architecture for Software Security
34th Annual International Symposium on Computer Architecture
ASSOC COMPUTING MACHINERY. 2007: 482–493
View details for Web of Science ID 000265786200043
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Register pointer architecture for efficient embedded processors
Design, Automation and Test in Europe Conference and Exhibition (DATE 07)
IEEE. 2007: 600–605
View details for Web of Science ID 000252175700101
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Evaluating MapReduce for multi-core and multiprocessor systems
13th International Symposium on High-Performance Computer Architecture
IEEE COMPUTER SOC. 2007: 13–24
View details for Web of Science ID 000245463100002
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A Practical FPGA-based Framework for Novel CMP Research
15th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
ASSOC COMPUTING MACHINERY. 2007: 116–125
View details for Web of Science ID 000268330100013
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Transactional Collection Classes
ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming
ASSOC COMPUTING MACHINERY. 2007: 56–67
View details for Web of Science ID 000266870900006
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ATLAS: A chip-multiprocessor with Transactional Memory support
Design, Automation and Test in Europe Conference and Exhibition (DATE 07)
IEEE. 2007: 3–8
View details for Web of Science ID 000252175700001
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Transactional memory: The hardware-software interface
IEEE MICRO
2007; 27 (1): 67-76
View details for Web of Science ID 000246455000009
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Comparing Memory Systems for Chip Multiprocessors
34th Annual International Symposium on Computer Architecture
ASSOC COMPUTING MACHINERY. 2007: 358–368
View details for Web of Science ID 000265786200032
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An Effective Hybrid Transactional Memory System with Strong Isolation Guarantees
34th Annual International Symposium on Computer Architecture
ASSOC COMPUTING MACHINERY. 2007: 69–80
View details for Web of Science ID 000265786200007
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A scalable, non-blocking approach to transactional memory
13th International Symposium on High-Performance Computer Architecture
IEEE COMPUTER SOC. 2007: 97–108
View details for Web of Science ID 000245463100010
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Executing Java programs with transactional memory
OOPSLA Workshop on Synchronization and Concurrent in Object-Oriented Languages
ELSEVIER SCIENCE BV. 2006: 111–29
View details for DOI 10.1016/j.scico.2006.05.006
View details for Web of Science ID 000241921200002
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Tradeoffs in transactional memory virtualization
ACM SIGPLAN NOTICES
2006; 41 (11): 371-381
View details for Web of Science ID 000202972600035
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The ATOMO Sigma transactional programming language
ACM SIGPLAN NOTICES
2006; 41 (6): 1-13
View details for Web of Science ID 000202972100001
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Vector lane threading
35th International Conference on Parallel Processing
IEEE COMPUTER SOC. 2006: 55–62
View details for Web of Science ID 000241495500006
- Parallelizing SPECjbb2000 with Transactional Memory 2006
- Early Release: Friend or Foe 2006
- Deconstructing Hardware Architectures for Security 2006
- Unlocking Concurrency: Multicore Programming with Transactional Memor ACM Queue 2006; 4 (10)
- Library-based Prefetching for Pointer Intensive Applications Online Technical Manuscript 2006
- Building and Using the ATLAS Transactional Memory System 2006
- Tutorial: Transactional Programming In A Multi-core Environment 2006
- CEARCH: Cognition Enabled Architecture 2006
- The Software Stack for Transactional Memory: Challenges and Opportunities 2006
- Full-system Power Analysis and Modeling for Server Environments 2006
- Testing Implementations of Transactional Memory 2006
- RAMP: Research Accelerator for Multiple Processors 2006
- From Chaos to QoS: Case Studies in CMP Resource Management 2006
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Simultaneously improving code size, performance, and energy in embedded processors
Design, Automation and Test in Europe Conference and Exhibition (DATE 06)
IEEE. 2006: 222–227
View details for Web of Science ID 000243721600045
- Block Aware Instruction Set Architecture ACM Transactions on Architecture and Code Optimization 2006; 3 (3): 327-357
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The common case transactional behavior of multithreaded programs
12th International Symposium on High-Performance Computer Architecture
IEEE COMPUTER SOC. 2006: 271–282
View details for Web of Science ID 000237200400026
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Architectural semantics for practical Transactional Memory
33rd International Symposium on Computer Architecture
IEEE COMPUTER SOC. 2006: 53–64
View details for Web of Science ID 000238976500005
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Heuristics for profile-driven method-level speculative parallelization
34th International Conference on Parallel Processing (ICPP)
IEEE COMPUTER SOC. 2005: 147–156
View details for Web of Science ID 000230567500016
- Transactional Execution of Java Programs 2005
- TAPE: a Transactional Application Profiling Environment 2005
- RAMP: Research Accelerator for Multiple Processors - A Community Vision for a Shared Experimental Parallel HW/SW Platform UC Berkeley Technical Report UCB/CSD-05-1412 2005
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Improving instruction delivery with a block-aware ISA
11th International Euro-Par Conference
SPRINGER-VERLAG BERLIN. 2005: 530–539
View details for Web of Science ID 000232259500060
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Energy-efficient and high-performance instruction fetch using a block-aware ISA
International Symposium on Low Power Electronics and Design
ASSOC COMPUTING MACHINERY. 2005: 36–41
View details for Web of Science ID 000232431400007
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Autonomic power management schemes for Internet servers and data centers
IEEE Global Telecommunications Conference (GLOBECOM 05)
IEEE. 2005: 943–947
View details for Web of Science ID 000234989601059
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Characterization of TCC on chip-multiprocessors
14th International Conference on Parallel Architectures and Compilation Techniques
IEEE COMPUTER SOC. 2005: 63–74
View details for Web of Science ID 000233637100006
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Transactional coherence and consistency: Simplifying parallel hardware and software
IEEE MICRO
2004; 24 (6): 92-103
View details for Web of Science ID 000226365900013
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Programming with transactional coherence and consistency (TCC)
11th International Conference on Architectural Support for Programming Languages and Operating Systems
ASSOC COMPUTING MACHINERY. 2004: 1–13
View details for Web of Science ID 000228341700003
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Transactional memory coherence and consistency
31st Annual International Symposium on Computer Architecture
IEEE COMPUTER SOC. 2004: 102–113
View details for Web of Science ID 000222915900009
- VIRAM-1: A Media-Oriented Vector Processor with Embedded DRAM 2004
- Transactional Memory Coherence and Consistency (TCC) 2004
- Stream Virtual Machine and Two-Level Compilation Model for Streaming Architectures and Languages 2004
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The stream virtual machine
13th International Conference on Parallel Architecture and Compilation Techniques
IEEE COMPUTER SOC. 2004: 267–277
View details for Web of Science ID 000224469900025
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Scalable vector processors for embedded systems
IEEE MICRO
2003; 23 (6): 36-45
View details for Web of Science ID 000188257700007
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Overcoming the limitations of conventional vector processors
30th Annual International Symposium on Computer Architecture
IEEE COMPUTER SOC. 2003: 399–409
View details for Web of Science ID 000183763700034
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Vector vs. superscalar and VLIW architectures for embedded multimedia benchmarks
35th Annual IEEE/ACM International Symposium on Microarchitecture
IEEE COMPUTER SOC. 2002: 283–293
View details for Web of Science ID 000179945200024
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Hardware/compiler codevelopment for an embedded media processor
PROCEEDINGS OF THE IEEE
2001; 89 (11): 1694-1709
View details for Web of Science ID 000172112300010
- Hardware/compiler Codevelopment for an Embedded Media Processor 2001
- Lecture Notes in Computer Science edited by Chong, F., Kozyrakis, C., Oskin, M. 2001
- Vector IRAM: A Media-oriented Vector Processor with Embedded DRAM Technical Record of the 12th Hot Chips Conference 2000
- Exploiting On-chip Memory Bandwidth in the VIRAM Compiler 2000
- Explicitly Parallel Architectures for Memory Performance Enhancement 2000
- Vector IRAM: A Media-oriented Vector Processor with Embedded DRAM 2000
- A Media-Enhanced Vector Architecture for Embedded Memory Systems Technical Report UCB-CSD-99-1059, University of California at Berkeley 1999
- High-Performance Architectures for Embedded Memory Systems 1999
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A new direction for computer architecture research
COMPUTER
1998; 31 (11): 24-?
View details for Web of Science ID 000076716300016
- High-Performance Architectures for Embedded Memory Systems 1998
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Scalable processors in the billion-transistor era: IRAM
COMPUTER
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View details for Web of Science ID A1997XU01900017
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A case for intelligent RAM
IEEE MICRO
1997; 17 (2): 34-44
View details for Web of Science ID A1997WR57900010
- Evaluation of Existing Architectures in IRAM Systems 1997
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Intelligent RAM (IRAM): the industrial setting, applications, and architectures
International Conference on Computer Design - VLSI in Computers and Processors (ICCD 97)
IEEE COMPUTER SOC. 1997: 2–7
View details for Web of Science ID A1997BJ80H00001
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Intelligent RAM (IRAM): Chips that remember and compute
1997 IEEE International Solid-State Circuits Conference
IEEE. 1997: 224–225
View details for Web of Science ID A1997BH40E00085
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The energy efficiency of IRAM architectures
24th Annual International Symposium on Computer Architecture
ASSOC COMPUTING MACHINERY. 1997: 327–337
View details for Web of Science ID A1997BH95B00029
- Pipelined Multi-Queue Management in a VLSI ATM Switch Chip with Credit-Based Flow-Control 1997
- Scalable Processors for the Billion Transistors Era: IRAM IEEE Computer 1997; 30 (9): 75-58
- A Case for Intelligent DRAM: IRAM IEEE Micro 1997; 17 (2): 33-44
- The Energy Efficiency of IRAM Architectures 1997
- Intelligent RAM (IRAM): Chips that Compute and Remember 1997
- Intellingent RAM (IRAM): the Industrial Setting, Applications, and Architectures 1997
- The Architecture, Operation, and Design of the Queue Management Block in the ATLAS I ATM Switch Technical Report FORTH-ICS/TR-172, Institute of Computer Science (ICS), Foundation for Research and Technology (FORTH), Heraklion, Crete, Greece 1996
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Plasticine: A Reconfigurable Architecture For Parallel Patterns
ISCA '17: 44th International Symposium on Computer Architecture, June 2017
2017
View details for DOI 10.1145/3079856.3080256