Bio

John L. Hennessy joined Stanford’s faculty in 1977 as an assistant professor of electrical engineering. He rose through the academic ranks to full professorship in 1986 and was the inaugural Willard R. and Inez Kerr Bell Professor of Electrical Engineering and Computer Science from 1987 to 2004.

From 1983 to 1993, Dr. Hennessy was director of the Computer Systems Laboratory, a research and teaching center operated by the Departments of Electrical Engineering and Computer Science that fosters research in computer systems design. He served as chair of computer science from 1994 to 1996 and, in 1996, was named dean of the School of Engineering. As dean, he launched a five-year plan that laid the groundwork for new activities in bioengineering and biomedical engineering. In 1999, he was named provost, the university’s chief academic and financial officer. As provost, he continued his efforts to foster interdisciplinary activities in the biosciences and bioengineering and oversaw improvements in faculty and staff compensation. In October 2000, he was inaugurated as Stanford University’s 10th president, a position he held until 2016. In 2016, he cofounded the Knight-Hennessy Scholars Program, which provides scholarships and leadership development for a global community of scholars enrolled in graduate programs at Stanford. The program admitted it's first class in 2018 and will provide full scholarships for up to 100 100 students every year.

A pioneer in computer architecture, in 1981 Dr. Hennessy drew together researchers to focus on a computer architecture known as RISC (Reduced Instruction Set Computer), a technology that has revolutionized the computer industry by increasing performance while reducing costs. In addition to his role in the basic research, Dr. Hennessy helped transfer this technology to industry. In 1984, he cofounded MIPS Computer Systems, now MIPS Technologies, which designs microprocessors. In recent years, his research has focused on the architecture of high-performance computers.

Dr. Hennessy is a recipient of the 2000 IEEE John von Neumann Medal, the 2000 ASEE Benjamin Garver Lamme Award, the 2001 ACM Eckert-Mauchly Award, the 2001 Seymour Cray Computer Engineering Award, a 2004 NEC C&C Prize for lifetime achievement in computer science and engineering, a 2005 Founders Award from the American Academy of Arts and Sciences and the 2012 IEEE Medal of Honor, IEEE's highest award. He is a member of the National Academy of Engineering and the National Academy of Sciences, and he is a fellow of the American Academy of Arts and Sciences, the Association for Computing Machinery, and the Institute of Electrical and Electronics Engineers.

He has lectured and published widely and is the co-author of two internationally used undergraduate and graduate textbooks on computer architecture design. Dr. Hennessy earned his bachelor’s degree in electrical engineering from Villanova University and his master’s and doctoral degrees in computer science from the State University of New York at Stony Brook.

Academic Appointments

Administrative Appointments

  • Director, Knight-Hennessy Scholars Program, Stanford University (2016 - Present)
  • President, Stanford Unversity (2000 - 2016)
  • Provost, Stanford University (1999 - 2000)
  • Dean, School of Engineering, Stanford University (1996 - 1999)
  • Chairman, Department of Computer Science, Stanford University (1994 - 1996)
  • Professor of Electrical Engineering and Computer Science, Stanford University (1986 - Present)

Honors & Awards

  • Turing Award, Association of Computing Machinery (2017)
  • Doctor Honris Causa, Mathematics, University of Waterloo (2012)
  • Medal of Honor (Highest award given by the Institute of Electrical and Electronics Engineers), IEEE (2012)
  • Foreign Policy Association Medal and Honorary Fellow, Foreign Policy Association (2010)
  • Morris Chang Exemplary Leadership Award, Global Semiconductor Alliance (2010)
  • Spirit of Silicon Valley—Lifetime Achievement Award, Silicon Valley Leadership Group (2009)
  • Ulysses Medal, University College Dublin (2009)
  • Member, American Philosophical Society (2008)
  • Educational Activities Board Vice President Recognition Award, IEEE (2007)
  • Fellow, Computer History Museum (2007)
  • 100th Anniversary Medallion, College of Engineering, Villanova University (2005)
  • Founders Award, American Academy of Arts and Sciences (2005)
  • Honorary Doctorate, University of Edinburgh (2005)
  • Honorary Doctor Degree, Peking University (2004)
  • Honorary Doctor of Engineering, University of Notre Dame (2004)
  • Koret Prize, Koret Foundation (2004)
  • Prize for lifetime achievement in computer science and engineering, NEC Computers and Communications (2004)
  • Docteur Honris Causa, Ecole Polytechnique Federale de Lausanne (2003)
  • Doctor Honris Causa, Universitat Politècnica de Catalunya (2002)
  • Member, National Academy of Sciences (2002)
  • Eckert-Mauchly Award, Association for Computing Machinery and IEEE Computer Society (2001)
  • Honorary Doctor of Humane Letters, Villanova University (2001)
  • Honorary Doctor of Science, State University of New York at Stony Brook (2001)
  • Seymour Cray Computer Engineering Award, IEEE Computer Society (2001)
  • Benjamin Garver Lamme Award, American Society for Engineering Education (2000)
  • John Von Neumann Medal (jointly with D. Patterson), IEEE (2000)
  • Fellow, Association for Computing Machinery (1997)
  • J. Stanley Morehouse Memorial Award, Villanova University (1997)
  • Fellow, American Academy of Arts and Sciences (1995)
  • Emannuel R. Piore Award, IEEE (1994)
  • Member, National Academy of Engineering (1992)
  • Distinguished Alumnus Award, State University of New York at Stony Brook (1991)
  • Fellow, Institute of Electrical and Electronics Engineers (1991)
  • Willard and Inez Kerr Bell Endowed Professor of Electrical Engineering and Computer Science, Stanford University (1987)
  • Outstanding Service Award, Electrical Engineering Department, Stanford University (1986)
  • Presidential Young Investigator, National Science Foundation (1984)
  • John J. Gallen Memorial Award, Villanova University (1983)
  • Member, Tau Beta Pi (1973)

Boards, Advisory Committees, Professional Organizations

  • Board of Directors, Cisco Systems (2002 - 2017)
  • Board of Trustees, Gordon & Betty Moore Foundation (2012 - Present)
  • Board of Directors, Google (2004 - Present)
  • Technology Advisory Board, Microsoft Corporation (1992 - 1996)
  • Chairman, Board of Directors, Atheros (1998 - 2010)
  • Member, Committee on Research Universities, National Research Council (2010 - Present)
  • Co-chair, Committee on Scientific Communication and National Security, National Research Council (2007 - Present)
  • Member and Chair, NAE, Peer Selection Committee for Computer Science and Engineering (Chair 2000) (1996 - 2000)
  • Member, Committee to Study the Investment Strategy for DARPA, Defense Science Board (1998 - 1999)
  • Member, Commission on Physical Sciences, Mathematics, and Applications, National Research Council (1998 - 1999)
  • Chairman, Information Science and Technology (ISAT) Study, Defense Advanced Research Projects Agency (1994 - 1996)
  • Member, Advisory Committee for Computer and Information Science and Engineering, NSF (1992 - 1996)
  • Member, Fellowship Selection Committee, Sloan Foundation (1993 - 1996)
  • Member, Task Force on Future of Supercomputer Centers Program, National Science Foundation (1995 - 1995)
  • Member, Status and Direction of the High Performance Computing and Communications Initiative (Brooks-Sutherland Committee), National Research Council (1995 - 1995)
  • Member, Computer Science and Technology Board, National Research Council (1989 - 1994)
  • Member, Committee to Study Academic Careers for Experimental Computer Scientists, National Research Council (1992 - 1993)
  • Chair, Oversight Review of the Computer and Information Science and Engineering Institutional Infrastructure Program, National Science Foundation (1992 - 1992)
  • Member, Committee to Study International Developments in Computer Science and Technology, NRC (1988)
  • Academic Advisory Councils and Visiting Committees, College of Engineering, UC Berkeley; College of Engineering, Cornell University; Computer Science Department, Princeton University; School of Engineering and Applied Sciences, Princeton University; NCIR, Dublin, Ireland
  • General Chair, Hot Chips Symposium (1999)
  • Program Committee Co-Chair, Hot Chips Symposium (1993)
  • Program Committee Member, Hot Chips Symposium (1991)
  • Program Chair, 20th International Conference on Computer Architecture (1993)
  • Program Chair, ASPLOS-III Conference (1988)
  • Member, Program Committee, 4th Annual ACM Symposium on Parallel Algorithms and Architectures (1992)
  • Co-Chair, Research in Experimental Computer Science (sponsored by Office of Naval Research) (1991)
  • Member, Program Committee, SOSP Conference (1991)
  • Member, Program Committee, ACM Sigmetrics Conference (1991)
  • Member, Program Committee, ISSMM (1991)
  • Member, Program Committee, Intl. Conference on Shared-Memory Multiprocessors (1990)
  • Member, Program Committee, Intl. Symposium on Computer Architecture (1999)
  • Member, Program Committee, Intl. Symposium on Computer Architecture (1995)
  • Member, Program Committee, Intl. Symposium on Computer Architecture (1990)
  • Member, Program Committee, Intl. Symposium on Computer Architecture (1987)
  • Member, Program Committee, Intl. Symposium on Computer Architecture (1986)
  • Member, Program Committee, ASPLOS-II Conference (1987)
  • Area Editor (Parallel Architecture), Journal of Parallel and Distributed Computing
  • Area Editor (Computer Architecture), Journal of the Association for Computing Machinery (1990 - 1995)
  • Associate Editor, IEEE Transactions on Microelectronic Systems (1992 - 1993)
  • Editor, Journal of the Association for Computing Machinery (1990 - 1993)
  • Editor, Journal of VLSI and Computer Systems (1982 - 1984)
  • Editor, IEEE Design and Test (1984 - 1986)
  • Associate Editor, IEEE MICRO (1981 - 1982)

Professional Education

  • Ph.D., S.U.N.Y. Stony Brook, Computer Science (1977)
  • M.S., S.U.N.Y. Stony Brook, Computer Science (1975)
  • B.E., Villanova University, Electrical Engineering (1973)

Contact

  • Academic
    hennessy@stanford.edu
    University - Faculty Department: Electrical Engineering Position: Professor
    University - Faculty Department: Computer Science Position: Professor
    University - Faculty Department: Knight-Hennessy Scholars Position: University Director

Additional Info

Links

2024-25 Courses

Stanford Advisees

  • Doctoral Dissertation Reader (AC)
    Sho Ko

All Publications

  • Computer Architecture: A Quantitative Approach. Hennessy, J. L., Patterson, D. A. Morgan Kaufmann Publishers, Inc. San Mateo, CA. 1990. Second Edition 1995. Third Edition 2002. Fourth Edition. 2007
  • Computer Organization and Design: The Hardware/Software Interface. Patterson, D. A., Hennessy, J. L. San Mateo, CA: Morgan Kaufmann Publishers, 1993. Second Edition, 1998. Third Edition. 2005
  • INTEGRATING SCALAR OPTIMIZATION AND PARALLELIZATION LECTURE NOTES IN COMPUTER SCIENCE Tjiang, S., Wolf, M., Lam, M., Pieper, K., Hennessy, J. 1992; 589: 137-151

    View details for Web of Science ID A1992KQ19600010

  • The MIPS-X RISC Microprocessor, Chow ed Acken, J., Agarwal, A., Gulak, G., Horowitz, M., McFarling, S., Richardson, S., Saltz, A., Simoni, R., Stark, D., Tijang, S. Kluwer Academic Publishes. Boston, MA. Foreward by J.L. Hennessy. 1989
  • ADVANCES IN COMPILER TECHNOLOGY ANNUAL REVIEW OF COMPUTER SCIENCE Hennessy, J., Ganapathi, M. 1986; 1: 83-106

    View details for Web of Science ID A1986F499800004

  • RISC Architectures. Chow, P., Hennessy, J., L. Elsevier-North Holland, New York. 1986
  • VLSI Electronics. Volume VII: VLSI Design and Architecture. Hennessy, J. L., Przyblski, S. Academic Press, New York.. 1984
  • TOMAL: A Task-Oriented Microprocessor Applications Language IEEE Transactions IECI Hennessy, J., L., Kieburtz, R., B., Smith, D., R. 1975; 8 (22): 283-289
  • Protecting scientific integrity in an age of generative AI. Proceedings of the National Academy of Sciences of the United States of America Blau, W., Cerf, V. G., Enriquez, J., Francisco, J. S., Gasser, U., Gray, M. L., Greaves, M., Grosz, B. J., Jamieson, K. H., Haug, G. H., Hennessy, J. L., Horvitz, E., Kaiser, D. I., London, A. J., Lovell-Badge, R., McNutt, M. K., Minow, M., Mitchell, T. M., Ness, S., Parthasarathy, S., Perlmutter, S., Press, W. H., Wing, J. M., Witherell, M. 2024; 121 (22): e2407886121

    View details for DOI 10.1073/pnas.2407886121

    View details for PubMedID 38771193

  • The 50 Year History of the Microprocessor as Five Technology Eras IEEE MICRO Hennessy, J. L. 2021; 41 (6): 20-21

    View details for DOI 10.1109/MM.2021.3112301

    View details for Web of Science ID 000722002100005

  • On the Spectre and Meltdown Processor Security Vulnerabilities IEEE MICRO Hill, M. D., Masters, J., Ranganathan, P., Turner, P., Hennessy, J. L. 2019; 39 (2): 9–19

    View details for DOI 10.1109/MM.2019.2897677

    View details for Web of Science ID 000461849800003

  • A New Golden Age for Computer Architecture COMMUNICATIONS OF THE ACM Hennessy, J. L., Patterson, D. A. 2019; 62 (2): 48–60

    View details for DOI 10.1145/3282307

    View details for Web of Science ID 000457160600021

  • Q&A Grooming the Leaders of Tomorrow COMMUNICATIONS OF THE ACM Hoffmann, L., Hennessy, J. 2017; 60 (12): 112–11

    View details for DOI 10.1145/3148854

    View details for Web of Science ID 000417206400023

  • A Retrospective on "MIPS: A Microprocessor Architecture" IEEE MICRO Gross, T. R., Jouppi, N. P., Hennessy, J. L., Przybylski, S., Rowen, C. 2016; 36 (4): 73–76

    View details for Web of Science ID 000384909100013

  • Parallel Processors from Client to Cloud COMPUTER ORGANIZATION AND DESIGN: THE HARDWARE/SOFTWARE INTERFACE, 5TH EDITION Patterson, D. A., Hennessy, J. L., Patterson, D., Hennessy, J. 2014: 500–575

    View details for DOI 10.1016/B978-0-12-407726-3.00006-0

    View details for Web of Science ID 000410558900007

  • Computer Abstractions and Technology COMPUTER ORGANIZATION AND DESIGN: THE HARDWARE/SOFTWARE INTERFACE, 5TH EDITION Patterson, D. A., Hennessy, J. L., Patterson, D., Hennessy, J. 2014: 2–59

    View details for DOI 10.1016/B978-0-12-407726-3.00001-1

    View details for Web of Science ID 000410558900002

  • Large and Fast: Exploiting Memory Hierarchy COMPUTER ORGANIZATION AND DESIGN: THE HARDWARE/SOFTWARE INTERFACE, 5TH EDITION Patterson, D. A., Hennessy, J. L., Patterson, D., Hennessy, J. 2014: 372–498

    View details for DOI 10.1016/B978-0-12-407726-3.00005-9

    View details for Web of Science ID 000410558900006

  • Arithmetic for Computers COMPUTER ORGANIZATION AND DESIGN: THE HARDWARE/SOFTWARE INTERFACE, 5TH EDITION Patterson, D. A., Hennessy, J. L., Patterson, D., Hennessy, J. 2014: 176–241

    View details for DOI 10.1016/B978-0-12-407726-3.00003-5

    View details for Web of Science ID 000410558900004

  • The Processor COMPUTER ORGANIZATION AND DESIGN: THE HARDWARE/SOFTWARE INTERFACE, 5TH EDITION Patterson, D. A., Hennessy, J. L., Patterson, D., Hennessy, J. 2014: 242–370

    View details for DOI 10.1016/B978-0-12-407726-3.00004-7

    View details for Web of Science ID 000410558900005

  • Instructions: Language of the Computer COMPUTER ORGANIZATION AND DESIGN: THE HARDWARE/SOFTWARE INTERFACE, 5TH EDITION Patterson, D. A., Hennessy, J. L., Patterson, D., Hennessy, J. 2014: 60–174

    View details for DOI 10.1016/B978-0-12-407726-3.00002-3

    View details for Web of Science ID 000410558900003

  • The Basics of Logic Design COMPUTER ORGANIZATION AND DESIGN: THE HARDWARE/SOFTWARE INTERFACE, 5TH EDITION Patterson, D. A., Hennessy, J. L., Patterson, D., Hennessy, J. 2014: B2–B87

    View details for Web of Science ID 000410558900009

  • Assemblers, Linkers, and the SPIM Simulator COMPUTER ORGANIZATION AND DESIGN: THE HARDWARE/SOFTWARE INTERFACE, 5TH EDITION Patterson, D. A., Hennessy, J. L., Patterson, D., Hennessy, J. 2014: A2–A83

    View details for Web of Science ID 000410558900008

  • 2020 visions NATURE Norvig, P., Relman, D. A., Goldstein, D. B., Kammen, D. M., Weinberger, D. R., Aiello, L. C., Church, G., Hennessy, J. L., Sachs, J., Burrows, A., Pisano, G. P., Goldstein, J. R., Anastas, P., Klausner, R., Baltimore, D., Montgomery, D. R., Baer, T. M., Bigelow, N. P., Holt, R. D., Nicholson, J. K. 2010; 463 (7277): 26-32

    View details for DOI 10.1038/463026a

    View details for Web of Science ID 000273344900016

    View details for PubMedID 20054379

  • Register allocation by priority-based coloring ACM SIGPLAN NOTICES Chow, F., Hennessy, J. 2004; 39 (4): 91-92

    View details for Web of Science ID 000221895400018

  • Register allocation by priority-based coloring ACM SIGPLAN NOTICES Chow, F., Hennessy, J. 2004; 39 (4): 93-103

    View details for Web of Science ID 000221895400019

  • Latency, occupancy, and bandwidth in DSM multiprocessors: A performance evaluation IEEE TRANSACTIONS ON COMPUTERS Chaudhuri, M., Heinrich, M., Holt, C., Singh, J. P., Rothberg, E., Hennessy, J. 2003; 52 (7): 862-880

    View details for Web of Science ID 000183747100004

  • FLASH vs. (Simulated) FLASH: Closing the simulation loop 9th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS_IX) Gibson, J., Kunz, R., Ofelt, D., Horowitz, M., Hennessy, J., Heinrich, M. ASSOC COMPUTING MACHINERY. 2000: 49–58

    View details for Web of Science ID 000165257200006

  • Efficient performance prediction for modern microprocessors International Conference on Measurement and Modeling of Computer Systems (ACM SIGMETRICS 2000) Ofelt, D., HENNESSY, J. L. ASSOC COMPUTING MACHINERY. 2000: 229–39

    View details for Web of Science ID 000088226100031

  • The future of systems research COMPUTER Hennessy, J. 1999; 32 (8): 27-?

    View details for Web of Science ID 000081788500007

  • Cache-coherent distributed shared memory: Perspectives on its development and future challenges PROCEEDINGS OF THE IEEE Hennessy, J., Heinrich, M., Gupta, A. 1999; 87 (3): 418-429

    View details for Web of Science ID 000078743500004

  • A quantitative analysis of the performance and scalability of distributed shared memory cache coherence protocols IEEE TRANSACTIONS ON COMPUTERS Heinrich, M., Soundararajan, V., Hennessy, J., Gupta, A. 1999; 48 (2): 205-217

    View details for Web of Science ID 000079060200013

  • Flexible use of memory for replication/migration in cache-coherent DSM multiprocessors 25th Annual International Symposium on Computer Architecture (ISCA 98) Soundararajan, V., Heinrich, M., Verghese, B., Gharachorloo, K., Gupta, A., Hennessy, J. IEEE COMPUTER SOC. 1998: 342–355

    View details for Web of Science ID 000074685600030

  • A nationwide parallel computing environment COMMUNICATIONS OF THE ACM Kennedy, K., Bender, C. F., CONNOLLY, J. W., HENNESSY, J. L., Vernon, M. K., Smarr, L. 1997; 40 (11): 62-72

    View details for Web of Science ID A1997YC47500011

  • Hardware/software co-design of the Stanford FLASH multiprocessor PROCEEDINGS OF THE IEEE Heinrich, M., Ofelt, D., Horowitz, M. A., Hennessy, J. 1997; 85 (3): 455-466

    View details for Web of Science ID A1997WN92900007

  • An evaluation of a commercial CC-NUMA architecture - The CONVEX exemplar SPP1200 11th International Parallel Processing Symposium (IPPS 97) THEKKATH, R., SINGH, A. P., Singh, J. P., John, S., Hennessy, J. IEEE COMPUTER SOC. 1997: 8–17

    View details for Web of Science ID A1997BH56G00002

  • RISC microprocessors IEEE MICRO Hennessy, J. 1996; 16 (6): 27-27

    View details for Web of Science ID A1996WE16800011

  • SoftFLASH: Analyzing the performance of clustered distributed virtual shared memory 7th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-VII) Erlichson, A., Nuckolls, N., Chesson, G., Hennessy, J. ASSOC COMPUTING MACHINERY. 1996: 210–20

    View details for Web of Science ID A1996VM12800021

  • Hardware software co-design of processors: Concepts and examples NATO Advanced Study Institute on Hardware/Software Co-Design Hennessy, J., Heinrich, M. SPRINGER. 1996: 29–44

    View details for Web of Science ID A1996BF04R00002

  • Application and architectural bottlenecks in large scale distributed shared memory machines 23rd Annual International Symposium on Computer Architecture Holt, C., Singh, J. P., Hennessy, J. ASSOC COMPUTING MACHINERY. 1996: 134–145

    View details for Web of Science ID A1996BF68U00013

  • LOAD BALANCING AND DATA LOCALITY IN ADAPTIVE HIERARCHICAL N-BODY METHODS - BARNES-HUT, FAST MULTIPOLE, AND RADIOSITY JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING Singh, J. P., Holt, C., Totsuka, T., Gupta, A., Hennessy, J. 1995; 27 (2): 118-141

    View details for Web of Science ID A1995RG09300002

  • IMPLICATIONS OF HIERARCHICAL N-BODY METHODS FOR MULTIPROCESSOR ARCHITECTURES ACM TRANSACTIONS ON COMPUTER SYSTEMS Singh, J. P., HENNESSY, J. L., Gupta, A. 1995; 13 (2): 141-202

    View details for Web of Science ID A1995RM74900003

  • EFFECTIVENESS OF DATA DEPENDENCE ANALYSIS INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING Maydan, D. E., HENNESSY, J. L., Lam, M. S. 1995; 23 (1): 63-81

    View details for Web of Science ID A1995QJ76700004

  • Hardware/Software Codesign of Processor Concepts and Examples Hennessy, J., L., Heinrich, M. 1995
  • SUIF - AN INFRASTRUCTURE FOR RESEARCH ON PARALLELIZING AND OPTIMIZING COMPILERS SIGPLAN NOTICES Wilson, R. P., French, R. S., Wilson, C. S., AMARASINGHE, S. P., Anderson, J. M., TJIANG, S. W., Liao, S. W., Tseng, C. W., Hall, M. W., Lam, M. S., HENNESSY, J. L. 1994; 29 (12): 31-37

    View details for Web of Science ID A1994PX39000005

  • THE PERFORMANCE ADVANTAGES OF INTEGRATING BLOCK DATA TRANSFER IN CACHE-COHERENT MULTIPROCESSORS 6th International Conference on Architectural Support for Programming Languages and Operating Systems Woo, S. C., Singh, J. P., HENNESSY, J. L. ASSOC COMPUTING MACHINERY. 1994: 219–29

    View details for Web of Science ID A1994PX02700021

  • THE PERFORMANCE IMPACT OF FLEXIBILITY IN THE STANFORD FLASH MULTIPROCESSOR 6th International Conference on Architectural Support for Programming Languages and Operating Systems Heinrich, M., KUSKIN, J., Ofelt, D., Heinlein, J., Baxter, J., Singh, J. P., Simoni, R., Gharachorloo, K., NAKAHIRA, D., Horowitz, M., Gupta, A., Rosenblum, M., Hennessy, J. ASSOC COMPUTING MACHINERY. 1994: 274–85

    View details for Web of Science ID A1994PX02700026

  • COOL - AN OBJECT-BASED LANGUAGE FOR PARALLEL PROGRAMMING COMPUTER Chandra, R., Gupta, A., HENNESSY, J. L. 1994; 27 (8): 13-26

    View details for Web of Science ID A1994PB81900002

  • FALSE SHARING AND SPATIAL LOCALITY IN MULTIPROCESSOR CACHES IEEE TRANSACTIONS ON COMPUTERS Torrellas, J., Lam, M. S., HENNESSY, J. L. 1994; 43 (6): 651-663

    View details for Web of Science ID A1994NR95300002

  • THE STANFORD FLASH MULTIPROCESSOR 21st Annual International Symposium on Computer Architecture KUSKIN, J., Ofelt, D., Heinrich, M., Heinlein, J., Simoni, R., Gharachorloo, K., Chapin, J., NAKAHIRA, D., Baxter, J., Horowitz, M., Gupta, A., Rosenblum, M., Hennessy, J. I E E E, COMPUTER SOC PRESS. 1994: 302–313

    View details for Web of Science ID A1994BA93B00027

  • Integrating Concurrency and Data Abstraction in the COOL Programming Language. IEEE Computer. Chandra, R., Gupta, A., Hennessy, J., L. 1994
  • EVALUATING THE MEMORY OVERHEAD REQUIRED FOR COMA ARCHITECTURES 21st Annual International Symposium on Computer Architecture Joe, T., HENNESSY, J. L. I E E E, COMPUTER SOC PRESS. 1994: 82–93

    View details for Web of Science ID A1994BA93B00008

  • COMPILE-TIME COPY ELIMINATION SOFTWARE-PRACTICE & EXPERIENCE SCHNORF, P., Ganapathi, M., HENNESSY, J. L. 1993; 23 (11): 1175-1200

    View details for Web of Science ID A1993MG83800001

  • MICROPROCESSORS - FROM DESKTOPS TO SUPERCOMPUTERS SCIENCE Baskett, F., HENNESSY, J. L. 1993; 261 (5123): 864-871

    Abstract

    Continuing improvements in integrated circuit technology and computer architecture have driven microprocessors to performance levels that rival those of supercomputers-at a fraction of the price. The use of sophisticated memory hierarchies enables microprocessor-based machines to have very large memories built from commodity dynamic random access memory while retaining the high bandwidth and low access time needed in a high-performance machine. Parallel processors composed of these high-performance microprocessors are becoming the supercomputing technology of choice for scientific and engineering applications. The challenges for these new supercomputers have been in developing multiprocessor architectures that are easy to program and that deliver high performance without extraordinary programming efforts by users. Recent progress in multiprocessor architecture has led to ways to meet these challenges.

    View details for Web of Science ID A1993LR89700026

    View details for PubMedID 17783732

  • DATA LOCALITY AND LOAD BALANCING IN COOL 4TH SYMP ON PRINCIPLES AND PRACTICE OF PARALLEL PROGRAMMING ( PPOPP ) Chandra, R., Gupta, A., HENNESSY, J. L. ASSOC COMPUTING MACHINERY. 1993: 249–59

    View details for Web of Science ID A1993LF54800027

  • SCALING PARALLEL PROGRAMS FOR MULTIPROCESSORS - METHODOLOGY AND EXAMPLES COMPUTER Singh, J. P., HENNESSY, J. L., Gupta, A. 1993; 26 (7): 42-50

    View details for Web of Science ID A1993LL90400004

  • MTOOL - AN INTEGRATED SYSTEM FOR PERFORMANCE DEBUGGING SHARED MEMORY MULTIPROCESSOR APPLICATIONS IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS Goldberg, A. J., HENNESSY, J. L. 1993; 4 (1): 28-40

    View details for Web of Science ID A1993KQ61500003

  • The Accuracy of Trace-Driven Simulations of Multiprocessors Goldschmidt, S., R., Hennessy, J., L. 1993
  • A PARALLEL ADAPTIVE FAST MULTIPOLE METHOD Supercomputing 93 Conference Singh, J. P., Holt, C., HENNESSY, J. L., Gupta, A. I E E E, COMPUTER SOC PRESS. 1993: 54–65

    View details for Web of Science ID A1993BA18A00006

  • THE DASH PROTOTYPE - LOGIC OVERHEAD AND PERFORMANCE IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS Lenoski, D., LAUDON, J., Joe, T., NAKAHIRA, D., Stevens, L., Gupta, A., Hennessy, J. 1993; 4 (1): 41-61

    View details for Web of Science ID A1993KQ61500004

  • AN EMPIRICAL-COMPARISON OF THE KENDALL SQUARE RESEARCH KSR-1 AND STANFORD DASH MULTIPROCESSORS Supercomputing 93 Conference Singh, J. P., Joe, T., Gupta, A., HENNESSY, J. L. I E E E, COMPUTER SOC PRESS. 1993: 214–225

    View details for Web of Science ID A1993BA18A00022

  • CHARACTERIZING THE CACHING AND SYNCHRONIZATION PERFORMANCE OF A MULTIPROCESSOR OPERATING SYSTEM SIGPLAN NOTICES Torrellas, J., Gupta, A., Hennessy, J. 1992; 27 (9): 162-174

    View details for Web of Science ID A1992JT83700014

  • PROGRAMMING FOR DIFFERENT MEMORY CONSISTENCY MODELS JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING Gharachorloo, K., Adve, S. V., Gupta, A., HENNESSY, J. L., Hill, M. D. 1992; 15 (4): 399-407

    View details for Web of Science ID A1992JK70000007

  • SHARLIT - A TOOL FOR BUILDING OPTIMIZERS CONF ON PROGRAMMING LANGUAGE DESIGN AND IMPLEMENTATION ( ACM SIGPLAN 92 ) TJIANG, S. W., HENNESSY, J. L. ASSOC COMPUTING MACHINERY. 1992: 82–93

    View details for Web of Science ID A1992HW16100009

  • FINDING AND EXPLOITING PARALLELISM IN AN OCEAN SIMULATION PROGRAM - EXPERIENCE, RESULTS, AND IMPLICATIONS JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING Singh, J. P., HENNESSY, J. L. 1992; 15 (1): 27-48

    View details for Web of Science ID A1992HV09300002

  • THE STANFORD DASH MULTIPROCESSOR COMPUTER Lenoski, D., LAUDON, J., Gharachorloo, K., Weber, W. D., Gupta, A., Hennessy, J., Horowitz, M., Lam, M. S. 1992; 25 (3): 63-79

    View details for Web of Science ID A1992HH04100006

  • OVERVIEW AND STATUS OF THE STANFORD DASH MULTIPROCESSOR INTERNATIONAL SYMP ON SHARED MEMORY MULTIPROCESSING Lenoski, D., LAUDON, J., Gharachorloo, K., Weber, W. D., Gupta, A., Hennessy, J. M I T PRESS. 1992: 391–406

    View details for Web of Science ID A1992BX58Y00016

  • INTEGRATING SCALAR OPTIMIZATION AND PARALLELIZATION 4TH INTERNATIONAL WORKSHOP ON LANGUAGES AND COMPILERS FOR PARALLEL COMPUTING Tjiang, S., Wolf, M., Lam, M., Pieper, K., Hennessy, J. SPRINGER-VERLAG BERLIN. 1992: 137–151

    View details for Web of Science ID A1992BX63Q00010

  • Integrating Scalar Optimization and Parallelization. Languages and Compilers for Parallel Computing. Tjiang, S., Wolf, M., Lam, M., Pieper, K., Hennessy, J. edited by Banerjee Springer-Verlag. New York.. 1992: 1
  • THE DASH PROTOTYPE - IMPLEMENTATION AND PERFORMANCE 19TH ANNUAL INTERNATIONAL SYMP ON COMPUTER ARCHITECTURE Lenoski, D., LAUDON, J., Joe, T., NAKAHIRA, D., Stevens, L., Gupta, A., Hennessy, J. ASSOC COMPUTING MACHINERY. 1992: 92–103

    View details for Web of Science ID A1992BW32V00009

  • HIDING MEMORY LATENCY USING DYNAMIC SCHEDULING IN SHARED-MEMORY MULTIPROCESSORS 19TH ANNUAL INTERNATIONAL SYMP ON COMPUTER ARCHITECTURE Gharachorloo, K., Gupta, A., Hennessy, J. ASSOC COMPUTING MACHINERY. 1992: 22–33

    View details for Web of Science ID A1992BW32V00003

  • Integrating Concurrency and Data Abstraction in a Parallel Programming Language Chandra, R., Gupta, A., Hennessy, J., L. 1992
  • Implications of Hierarchical N-body Techniques for Multiprocessor Architecture Singh, J., P., Hennessy, J., L., Gupta, A. 1992
  • A Parallel Adaptive Fast Multipole Method, SIAM Singh, J., Holt, C., Gupta, A., Hennessy, J. 1992
  • COMPUTER-TECHNOLOGY AND ARCHITECTURE - AN EVOLVING INTERACTION COMPUTER HENNESSY, J. L., Jouppi, N. P. 1991; 24 (9): 18-29

    View details for Web of Science ID A1991GD91300003

  • EFFICIENT AND EXACT DATA DEPENDENCE ANALYSIS CONF ON PROGRAMMING LANGUAGE : DESIGN AND IMPLEMENTATION Maydan, D. E., HENNESSY, J. L., Lam, M. S. ASSOC COMPUTING MACHINERY. 1991: 1–14

    View details for Web of Science ID A1991FP75600002

  • PERFORMANCE EVALUATION OF MEMORY CONSISTENCY MODELS FOR SHARED-MEMORY MULTIPROCESSORS 4TH INTERNATIONAL CONF ON ARCHITECTURAL SUPPORT FOR PROGRAMMING LANGUAGES AND OPERATING SYSTEMS Gharachorloo, K., Gupta, A., Hennessy, J. ASSOC COMPUTING MACHINERY. 1991: 245–57

    View details for Web of Science ID A1991FN30700024

  • Multiprocessor Simulation and Tracing Using Tango Davis, H., Goldschmidt, S., R., Hennessy, J. 1991
  • MTOOL - A METHOD FOR ISOLATING MEMORY BOTTLENECKS IN SHARED MEMORY MULTIPROCESSOR PROGRAMS INTERNATIONAL CONF ON PARALLEL PROCESSING Goldberg, A., Hennessy, J. CRC PRESS INC. 1991: 251–257

    View details for Web of Science ID A1991BV45D00039

  • COMPARATIVE-EVALUATION OF LATENCY REDUCING AND TOLERATING TECHNIQUES 18TH ANNUAL INTERNATIONAL SYMP ON COMPUTER ARCHITECTURE Gupta, A., Hennessy, J., Gharachorloo, K., MOWRY, T., Weber, W. D. ASSOC COMPUTING MACHINERY. 1991: 254–263

    View details for Web of Science ID A1991BT52Q00025

  • PERFORMANCE DEBUGGING SHARED MEMORY MULTIPROCESSOR PROGRAMS WITH MTOOL 4TH ANNUAL CONF ON HIGH PERFORMANCE COMPUTING ( SUPERCOMPUTING 91 ) Goldberg, A. J., HENNESSY, J. L. I E E E, COMPUTER SOC PRESS. 1991: 481–490

    View details for Web of Science ID A1991BV10P00047

  • 2 TECHNIQUES TO ENHANCE THE PERFORMANCE OF MEMORY CONSISTENCY MODELS INTERNATIONAL CONF ON PARALLEL PROCESSING Gharachorloo, K., Gupta, A., Hennessy, J. CRC PRESS INC. 1991: I355–I364

    View details for Web of Science ID A1991BV45C00058

  • An Empirical Investigation of the Effectiveness and Limitations of Automatic Parallelization Singh, J., P., Hennessy, J. 1991
  • Two Techniques to Enhance the Performance of Memory Consistency Models Gharachorloo, K., Gupta, A., Hennessy, J. 1991
  • MTOOL: A Method for Isolating Memory Bottlenecks in Shared Memory Multiprocessor Programs Goldberg, A., Hennessy, J. 1991
  • Data Locality and Memory System Performance in the Parallel Simulation of Ocean Eddy Currents. Singh, J., P., Hennessy, J., L 1991
  • Data Locality and Cache Performance in the Parallel Simulation of Ocean Eddy Currents Singh, J., P., Hennessy, J., L. 1991
  • Comparative Evaluation of Latency Reducing and Tolerating Techniques Gupta, A., Hennessy, J., Gharachorloo, K., Mowry, T., Weber, W.-D. 1991
  • Performance Debugging Shared Memory Multiprocessor Programs with MTOOL Supercomputing 91, Albuquerque, NM. Goldberg, A., Hennessy, J. 1991
  • THE PRIORITY-BASED COLORING APPROACH TO REGISTER ALLOCATION ACM TRANSACTIONS ON PROGRAMMING LANGUAGES AND SYSTEMS Chow, F. C., HENNESSY, J. L. 1990; 12 (4): 501-536

    View details for Web of Science ID A1990EH70500001

  • Analysis of Critical Architectural and Program Parameters in a Hierarchical Shared-Memory Multiprocessor ACM, Sigmetrics Torrellas, J., Hennessy, J., Weil, T. 1990
  • ANALYSIS OF CRITICAL ARCHITECTURAL AND PROGRAM PARAMETERS IN A HIERARCHICAL SHARED-MEMORY MULTIPROCESSOR 1990 CONF ON MEASUREMENT AND MODELING OF COMPUTER SYSTEMS Torrellas, J., Hennessy, J., Weil, T. ASSOC COMPUTING MACHINERY. 1990: 163–172

    View details for Web of Science ID A1990BR67M00017

  • THE DIRECTORY-BASED CACHE COHERENCE PROTOCOL FOR THE DASH MULTIPROCESSOR 17TH ANNUAL INTERNATIONAL SYMP ON COMPUTER ARCHITECTURE Lenoski, D., LAUDON, J., Gharachorloo, K., Gupta, A., Hennessy, J. I E E E, COMPUTER SOC PRESS. 1990: 148–159

    View details for Web of Science ID A1990BQ97U00014

  • MEMORY CONSISTENCY AND EVENT ORDERING IN SCALABLE SHARED-MEMORY MULTIPROCESSORS 17TH ANNUAL INTERNATIONAL SYMP ON COMPUTER ARCHITECTURE Gharachorloo, K., Lenoski, D., LAUDON, J., Gibbons, P., Gupta, A., Hennessy, J. I E E E, COMPUTER SOC PRESS. 1990: 15–26

    View details for Web of Science ID A1990BQ97U00002

  • High Performance Microprocessor Architectures International Journal of High Speed Electronics. Katz, R., H., Hennessy, J., L. 1990; 1 (1): 1-18
  • Design of Scalable Shared-Memory Multiprocessors: The DASH Approach ACM, Compcon Lenoski, D., Gharacharloo, K., Laudon, J., Gupta, A., Hennessy, J., L., Horowitz, M. 1990
  • Shared Data Placement Optimizations to Reduce Multiprocessor Cache Miss Rates Torrellas, J., Lam, M., Hennessy, J., L. 1990
  • AN ANALYTICAL CACHE MODEL ACM TRANSACTIONS ON COMPUTER SYSTEMS Agarwal, A., Horowitz, M., Hennessy, J. 1989; 7 (2): 184-215

    View details for Web of Science ID A1989U462500003

  • A SIMPLE INTERPROCEDURAL REGISTER ALLOCATION ALGORITHM AND ITS EFFECTIVENESS FOR LISP ACM TRANSACTIONS ON PROGRAMMING LANGUAGES AND SYSTEMS STEENKISTE, P. A., HENNESSY, J. L. 1989; 11 (1): 1-32

    View details for Web of Science ID A1989T191800001

  • Forward The MIPS-X RISC Microprocessor Hennessy, J., L. edited by Chow Kluwer Academic Publishers. Boston, MA. 1989: 1
  • RISC Architecture: A Perspective on the Past and Future Hennessy, J., L. 1989
  • Copy Elimination in Functional Languages. Gopinath, K., Hennessy, J., L. 1989
  • Characteristics of Performance-Optimal Multi-Level Cache Hierarchies Przybylski, S., Horowitz, M., Hennessy, J. 1989
  • CACHE PERFORMANCE OF OPERATING SYSTEM AND MULTIPROGRAMMING WORKLOADS ACM TRANSACTIONS ON COMPUTER SYSTEMS Agarwal, A., Hennessy, J., Horowitz, M. 1988; 6 (4): 393-431

    View details for Web of Science ID A1988Q844600003

  • CHARACTERIZING THE SYNCHRONIZATION BEHAVIOR OF PARALLEL PROGRAMS SIGPLAN NOTICES Davis, H., Hennessy, J. 1988; 23 (9): 198-211

    View details for Web of Science ID A1988P692500019

  • MEASUREMENT AND EVALUATION OF THE MIPS ARCHITECTURE AND PROCESSOR ACM TRANSACTIONS ON COMPUTER SYSTEMS Gross, T. R., HENNESSY, J. L., Przybylski, S. A., Rowen, C. 1988; 6 (3): 229-257

    View details for Web of Science ID A1988P488900001

  • LISP ON A REDUCED-INSTRUCTION-SET PROCESSOR - CHARACTERIZATION AND OPTIMIZATION COMPUTER Steenkiste, P., Hennessy, J. 1988; 21 (7): 34-45

    View details for Web of Science ID A1988P236600004

  • A Simple and Efficient Implementation Approach for Single Assignment Languages. Gharachorloo, K., Sarkar, V., Hennessy, J., L. 1988
  • Performance Effects in Memory Hierarchy Design Przybylski, S., Horowitz, M., Hennessy, J., L. 1988
  • An Evaluation of Directory Schemes for Cache Consistency Agarwal, A., Simoni, R., Hennessy, J., L. 1988
  • MIPS-X - A 20-MIPS PEAK, 32-BIT MICROPROCESSOR WITH ON-CHIP CACHE IEEE JOURNAL OF SOLID-STATE CIRCUITS Horowitz, M., Chow, P., Stark, D., SIMONI, R. T., SALZ, A., PRZYBYLSKI, S., Hennessy, J., Gulak, G., Agarwal, A., Acken, J. M. 1987; 22 (5): 790-799

    View details for Web of Science ID A1987K182100024

  • Tags and Type Checking in Lisp: Hardware and Software Approaches Steenkiste, P., Hennessy, J., L. 1987
  • COMPILE-TIME PARTITIONING AND SCHEDULING OF PARALLEL PROGRAMS SIGPLAN NOTICES Sarkar, V., Hennessy, J. 1986; 21 (7): 17-26

    View details for Web of Science ID A1986E058100003

  • SMALL SHARED-MEMORY MULTIPROCESSORS SCIENCE Baskett, F., HENNESSY, J. L. 1986; 231 (4741): 963-967

    Abstract

    Multiprocessors built from today's microprocessors are economically attractive. Although we can use these multiprocessors for time-sharing applications, it would be preferable to use them as true parallel processors. One key to achieving efficient parallel processing is to match the communications capabilities of the multiprocessor to the communications needs of the problem. The other key is improved parallel programming systems. If these are achieved, then efficient parallel processing can be approached from both ends by providing more communications capability in the hardware and restructuring the problem to reduce the communications requirements.

    View details for Web of Science ID A1986A067700019

    View details for PubMedID 17740293

  • LISP on a Reduced-Instruction-Set Processor. Steenkiste, P., Hennessy, J., L. 1986
  • Reducing the Cost of Branches McFarling, S., Hennessy, J., L. 1986
  • Partitioning Parallel Programs for Macro-Dataflow Sarkar, V., Hennessy, J., L 1986
  • Logic Minimization, Placement and Routing in SWAMI Rowen, C., Hennessy, J., L. 1985
  • SWAMI: A Flexible Logic Implementation System. Rowen, C., Hennessy, J., L. 1985
  • REGISTER ALLOCATION BY PRIORITY-BASED COLORING SIGPLAN NOTICES Chow, F., Hennessy, J. 1984; 19 (6): 222-232

    View details for Web of Science ID A1984SZ90500023

  • VLSI Processor Design Methodology. VLSI Electronics. Volume VII: VLSI Design and Architecture Hennessy, J., L., Przybylski, S. Academic Press, New York. 1984: 1
  • MIPS: A High Performance 32-Bit NMOS Microprocessor Rowen, C., Przybylski, S., Jouppi, N., Gross, T., Shott, J., Hennessy, J., L. 1984
  • VLSI PROCESSOR ARCHITECTURE IEEE TRANSACTIONS ON COMPUTERS HENNESSY, J. L. 1984; 33 (12): 1221-1246

    View details for Web of Science ID A1984TV61200010

  • ORGANIZATION AND VLSI IMPLEMENTATION OF MIPS JOURNAL OF VLSI AND COMPUTER SYSTEMS Przybylski, S. A., Gross, T. R., HENNESSY, J. L., Jouppi, N. P., Rowen, C. 1984; 1 (2): 170-208

    View details for Web of Science ID A1984TU30600004

  • A PIPELINED 32B NMOS MICROPROCESSOR ISSCC DIGEST OF TECHNICAL PAPERS Rowen, C., PRZBYLSKI, S. A., Jouppi, N. P., Gross, T. R., SHOTT, J. D., HENNESSY, J. L. 1984; 27: 180-181

    View details for Web of Science ID A1984SJ77000073

  • COMPLEX VERSUS REDUCED INSTRUCTION SET COMPUTERS ISSCC DIGEST OF TECHNICAL PAPERS HENNESSY, J. L., Lu, P., Patterson, D. A., Radin, G., SECCOMBE, S. D., Tredennick, N., VERHOFSTADT, P. 1983; 26: 218-219

    View details for Web of Science ID A1983QL69100087

  • Partitioning Programmable Logic Arrays Hennessy, J., L. 1983
  • Design of a High Performance VLSI Processor. Hennessy, J., L., Jouppi, N., Przybylski, S., Rowen, C., Gross, T. 1983
  • POSTPASS CODE OPTIMIZATION OF PIPELINE CONSTRAINTS ACM TRANSACTIONS ON PROGRAMMING LANGUAGES AND SYSTEMS Hennessy, J., Gross, T. 1983; 5 (3): 422-448

    View details for Web of Science ID A1983RF34100008

  • THE DESIGN AND IMPLEMENTATION OF PARAMETRIC TYPES IN PASCAL SOFTWARE-PRACTICE & EXPERIENCE Hennessy, J., Elmquist, H. 1982; 12 (2): 169-184

    View details for Web of Science ID A1982ND62700006

  • TOMAL: A Task-Oriented Microprocessor Applications Language. Hennessy, J., L., Kieburtz, R., B., Smith, D., R. edited by Glass, R., L. Real-Time Software, Prentice-Hall. 1982
  • Code Generation and Reorganization in the Presence of Pipeline Constraints Hennessy, J., L., Gross, T., R. 1982
  • Automatic Compiler Code Generation. Computing Surveys Ganapathi, M., Fisher, C., N., Hennessy, J., L. 1982
  • COMPILATION OF THE PASCAL CASE STATEMENT SOFTWARE-PRACTICE & EXPERIENCE HENNESSY, J. L., Mendelsohn, N. 1982; 12 (9): 879-882

    View details for Web of Science ID A1982PJ41900006

  • RETARGETABLE COMPILER CODE GENERATION COMPUTING SURVEYS Ganapathi, M., Fischer, C. N., HENNESSY, J. L. 1982; 14 (4): 573-592

    View details for Web of Science ID A1982QD29000003

  • SYMBOLIC DEBUGGING OF OPTIMIZED CODE ACM TRANSACTIONS ON PROGRAMMING LANGUAGES AND SYSTEMS Hennessy, J. 1982; 4 (3): 323-344

    View details for Web of Science ID A1982PA96000001

  • THE FORMAL DEFINITION OF A REAL-TIME LANGUAGE ACTA INFORMATICA HENNESSY, J. L., Kieburtz, R. B. 1981; 16 (3): 309-345

    View details for Web of Science ID A1981MT65600004

  • Program Optimization and Exception Handling. Hennessy, J., L. 1981
  • MIPS: A VLSI Processor Architecture. Hennessy, J., L., Jouppi, N., Baskett, F., Gill, J. 1981
  • WSCLOCK: A Simple and Effective Virtual Memory Management Algorithm. Carr, R., W., Hennessy, J., L. 1981
  • A Language for Microcode Description and Simulation in VLSI. Hennessy, J., L. 1981
  • PARALLELISM AND REPRESENTATION PROBLEMS IN DISTRIBUTED SYSTEMS IEEE TRANSACTIONS ON COMPUTERS Flynn, M. J., HENNESSY, J. L. 1980; 29 (12): 1080-1086

    View details for Web of Science ID A1980KV26500006

  • A System for Producing Multitasking Software for Microprocessors. Hennessy, J., L., Kieburtz, R., B. 1976
  • TOMAL - TASK-ORIENTED MICROPROCESSOR APPLICATIONS LANGUAGE IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS AND CONTROL INSTRUMENTATION HENNESSY, J. L., Kieburtz, R. B., Smith, D. R. 1975; 22 (3): 283-289

    View details for Web of Science ID A1975AL47400006

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