Mark Horowitz
Fortinet Founders Chair of the Department of Electrical Engineering, Yahoo! Founders Professor in the School of Engineering and Professor of Computer Science
Web page: http://web.stanford.edu/people/horowitz
Bio
Professor Horowitz initially focused on designing high-performance digital systems by combining work in computer-aided design tools, circuit design, and system architecture. During this time, he built a number of early RISC microprocessors, and contributed to the design of early distributed shared memory multiprocessors. In 1990, Dr. Horowitz took leave from Stanford to help start Rambus Inc., a company designing high-bandwidth memory interface technology. After returning in 1991, his research group pioneered many innovations in high-speed link design, and many of today’s high speed link designs are designed by his former students or colleagues from Rambus.
In the 2000s he started a long collaboration with Prof. Levoy on computational photography, which included work that led to the Lytro camera, whose photographs could be refocused after they were captured.. Dr. Horowitz's current research interests are quite broad and span using EE and CS analysis methods to problems in neuro and molecular biology to creating new agile design methodologies for analog and digital VLSI circuits. He remains interested in learning new things, and building interdisciplinary teams.
Academic Appointments
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Professor, Electrical Engineering
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Professor, Computer Science
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Member, Bio-X
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Affiliate, Precourt Institute for Energy
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Member, Wu Tsai Neurosciences Institute
Administrative Appointments
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Chair, Electrical Engineering Department (2023 - Present)
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Vice Chair, 54th Senate of the Academic Council (2021 - 2022)
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Steering Committee, 53rd Senate of the Academic Council (2020 - 2021)
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Chair, Committee on Academic Computing and Information Systems (C-ACIS) (2019 - 2022)
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Chair, Electrical Engineering Department (2008 - 2012)
Honors & Awards
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Elected Fellow, IEEE
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Elected Fellow, Association for Computing Machinery
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Eckert-Mauchly Award, ACM and IEEE Computer Society (2022)
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Faculty Researcher Award, SIA (2011)
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Donald O. Pederson Technical Field Award, IEEE (2006)
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Best Paper Award, ISQED (2005)
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Most Influential Paper of 1989, ISCA (2004)
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Jack Kilby Outstanding Paper Award, ISSCC (2003)
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Most influential paper, International Symposium of Computer Arch (1994)
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Best Paper Award, ISSCC (1993)
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Most Influential Paper, International Symposium on Computer Architecture (1989)
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Presidential Young Investigator Award, NSF (1985)
Boards, Advisory Committees, Professional Organizations
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Member, National Academy of Engineering (2013 - Present)
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Member, Computer Science and Telecommunications Advisory Board, NAS (2013 - 2019)
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Member, American Academy of Arts and Sciences (2013 - Present)
Program Affiliations
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Stanford SystemX Alliance
Professional Education
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PhD, Stanford University (1984)
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MS, MIT (1978)
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BS, MIT (1978)
Patents
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Gary B. Bronner, Brent S. Haukness, Mark A. Horowitz, Mark D. Kellam, Fariborz Assaderaghi. "United States Patent 11,244,727 Dynamic memory rank configuration", Rambus Inc, Feb 8, 2022
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Vladimir M Stojanovic, Andrew C Ho, Anthony Bessios, Bruno W Garlepp, Grace Tsang, Mark A Horowitz, Jared L Zerbe, Jason C Wei. "United States Patent 16/999,853 Partial response receiver", Rambus Inc, Mar 11, 2021
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Craig Hampel, Mark Horowitz. "United States Patent 17/000,130 System including hierarchical memory modules having different types of integrated circuit memory devices", Rambus Inc, Feb 4, 2021
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Mark Alan Horowitz, Ilias Pappas, Edward Buckley, William Thomas Blank. "United States Patent 10,861,380 Display systems with hybrid emitter circuits", Facebook Technologies LLC, Dec 8, 2020
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Haw-Jyh Liaw, Xingchao Yuan, Mark A Horowitz. "United States Patent 10,782,344 Technique for determining performance characteristics of electronic devices and systems", Rambus Inc, Sep 22, 2020
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Vladimir M Stojanovic, Andrew C Ho, Anthony Bessios, Fred F Chen, Elad Alon, Mark A Horowitz. "United States Patent 10,771,295 High speed signaling system with adaptive transmit pre-emphasis", Rambus Inc, Sep 8, 2020
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Vladimir M Stojanovic, Andrew C Ho, Anthony Bessios, Bruno W Garlepp, Grace Tsang, Mark A Horowitz, Jared L Zerbe, Jason C Wei. "United States Patent 10,764,094 Partial response receiver", Rambus Inc, Sep 1, 2020
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Craig Hampel, Mark Horowitz. "United States Patent 10,755,794 System including hierarchical memory modules having different types of integrated circuit memory devices", Rambus Inc, Aug 25, 2020
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Ely K Tsern, Mark A Horowitz, Frederick A Ware. "United States Patent 16/805,619 Memory Controller With Error Detection And Retry Modes Of Operation", Rambus Inc, Aug 20, 2020
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Ely K Tsern, Mark A Horowitz, Frederick A Ware. "United States Patent 10,621,023 Memory controller with error detection and retry modes of operation", Rambus Inc, Apr 14, 2020
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Vladimir M Stojanovic, Andrew C Ho, Anthony Bessios, Fred F Chen, Elad Alon, Mark A Horowitz. "United States Patent 10,411,923 High speed signaling system with adaptive transmit pre-emphasis", Rambus Inc, Sep 10, 2019
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Mark A Horowitz, Craig E Hampel, Alfredo Moncayo, Kevin S Donnelly, Jared L Zerbe. "United States Patent 10,366,045 Flash controller to provide a value that represents a parameter to a flash memory Inventors", Rambus Inc, Jul 30, 2019
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Noy Cohen, Marc S Levoy, Michael J Broxton, Logan Grosenick, Samuel Yang, Aaron Andalman, Karl A Disseroth, Mark A Horowitz. "United States Patent 10,317,597 Light-field microscopy with phase masking", Leland Stanford Junior University, Jun 11, 2019
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Jared LeVan Zerbe, Kevin S Donnelly, Stefanos Sidiropoulos, Donald C Stark, Mark A Horowitz, Leung Yu, Roxanne Vu, Jun Kim, Bruno W Garlepp, Tsyr-Chyang Ho, Benedict Chung-Kwong Lau. "United States Patent 10,310,999 Flash memory controller with calibrated data communication", Rambus Inc, Jun 4, 2019
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Jared L Zerbe, Bruno W Garlepp, Pak S Chau, Kevin S Donnelly, Mark A Horowitz, Stefanos Sidiropoulos, Billy W Garrett Jr, Carl W Werner. "United States Patent 9,998,305 Multi-PAM output driver with distortion compensation", Rambus Inc, Jun 12, 2018
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Haw-Jyh Liaw, Xingchao Yuan, Mark A Horowitz. "United States Patent 9,977,076 Technique for determining performance characteristics of electronic devices and systems", Rambus Inc, May 22, 2018
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Vladimir M Stojanovic, Andrew C Ho, Anthony Bessios, Bruno W Garlepp, Grace Tsang, Mark A Horowitz, Jared L Zerbe, Jason C Wei. "United States Patent 9,917,708 Partial response receiver", Rambus Inc, Mar 6, 2018
2024-25 Courses
- An Intro to Making: What is EE
ENGR 40M (Aut) - Digital Systems Engineering
EE 273 (Spr) -
Independent Studies (19)
- Advanced Reading and Research
CS 499 (Aut, Win, Spr, Sum) - Advanced Reading and Research
CS 499P (Aut, Win, Spr, Sum) - Curricular Practical Training
CS 390A (Aut, Win, Spr, Sum) - Curricular Practical Training
CS 390B (Aut, Win, Spr, Sum) - Curricular Practical Training
CS 390C (Aut, Win, Spr, Sum) - Independent Project
CS 399 (Aut, Win, Spr, Sum) - Independent Project
CS 399P (Aut, Win, Spr, Sum) - Independent Work
CS 199 (Aut, Win, Spr, Sum) - Independent Work
CS 199P (Aut, Win, Spr, Sum) - Master's Thesis and Thesis Research
EE 300 (Aut, Win, Spr, Sum) - Part-time Curricular Practical Training
CS 390D (Aut, Win, Spr, Sum) - Programming Service Project
CS 192 (Aut, Win, Spr, Sum) - Senior Project
CS 191 (Aut, Win, Spr, Sum) - Special Studies and Reports in Electrical Engineering
EE 191 (Aut, Win, Spr, Sum) - Special Studies and Reports in Electrical Engineering
EE 391 (Aut, Win, Spr, Sum) - Special Studies and Reports in Electrical Engineering (WIM)
EE 191W (Aut, Win, Spr, Sum) - Special Studies or Projects in Electrical Engineering
EE 190 (Aut, Win, Spr, Sum) - Special Studies or Projects in Electrical Engineering
EE 390 (Aut, Win, Spr, Sum) - Writing Intensive Senior Research Project
CS 191W (Aut, Win, Spr)
- Advanced Reading and Research
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Prior Year Courses
2023-24 Courses
- An Intro to Making: What is EE
ENGR 40M (Aut, Win)
2021-22 Courses
- An Intro to Making: What is EE
ENGR 40M (Aut, Win) - An Intro to Making: What is EE
OSPBER 40M (Aut, Win) - Digital Systems Engineering
EE 273 (Win)
- An Intro to Making: What is EE
Stanford Advisees
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Doctoral Dissertation Reader (AC)
Po-Han Chen, Timothy Chong, Kathleen Feng, Kalhan Koul, Aya Mouallem, Akshat Nigam, Nikhil Poole, Kartik Prabhu, Taha Rajabzadeh, Raj Setaluri, Ritvik Sharma, Lenny Truong -
Doctoral Dissertation Advisor (AC)
Nikhil Bhagdikar, Alex Carsello, Taeyoung Kong, Zachary Myers, Gedeon Nyengele, Kavya Sreedhar, Maxwell Strange, Sunil Sudhakaran, Victor Turbiner, Can WANG -
Orals Evaluator
Lenny Truong -
Master's Program Advisor
Alex Hodges, Marc Huerta, Atindra Jha, Andy Liang -
Doctoral (Program)
Nikhil Bhagdikar, Alex Carsello, Brandon D'Agostino, Zachary Myers, Kavya Sreedhar, Sunil Sudhakaran, Can WANG
All Publications
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Amber: A 16-nm System-on-Chip With a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra
IEEE JOURNAL OF SOLID-STATE CIRCUITS
2023
View details for DOI 10.1109/JSSC.2023.3313116
View details for Web of Science ID 001078350700001
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Unified Buffer: Compiling Image Processing and Machine Learning Applications to Push-Memory Accelerators
ACM Transactions on Architecture and Code Optimization
2023: 26
View details for DOI 10.1145/3572908
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Hardware Abstractions and Hardware Mechanisms to Support Multi-Task Execution on Coarse-Grained Reconfigurable Arrays
arXiv
2023
View details for DOI 10.48550/arXiv.2301.00861
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Canal: A Flexible Interconnect Generator for Coarse-Grained Reconfigurable Arrays
IEEE Computer Architecture Letters
2023
View details for DOI 10.1109/LCA.2023.3268126
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APEX: A Framework for Automated Processing Element Design Space Exploration using Frequent Subgraph Analysis
ASPLOS 2023: Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems
2023
View details for DOI 10.1145/3582016.3582070
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AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers
ACM Transactions on Embedded Computing Systems
2023; 22 (2)
View details for DOI 10.1145/3534933
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Higher education's influence on social networks and entrepreneurship in Brazil
SOCIAL NETWORK ANALYSIS AND MINING
2022; 13 (1)
View details for DOI 10.1007/s13278-022-01011-6
View details for Web of Science ID 000895420800001
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An Open-Source Framework for FPGA Emulation of Analog/Mixed-Signal Integrated Circuit Designs
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
2022; 41 (7): 2223-2236
View details for DOI 10.1109/TCAD.2021.3102516
View details for Web of Science ID 000812532700023
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Improving Energy Efficiency of CGRAs with Low-Overhead Fine-Grained Power Domains
ACM Transactions on Reconfigurable Technology and Systems
2022
View details for DOI 10.1145/3558394
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Enabling and Accelerating Dynamic Vision Transformer Inference for Real-Time Applications
arXiv
2022
View details for DOI 10.48550/arXiv.2212.02687
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Cascade: An Application Pipelining Toolkit for Coarse-Grained Reconfigurable Arrays
arXiv
2022
View details for DOI 10.48550/arXiv.2211.13182
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The Sparse Abstract Machine
arXiv
2022
View details for DOI 10.48550/arXiv.2208.14610
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Amber: Coarse-Grained Reconfigurable Array-Based SoC for Dense Linear Algebra Acceleration
2022 IEEE Hot Chips 34 Symposium (HCS)
2022: 1-30
View details for DOI 10.1109/HCS55958.2022.9895616
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mflowgen: a modular flow generator and ecosystem for community-driven physical design
DAC '22: Proceedings of the 59th ACM/IEEE Design Automation Conference
2022: 1339–1342
View details for DOI 10.1145/3489517.3530633
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Bringing source-level debugging frameworks to hardware generators
DAC '22: Proceedings of the 59th ACM/IEEE Design Automation Conference
2022: 1171–1176
View details for DOI 10.1145/3489517.3530603
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Amber: A 367 GOPS, 538 GOPS/W 16nm SoC with a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
2022
View details for DOI 10.1109/VLSITechnologyandCir46769.2022.9830509
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Automating System Configuration
CONFERENCE ON FORMAL METHODS IN COMPUTER-AIDED DESIGN–FMCAD 2021
2021
View details for DOI 10.48550/arXiv.2108.05987
- Compiling Halide Programs to Push-Memory Accelerators arXiv.org (https://arxiv.org/abs/2105.12858) 2021
- Automated Design Space Exploration of CGRA Processing Element Architectures using Frequent Subgraph Analysis arXiv.org (https://arxiv.org/abs/2104.14155) 2021
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A Fast Large-Integer Extended GCD Algorithm and Hardware Design for Verifiable Delay Functions and Modular Inversion
Cryptology ePrint Archive
2021
View details for DOI 10.46586/tches.v2022.i4.163-187
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Enabling Reusable Physical Design Flows with Modular Flow Generators
arXiv.org
2021
View details for DOI 10.48550/arXiv.2111.14535
- Online, Interactive Tool for Studying How Students Troubleshoot Circuits 2021 ASEE Virtual Annual Conference 2021
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Fast Validation of Mixed-Signal SoCs
IEEE Open Journal of the Solid-State Circuits Society
2021; 1: 184 - 195
View details for DOI 10.1109/OJSSCS.2021.3122397
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fault: A Python Embedded Domain-Specific Language for Metaprogramming Portable Hardware Verification Components
International Conference on Computer Aided Verification
2020
View details for DOI 10.1007/978-3-030-53288-8_19
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Interstellar: Using Halide's Scheduling Language to Analyze DNN Accelerators
ASSOC COMPUTING MACHINERY. 2020: 369–83
View details for DOI 10.1145/3373376.3378514
View details for Web of Science ID 000541369300024
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20-GS/s 8-bit Analog-to-Digital Converter and 5-GHz Phase Interpolator for Open-Source Synthesizable High-Speed Link Applications
IEEE Solid-State Circuits Letters
2020; 3: 518 - 521
View details for DOI 10.1109/LSSC.2020.3037823
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SegAlign: A Scalable GPU-Based Whole Genome Aligner
International Conference for High Performance Computing, Networking, Storage and Analysis (SC)
2020: 540–552
View details for DOI 10.1109/SC41405.2020.00043
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Creating an Agile Hardware Design Flow
2020 57th ACM/IEEE Design Automation Conference (DAC)
2020
View details for DOI 10.1109/DAC18072.2020.9218553
- A Framework for Adding Low-Overhead, Fine-Grained Power Domains to CGRAs Design, Automation and Test in Europe Conference (DATE). 2020
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Open-Source Synthesizable Analog Blocks for High-Speed Link Designs: 20-GS/s 5b ENOB Analog-to-Digital Converter and 5-GHz Phase Interpolator
2020 IEEE Symposium on VLSI Circuits
2020
View details for DOI 10.1109/VLSICircuits18222.2020.9162800
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An Analog Model Template Library: Simplifying Chip-Level, Mixed-Signal Design Verification
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
2019; 27 (1): 193–204
View details for DOI 10.1109/TVLSI.2018.2873387
View details for Web of Science ID 000455117600019
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DATASET CULLING: TOWARDS EFFICIENT TRAINING OF DISTILLATION-BASED DOMAIN SPECIFIC MODELS
IEEE. 2019: 3237–41
View details for Web of Science ID 000521828603075
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Superconducting Quantum Computers
QUANTUM COMPUTING: PROGRESS AND PROSPECTS
2019: 205–11
View details for Web of Science ID 000574896500012
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Quantum Computing's Implications for Cryptography
QUANTUM COMPUTING: PROGRESS AND PROSPECTS
2019: 95–112
View details for Web of Science ID 000574896500006
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Quantum Algorithms and Applications
QUANTUM COMPUTING: PROGRESS AND PROSPECTS
2019: 57–94
View details for Web of Science ID 000574896500005
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QUANTUM COMPUTING Progress and Prospects Summary
QUANTUM COMPUTING: PROGRESS AND PROSPECTS
2019: 1–11
View details for Web of Science ID 000574896500002
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Other Approaches to Building Qubits
QUANTUM COMPUTING: PROGRESS AND PROSPECTS
2019: 212–25
View details for Web of Science ID 000574896500013
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Statement of Task
QUANTUM COMPUTING: PROGRESS AND PROSPECTS
2019: 195
View details for Web of Science ID 000574896500010
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Essential Hardware Components of a Quantum Computer
QUANTUM COMPUTING: PROGRESS AND PROSPECTS
2019: 113–34
View details for Web of Science ID 000574896500007
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Essential Software Components of a Scalable Quantum Computer
QUANTUM COMPUTING: PROGRESS AND PROSPECTS
2019: 135–55
View details for Web of Science ID 000574896500008
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Global R&D Investment
QUANTUM COMPUTING: PROGRESS AND PROSPECTS
2019: 226–29
View details for Web of Science ID 000574896500014
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Quantum Computing: A New Paradigm
QUANTUM COMPUTING: PROGRESS AND PROSPECTS
2019: 24–56
View details for Web of Science ID 000574896500004
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Falcon — A Flexible Architecture For Accelerating Cryptography
2019 IEEE 16th International Conference on Mobile Ad Hoc and Sensor Systems (MASS)
2019
View details for DOI 10.1109/MASS.2019.00025
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TANGRAM: Optimized Coarse-Grained Dataflow for Scalable NN Accelerators
ASPLOS '19: Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems
2019: 807–20
View details for DOI 10.1145/3297858.3304014
- StartupBR: Higher Education's Influence on Social Networks and Entrepreneurship in Brazil arXiv:1904.12026 2019
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Trapped Ion Quantum Computers
QUANTUM COMPUTING: PROGRESS AND PROSPECTS
2019: 196–204
View details for Web of Science ID 000574896500011
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Feasibility and Time Frames of Quantum Computing
QUANTUM COMPUTING: PROGRESS AND PROSPECTS
2019: 156–92
View details for Web of Science ID 000574896500009
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Progress in Computing
QUANTUM COMPUTING: PROGRESS AND PROSPECTS
2019: 12–23
View details for Web of Science ID 000574896500003
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QUANTUM COMPUTING Progress and Prospects Preface
QUANTUM COMPUTING: PROGRESS AND PROSPECTS
2019: XI-XV
View details for Web of Science ID 000574896500001
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Mapping Histological Slice Sequences to the Allen Mouse Brain Atlas Without 3D Reconstruction.
Frontiers in neuroinformatics
2018; 12: 93
Abstract
Histological brain slices are widely used in neuroscience to study the anatomical organization of neural circuits. Systematic and accurate comparisons of anatomical data from multiple brains, especially from different studies, can benefit tremendously from registering histological slices onto a common reference atlas. Most existing methods rely on an initial reconstruction of the volume before registering it to a reference atlas. Because these slices are prone to distortions during the sectioning process and often sectioned with non-standard angles, reconstruction is challenging and often inaccurate. Here we describe a framework that maps each slice to its corresponding plane in the Allen Mouse Brain Atlas (2015) to build a plane-wise mapping and then perform 2D nonrigid registration to build a pixel-wise mapping. We use the L2 norm of the histogram of oriented gradients difference of two patches as the similarity metric for both steps and a Markov random field formulation that incorporates tissue coherency to compute the nonrigid registration. To fix significantly distorted regions that are misshaped or much smaller than the control grids, we train a context-aggregation network to segment and warp them to their corresponding regions with thin plate spline. We have shown that our method generates results comparable to an expert neuroscientist and is significantly better than reconstruction-first approaches. Code and sample dataset are available at sites.google.com/view/brain-mapping.
View details for DOI 10.3389/fninf.2018.00093
View details for PubMedID 30618698
View details for PubMedCentralID PMC6297281
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Mapping Histological Slice Sequences to the Allen Mouse Brain Atlas Without 3D Reconstruction
FRONTIERS IN NEUROINFORMATICS
2018; 12
View details for DOI 10.3389/fninf.2018.00093
View details for Web of Science ID 000452913600001
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Anatomically Defined and Functionally Distinct Dorsal Raphe Serotonin Sub-systems
CELL
2018; 175 (2): 472-+
View details for DOI 10.1016/j.cell.2018.07.043
View details for Web of Science ID 000446321300018
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The Interaction Engine
DESIGN THINKING RESEARCH: MAKING DISTINCTIONS: COLLABORATION VERSUS COOPERATION
2018: 147–69
View details for DOI 10.1007/978-3-319-60967-6_8
View details for Web of Science ID 000432741300009
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Tethys: Collecting Sensor Data without Infrastracture or Trust
2018 IEEE/ACM Third International Conference on Internet-of-Things Design and Implementation (IoTDI)
2018: 249–54
View details for DOI 10.1109/IoTDI.2018.00032
- Rethinking Non-major Circuits Pedagogy for Improved Motivation 2018 ASEE Annual Conference & Exposition (https://peer.asee.org/30936). 2018
- DNN Dataflow Choice Is Overrated arXiv:1809.04070 2018
- Training Domain Specific Models for Energy-Efficient Object Detection arXiv:1811.02689 2018
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Mapping Mouse Brain Slice Sequence to a Reference Brain Without 3D Reconstruction
bioRxiv
2018
View details for DOI 10.1101/357475
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Fast FPGA Emulation of Analog Dynamics in Digitally-Driven Systems
ASSOC COMPUTING MACHINERY. 2018
View details for DOI 10.1145/3240765.3240808
View details for Web of Science ID 000494640800129
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Compiling Algorithms for Heterogeneous Systems
Synthesis Lectures on Computer Architecture
2018: 105
View details for DOI 10.2200/S00816ED1V01Y201711CAC043
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Anatomically Defined and Functionally Distinct Dorsal Raphe Serotonin Sub-systems.
Cell
2018
Abstract
The dorsal raphe (DR) constitutes a major serotonergic input to the forebrain and modulates diverse functions and brain states, including mood, anxiety, and sensory and motor functions. Most functional studies to date have treated DR serotonin neurons as a single population. Using viral-genetic methods, we found that subcortical- and cortical-projecting serotonin neurons have distinct cell-body distributions within the DR and differentially co-express a vesicular glutamate transporter. Further, amygdala- and frontal-cortex-projecting DR serotonin neurons have largely complementary whole-brain collateralization patterns, receive biased inputs from presynaptic partners, and exhibit opposite responses to aversive stimuli. Gain- and loss-of-function experiments suggest that amygdala-projecting DR serotonin neurons promote anxiety-like behavior, whereas frontal-cortex-projecting neurons promote active coping in the face of challenge. These results provide compelling evidence that the DR serotonin system contains parallel sub-systems that differ in input and output connectivity, physiological response properties, and behavioral functions.
View details for PubMedID 30146164
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Volumetric Image Registration From Invariant Keypoints
IEEE TRANSACTIONS ON IMAGE PROCESSING
2017; 26 (10): 4900–4910
Abstract
We present a method for image registration based on 3D scale- and rotation-invariant keypoints. The method extends the scale invariant feature transform (SIFT) to arbitrary dimensions by making key modifications to orientation assignment and gradient histograms. Rotation invariance is proven mathematically. Additional modifications are made to extrema detection and keypoint matching based on the demands of image registration. Our experiments suggest that the choice of neighborhood in discrete extrema detection has a strong impact on image registration accuracy. In head MR images, the brain is registered to a labeled atlas with an average Dice coefficient of 92%, outperforming registration from mutual information as well as an existing 3D SIFT implementation. In abdominal CT images, the spine is registered with an average error of 4.82 mm. Furthermore, keypoints are matched with high precision in simulated head MR images exhibiting lesions from multiple sclerosis. These results were achieved using only affine transforms, and with no change in parameters across a wide variety of medical images. This paper is freely available as a cross-platform software library.
View details for DOI 10.1109/TIP.2017.2722689
View details for Web of Science ID 000406329500024
View details for PubMedID 28682256
View details for PubMedCentralID PMC5581541
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Scalable Device for Automated Microbial Electroporation in a Digital Microfluidic Platform.
ACS synthetic biology
2017; 6 (9): 1701-1709
Abstract
Electrowetting-on-dielectric (EWD) digital microfluidic laboratory-on-a-chip platforms demonstrate excellent performance in automating labor-intensive protocols. When coupled with an on-chip electroporation capability, these systems hold promise for streamlining cumbersome processes such as multiplex automated genome engineering (MAGE). We integrated a single Ti:Au electroporation electrode into an otherwise standard parallel-plate EWD geometry to enable high-efficiency transformation of Escherichia coli with reporter plasmid DNA in a 200 nL droplet. Test devices exhibited robust operation with more than 10 transformation experiments performed per device without cross-contamination or failure. Despite intrinsic electric-field nonuniformity present in the EP/EWD device, the peak on-chip transformation efficiency was measured to be 8.6 ± 1.0 × 108 cfu·μg-1 for an average applied electric field strength of 2.25 ± 0.50 kV·mm-1. Cell survival and transformation fractions at this electroporation pulse strength were found to be 1.5 ± 0.3 and 2.3 ± 0.1%, respectively. Our work expands the EWD toolkit to include on-chip microbial electroporation and opens the possibility of scaling advanced genome engineering methods, like MAGE, into the submicroliter regime.
View details for DOI 10.1021/acssynbio.7b00007
View details for PubMedID 28569062
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Programming Heterogeneous Systems from an Image Processing DSL
ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION
2017; 14 (3)
View details for DOI 10.1145/3107953
View details for Web of Science ID 000423744000006
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Dynamic structure of locomotor behavior in walking fruit flies
ELIFE
2017; 6
Abstract
The function of the brain is unlikely to be understood without an accurate description of its output, yet the nature of movement elements and their organization remains an open problem. Here, movement elements are identified from dynamics of walking in flies, using unbiased criteria. On one time scale, dynamics of walking are consistent over hundreds of milliseconds, allowing elementary features to be defined. Over longer periods, walking is well described by a stochastic process composed of these elementary features, and a generative model of this process reproduces individual behavior sequences accurately over seconds or longer. Within elementary features, velocities diverge, suggesting that dynamical stability of movement elements is a weak behavioral constraint. Rather, long-term instability can be limited by the finite memory between these elementary features. This structure suggests how complex dynamics may arise in biological systems from elements whose combination need not be tuned for dynamic stability.
View details for PubMedID 28742018
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Microfluidic-based mini-metagenomics enables discovery of novel microbial lineages from complex environmental samples
ELIFE
2017; 6
Abstract
Metagenomics and single-cell genomics have enabled genome discovery from unknown branches of life. However, extracting novel genomes from complex mixtures of metagenomic data can still be challenging and represents an ill-posed problem which is generally approached with ad hoc methods. Here we present a microfluidic-based mini-metagenomic method which offers a statistically rigorous approach to extract novel microbial genomes while preserving single-cell resolution. We used this approach to analyze two hot spring samples from Yellowstone National Park and extracted 29 new genomes, including three deeply branching lineages. The single-cell resolution enabled accurate quantification of genome function and abundance, down to 1% in relative abundance. Our analyses of genome level SNP distributions also revealed low to moderate environmental selection. The scale, resolution, and statistical power of microfluidic-based mini-metagenomics make it a powerful tool to dissect the genomic structure of microbial communities while effectively preserving the fundamental unit of biology, the single cell.
View details for PubMedID 28678007
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Local inhibition of microtubule dynamics by dynein is required for neuronal cargo distribution
NATURE COMMUNICATIONS
2017; 8
Abstract
Abnormal axonal transport is associated with neuronal disease. We identified a role for DHC-1, the C. elegans dynein heavy chain, in maintaining neuronal cargo distribution. Surprisingly, this does not involve dynein's role as a retrograde motor in cargo transport, hinging instead on its ability to inhibit microtubule (MT) dynamics. Neuronal MTs are highly static, yet the mechanisms and functional significance of this property are not well understood. In disease-mimicking dhc-1 alleles, excessive MT growth and collapse occur at the dendrite tip, resulting in the formation of aberrant MT loops. These unstable MTs act as cargo traps, leading to ectopic accumulations of cargo and reduced availability of cargo at normal locations. Our data suggest that an anchored dynein pool interacts with plus-end-out MTs to stabilize MTs and allow efficient retrograde transport. These results identify functional significance for neuronal MT stability and suggest a mechanism for cellular dysfunction in dynein-linked disease.
View details for DOI 10.1038/ncomms15063
View details for Web of Science ID 000399053800001
View details for PubMedID 28406181
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Dark Memory and Accelerator-Rich System Optimization in the Dark Silicon Era
IEEE DESIGN & TEST
2017; 34 (2): 39-50
View details for DOI 10.1109/MDAT.2016.2573586
View details for Web of Science ID 000396240300006
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TETRIS: Scalable and Efficient Neural Network Acceleration with 3D Memory
ASSOC COMPUTING MACHINERY. 2017: 751-764
View details for DOI 10.1145/3093336.3037702
View details for Web of Science ID 000408313700053
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TETRIS: Scalable and Efficient Neural Network Acceleration with 3D Memory
ACM SIGPLAN NOTICES
2017; 52 (4): 751-764
View details for DOI 10.1145/3037697.3037702
View details for Web of Science ID 000401540000053
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Long-term microfluidic tracking of coccoid cyanobacterial cells reveals robust control of division timing
BMC BIOLOGY
2017; 15
Abstract
Cyanobacteria are important agents in global carbon and nitrogen cycling and hold great promise for biotechnological applications. Model organisms such as Synechocystis sp. and Synechococcus sp. have advanced our understanding of photosynthetic capacity and circadian behavior, mostly using population-level measurements in which the behavior of individuals cannot be monitored. Synechocystis sp. cells are small and divide slowly, requiring long-term experiments to track single cells. Thus, the cumulative effects of drift over long periods can cause difficulties in monitoring and quantifying cell growth and division dynamics.To overcome this challenge, we enhanced a microfluidic cell-culture device and developed an image analysis pipeline for robust lineage reconstruction. This allowed simultaneous tracking of many cells over multiple generations, and revealed that cells expand exponentially throughout their cell cycle. Generation times were highly correlated for sister cells, but not between mother and daughter cells. Relationships between birth size, division size, and generation time indicated that cell-size control was inconsistent with the "sizer" rule, where division timing is based on cell size, or the "timer" rule, where division occurs after a fixed time interval. Instead, single cell growth statistics were most consistent with the "adder" rule, in which division occurs after a constant increment in cell volume. Cells exposed to light-dark cycles exhibited growth and division only during the light period; dark phases pause but do not disrupt cell-cycle control.Our analyses revealed that the "adder" model can explain both the growth-related statistics of single Synechocystis cells and the correlation between sister cell generation times. We also observed rapid phenotypic response to light-dark transitions at the single cell level, highlighting the critical role of light in cyanobacterial cell-cycle control. Our findings suggest that by monitoring the growth kinetics of individual cells we can build testable models of circadian control of the cell cycle in cyanobacteria.
View details for DOI 10.1186/s12915-016-0344-4
View details for Web of Science ID 000394057800001
View details for PubMedID 28196492
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Microtubule Organization Determines Axonal Transport Dynamics.
Neuron
2016; 92 (2): 449-460
Abstract
Axonal microtubule (MT) arrays are the major cytoskeleton substrate for cargo transport. How MT organization, i.e., polymer length, number, and minus-end spacing, is regulated and how it impinges on axonal transport are unclear. We describe a method for analyzing neuronal MT organization using light microscopy. This method circumvents the need for electron microscopy reconstructions and is compatible with live imaging of cargo transport and MT dynamics. Examination of a C. elegans motor neuron revealed how age, MT-associated proteins, and signaling pathways control MT length, minus-end spacing, and coverage. In turn, MT organization determines axonal transport progression: cargoes pause at polymer termini, suggesting that switching MT tracks is rate limiting for efficient transport. Cargo run length is set by MT length, and higher MT coverage correlates with shorter pauses. These results uncover the principles and mechanisms of neuronal MT organization and its regulation of axonal cargo transport.
View details for DOI 10.1016/j.neuron.2016.09.036
View details for PubMedID 27764672
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Rigel: Flexible Multi-Rate Image Processing Hardware
ACM TRANSACTIONS ON GRAPHICS
2016; 35 (4)
View details for DOI 10.1145/2897824.2925892
View details for Web of Science ID 000380112400055
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Tomographic Reconstruction and Alignment Using Matrix Norm Minimization
IEEE JOURNAL OF SELECTED TOPICS IN SIGNAL PROCESSING
2016; 10 (1): 47-60
View details for DOI 10.1109/JSTSP.2015.2510163
View details for Web of Science ID 000369495900004
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Evaluating Programmable Architectures for Imaging and Vision Applications
IEEE. 2016
View details for Web of Science ID 000391364100052
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A 220pJ/Pixel/Frame CMOS Image Sensor with Partial Settling Readout Architecture
IEEE. 2016
View details for Web of Science ID 000392504700088
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EIE: Efficient Inference Engine on Compressed Deep Neural Network
IEEE. 2016: 243-254
View details for DOI 10.1109/ISCA.2016.30
View details for Web of Science ID 000389548600020
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Deep Compression and EIE: Efficient Inference Engine on Compressed Deep Neural Network
IEEE. 2016
View details for Web of Science ID 000405553300037
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Improving Energy Efficiency of DRAM by Exploiting Half Page Row Access
IEEE. 2016
View details for Web of Science ID 000391364100027
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Error Control and Limit Cycle Elimination in Event-Driven Piecewise Linear Analog Functional Models
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
2016; 63 (1): 23-33
View details for DOI 10.1109/TCSI.2015.2512699
View details for Web of Science ID 000372001500003
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Convolution Engine: Balancing Efficiency and Flexibility in Specialized Computing
COMMUNICATIONS OF THE ACM
2015; 58 (4): 85-93
View details for DOI 10.1145/2735841
View details for Web of Science ID 000351734500024
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Building Conflict-Free FFT Schedules
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
2015; 62 (4): 1146-1155
View details for DOI 10.1109/TCSI.2015.2402935
View details for Web of Science ID 000352288800024
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Digital Analog Design: Enabling Mixed-Signal System Validation
IEEE DESIGN & TEST
2015; 32 (1): 44-52
View details for DOI 10.1109/MDAT.2014.2361718
View details for Web of Science ID 000348097200007
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Demo Abstract: Tethys - An Energy Harvesting Networked Water Flow Sensor
ASSOC COMPUTING MACHINERY. 2015: 489-490
View details for DOI 10.1145/2809695.2817868
View details for Web of Science ID 000380612400085
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SCALE- AND ORIENTATION-INVARIANT KEYPOINTS IN HIGHER-DIMENSIONAL DATA
IEEE. 2015: 3490-3494
View details for Web of Science ID 000371977803125
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Enhancing the performance of the light field microscope using wavefront coding
OPTICS EXPRESS
2014; 22 (20): 24817-24839
Abstract
Light field microscopy has been proposed as a new high-speed volumetric computational imaging method that enables reconstruction of 3-D volumes from captured projections of the 4-D light field. Recently, a detailed physical optics model of the light field microscope has been derived, which led to the development of a deconvolution algorithm that reconstructs 3-D volumes with high spatial resolution. However, the spatial resolution of the reconstructions has been shown to be non-uniform across depth, with some z planes showing high resolution and others, particularly at the center of the imaged volume, showing very low resolution. In this paper, we enhance the performance of the light field microscope using wavefront coding techniques. By including phase masks in the optical path of the microscope we are able to address this non-uniform resolution limitation. We have also found that superior control over the performance of the light field microscope can be achieved by using two phase masks rather than one, placed at the objective's back focal plane and at the microscope's native image plane. We present an extended optical model for our wavefront coded light field microscope and develop a performance metric based on Fisher information, which we use to choose adequate phase masks parameters. We validate our approach using both simulated data and experimental resolution measurements of a USAF 1951 resolution target; and demonstrate the utility for biological applications with in vivo volumetric calcium imaging of larval zebrafish brain.
View details for DOI 10.1364/OE.22.024817
View details for Web of Science ID 000342757000104
View details for PubMedCentralID PMC4247191
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A Verilog Piecewise-Linear Analog Behavior Model for Mixed-Signal Validation
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
2014; 61 (8): 2229-2235
View details for DOI 10.1109/TCSI.2014.2332265
View details for Web of Science ID 000341593000003
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Darkroom: Compiling High-Level Image Processing Code into Hardware Pipelines
ACM TRANSACTIONS ON GRAPHICS
2014; 33 (4)
View details for DOI 10.1145/2601097.2601174
View details for Web of Science ID 000340000100111
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Large-scale mapping of transposable element insertion sites using digital encoding of sample identity.
Genetics
2014; 196 (3): 615-623
Abstract
Determining the genomic locations of transposable elements is a common experimental goal. When mapping large collections of transposon insertions, individualized amplification and sequencing is both time consuming and costly. We describe an approach in which large numbers of insertion lines can be simultaneously mapped in a single DNA sequencing reaction by using digital error-correcting codes to encode line identity in a unique set of barcoded pools.
View details for DOI 10.1534/genetics.113.159483
View details for PubMedID 24374352
View details for PubMedCentralID PMC3948795
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Large-scale mapping of transposable element insertion sites using digital encoding of sample identity.
Genetics
2014; 196 (3): 615-623
Abstract
Determining the genomic locations of transposable elements is a common experimental goal. When mapping large collections of transposon insertions, individualized amplification and sequencing is both time consuming and costly. We describe an approach in which large numbers of insertion lines can be simultaneously mapped in a single DNA sequencing reaction by using digital error-correcting codes to encode line identity in a unique set of barcoded pools.
View details for DOI 10.1534/genetics.113.159483
View details for PubMedID 24374352
View details for PubMedCentralID PMC3948795
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Computing's Energy Problem (and what we can do about it)
IEEE. 2014: 10-14
View details for DOI 10.1109/isscc.2014.6757323
View details for Web of Science ID 000353615000001
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Forwarding Metamorphosis: Fast Programmable Match-Action Processing in Hardware for SDN
SIGCOMM Conference
ASSOC COMPUTING MACHINERY. 2013: 99–110
View details for DOI 10.1145/2534169.2486011
View details for Web of Science ID 000327465900016
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GABAergic Lateral Interactions Tune the Early Stages of Visual Processing in Drosophila
NEURON
2013; 78 (6): 1075-1089
Abstract
Early stages of visual processing must capture complex, dynamic inputs. While peripheral neurons often implement efficient encoding by exploiting natural stimulus statistics, downstream neurons are specialized to extract behaviorally relevant features. How do these specializations arise? We use two-photon imaging in Drosophila to characterize a first-order interneuron, L2, that provides input to a pathway specialized for detecting moving dark edges. GABAergic interactions, mediated in part presynaptically, create an antagonistic and anisotropic center-surround receptive field. This receptive field is spatiotemporally coupled, applying differential temporal processing to large and small dark objects, achieving significant specialization. GABAergic circuits also mediate OFF responses and balance these with responses to ON stimuli. Remarkably, the functional properties of L2 are strikingly similar to those of bipolar cells, yet emerge through different molecular and circuit mechanisms. Thus, evolution appears to have converged on a common strategy for processing visual information at the first synapse.
View details for DOI 10.1016/j.neuron.2013.04.024
View details for Web of Science ID 000321026900013
View details for PubMedID 23791198
View details for PubMedCentralID PMC3694283
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Microfluidic serial digital to analog pressure converter for arbitrary pressure generation and contamination-free flow control
LAB ON A CHIP
2013; 13 (10): 1911-1918
Abstract
Multilayer microfluidics based on PDMS (polydimethylsiloxane) soft lithography have offered parallelism and integration for biological and chemical sciences, where reduction in reaction volume and consistency of controlled variables across experiments translate into reduced cost, increased quantity and quality of data. One issue with push up or push down microfluidic control concept is the inability to provide multiple control pressures without adding more complex and expensive external pressure controls. We present here a microfluidic serial DAC (Digital to Analog Converter) that can be integrated with any PDMS device to expand the device's functionality by effectively adding an on-chip pressure regulator. The microfluidic serial DAC can be used with any incompressible fluids and operates in a similar fashion compared to an electronic serial DAC. It can be easily incorporated into any existing multilayer microfluidic devices, and the output pressure that the device generates could be held for extensive times. We explore in this paper various factors that affect resolution, speed, and linearity of the DAC output. As an application, we demonstrate microfluidic DAC's ability for on-chip manipulation of flow resistance when integrated with a simple flow network. In addition, we illustrate an added advantage of using the microfluidic serial DAC in preventing back flow and possible contamination.
View details for DOI 10.1039/c3lc41394b
View details for Web of Science ID 000317937300011
View details for PubMedID 23529280
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A Verilog Piecewise-Linear Analog Behavior Model for Mixed-Signal Validation
35th Annual IEEE Custom Integrated Circuits Conference (CICC) - The Showcase for Circuit Design in the Heart of Silicon Valley
IEEE. 2013
View details for Web of Science ID 000350887800060
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Design Principles for Packet Parsers
9th ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS)
IEEE. 2013: 13–24
View details for Web of Science ID 000345909600002
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An Area-Efficient Minimum-Time FFT Schedule Using Single-Ported Memory
IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)
IEEE. 2013: 39–44
View details for Web of Science ID 000332046100008
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FPU Generator for Design Space Exploration
21st IEEE Symposium on Computer Arithmetic (ARITH)
IEEE. 2013: 25–34
View details for DOI 10.1109/ARITH.2013.27
View details for Web of Science ID 000326337100004
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The Frankencamera: An Experimental Platform for Computational Photography
COMMUNICATIONS OF THE ACM
2012; 55 (11): 90-98
View details for DOI 10.1145/2366316.2366339
View details for Web of Science ID 000311293300029
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Bringing Up a Chip on the Cheap
IEEE DESIGN & TEST OF COMPUTERS
2012; 29 (6): 57-65
View details for DOI 10.1109/MDT.2011.2179849
View details for Web of Science ID 000318544300008
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Removing high contrast artifacts via digital inpainting in cryo-electron tomography: An application of compressed sensing
JOURNAL OF STRUCTURAL BIOLOGY
2012; 178 (2): 108-120
Abstract
To cope with poor quality in cryo-electron tomography images, electron-dense markers, such as colloidal goldbeads, are often used to assist image registration and analysis algorithms. However, these markers can create artifacts that occlude a specimen due to their high contrast, which can also cause failure of some image processing algorithms. One way of reducing these artifacts is to replace high contrast objects with pixel densities that blend into the surroundings in the projection domain before volume reconstruction. In this paper, we propose digital inpainting via compressed sensing (CS) as a new method to achieve this goal. We show that cryo-ET projections are sparse in the discrete cosine transform (DCT) domain, and, by finding the sparsest DCT domain decompositions given uncorrupted pixels, we can fill in the missing pixel values that are occluded by high contrast objects without discontinuities. Our method reduces visual artifacts both in projections and in tomograms better than conventional algorithms, such as polynomial interpolation and random noise inpainting.
View details for DOI 10.1016/j.jsb.2012.01.003
View details for Web of Science ID 000304287400006
View details for PubMedID 22248454
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CPU DB: Recording Microprocessor History
COMMUNICATIONS OF THE ACM
2012; 55 (4): 55-63
View details for DOI 10.1145/2133806.2133822
View details for Web of Science ID 000302915000023
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CMOS Image Sensors With Multi-Bucket Pixels for Computational Photography
IEEE JOURNAL OF SOLID-STATE CIRCUITS
2012; 47 (4): 1031-1042
View details for DOI 10.1109/JSSC.2012.2185189
View details for Web of Science ID 000302494700022
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Avoiding Game Over: Bringing Design to the Next Level
49th ACM/EDAC/IEEE Design Automation Conference (DAC)
IEEE. 2012: 623–629
View details for Web of Science ID 000309256800089
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A New IC with Level-Crossing ADC Readout Architecture for PET Detector Signals
IEEE Nuclear Science Symposium / Medical Imaging Conference Record (NSS/MIC) / 19th Room-Temperature Semiconductor X-ray and Gamma-ray Detector Workshop
IEEE. 2012: 2486–2488
View details for Web of Science ID 000326814202127
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Design Automation Framework for Application-Specific Logic-in-Memory Blocks
23rd IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP)
IEEE. 2012: 125–132
View details for Web of Science ID 000312737700018
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Rethinking DRAM Power Modes for Energy Proportionality
45th IEEE/ACM Annual International Symposium on Microarchitecture (MICRO)
IEEE COMPUTER SOC. 2012: 131–142
View details for DOI 10.1109/MICRO.2012.21
View details for Web of Science ID 000319333900012
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Removing Overhead From High-Level Interfaces
49th ACM/EDAC/IEEE Design Automation Conference (DAC)
IEEE. 2012: 783–789
View details for Web of Science ID 000309256800112
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Towards Energy-Proportional Datacenter Memory with Mobile DRAM
39th Annual International Symposium on Computer Architecture (ISCA)
IEEE. 2012: 37–48
View details for Web of Science ID 000309010000004
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Understanding Sources of Inefficiency in General-Purpose Chips
COMMUNICATIONS OF THE ACM
2011; 54 (10): 85-93
View details for DOI 10.1145/2001269.2001291
View details for Web of Science ID 000296022500021
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Energy-Efficient Floating-Point Unit Design
IEEE TRANSACTIONS ON COMPUTERS
2011; 60 (7): 913-922
View details for DOI 10.1109/TC.2010.121
View details for Web of Science ID 000290867300001
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Defining the Computational Structure of the Motion Detector in Drosophila
NEURON
2011; 70 (6): 1165-1177
Abstract
Many animals rely on visual motion detection for survival. Motion information is extracted from spatiotemporal intensity patterns on the retina, a paradigmatic neural computation. A phenomenological model, the Hassenstein-Reichardt correlator (HRC), relates visual inputs to neural activity and behavioral responses to motion, but the circuits that implement this computation remain unknown. By using cell-type specific genetic silencing, minimal motion stimuli, and in vivo calcium imaging, we examine two critical HRC inputs. These two pathways respond preferentially to light and dark moving edges. We demonstrate that these pathways perform overlapping but complementary subsets of the computations underlying the HRC. A numerical model implementing differential weighting of these operations displays the observed edge preferences. Intriguingly, these pathways are distinguished by their sensitivities to a stimulus correlation that corresponds to an illusory percept, "reverse phi," that affects many species. Thus, this computational architecture may be widely used to achieve edge selectivity in motion detection.
View details for DOI 10.1016/j.neuron.2011.05.023
View details for Web of Science ID 000292410700014
View details for PubMedID 21689602
View details for PubMedCentralID PMC3121538
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Cortical representations of olfactory input by trans-synaptic tracing
NATURE
2011; 472 (7342): 191-196
Abstract
In the mouse, each class of olfactory receptor neurons expressing a given odorant receptor has convergent axonal projections to two specific glomeruli in the olfactory bulb, thereby creating an odour map. However, it is unclear how this map is represented in the olfactory cortex. Here we combine rabies-virus-dependent retrograde mono-trans-synaptic labelling with genetics to control the location, number and type of 'starter' cortical neurons, from which we trace their presynaptic neurons. We find that individual cortical neurons receive input from multiple mitral cells representing broadly distributed glomeruli. Different cortical areas represent the olfactory bulb input differently. For example, the cortical amygdala preferentially receives dorsal olfactory bulb input, whereas the piriform cortex samples the whole olfactory bulb without obvious bias. These differences probably reflect different functions of these cortical areas in mediating innate odour preference or associative memory. The trans-synaptic labelling method described here should be widely applicable to mapping connections throughout the mouse nervous system.
View details for DOI 10.1038/nature09714
View details for Web of Science ID 000289469100036
View details for PubMedID 21179085
View details for PubMedCentralID PMC3073090
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Latency Sensitive FMA Design
20th IEEE Symposium on Computer Arithmetic (ARITH)
IEEE COMPUTER SOC. 2011: 129–138
View details for DOI 10.1109/ARITH.2011.26
View details for Web of Science ID 000296333300016
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Intermediate Representations for Controllers in Chip Generators
IEEE. 2011: 1394-1399
View details for Web of Science ID 000410278900265
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Joint DAC/IWBDA Special Session Design and Synthesis of Biological Circuits
48th ACM/IEEE/EDAC Design Automation Conference (DAC)
ASSOC COMPUTING MACHINERY. 2011: 114–115
View details for Web of Science ID 000297360000020
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Global Convergence Analysis of Mixed-Signal Systems
48th ACM/IEEE/EDAC Design Automation Conference (DAC)
ASSOC COMPUTING MACHINERY. 2011: 498–503
View details for Web of Science ID 000297360000093
- Global convergence analysis of mixed-signal systems Design Automation Conference (DAC) 2011: 498-503
- Energy-efficient floating point unit design Computers, IEEE Transactions on 2011; 99: 1-1
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Analog signal multiplexing for PSAPD-based PET detectors: simulation and experimental validation
PHYSICS IN MEDICINE AND BIOLOGY
2010; 55 (23): 7149-7174
Abstract
A 1 mm(3) resolution clinical positron emission tomography (PET) system employing 4608 position-sensitive avalanche photodiodes (PSAPDs) is under development. This paper describes a detector multiplexing technique that simplifies the readout electronics and reduces the density of the circuit board design. The multiplexing scheme was validated using a simulation framework that models the PSAPDs and front-end multiplexing circuits to predict the signal-to-noise ratio and flood histogram performance. Two independent experimental setups measured the energy resolution, time resolution, crystal identification ability and count rate both with and without multiplexing. With multiplexing, there was no significant degradation in energy resolution, time resolution and count rate. There was a relative 6.9 ± 1.0% and 9.4 ± 1.0% degradation in the figure of merit that characterizes the crystal identification ability observed in the measured and simulated ceramic-mounted PSAPD module flood histograms, respectively.
View details for DOI 10.1088/0031-9155/55/23/001
View details for Web of Science ID 000284261000015
View details for PubMedID 21081831
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Analysis of the Intact Surface Layer of Caulobacter crescentus by Cryo-Electron Tomography
JOURNAL OF BACTERIOLOGY
2010; 192 (22): 5855-5865
Abstract
The surface layers (S layers) of those bacteria and archaea that elaborate these crystalline structures have been studied for 40 years. However, most structural analysis has been based on electron microscopy of negatively stained S-layer fragments separated from cells, which can introduce staining artifacts and allow rearrangement of structures prone to self-assemble. We present a quantitative analysis of the structure and organization of the S layer on intact growing cells of the Gram-negative bacterium Caulobacter crescentus using cryo-electron tomography (CET) and statistical image processing. Instead of the expected long-range order, we observed different regions with hexagonally organized subunits exhibiting short-range order and a broad distribution of periodicities. Also, areas of stacked double layers were found, and these increased in extent when the S-layer protein (RsaA) expression level was elevated by addition of multiple rsaA copies. Finally, we combined high-resolution amino acid residue-specific Nanogold labeling and subtomogram averaging of CET volumes to improve our understanding of the correlation between the linear protein sequence and the structure at the 2-nm level of resolution that is presently available. The results support the view that the U-shaped RsaA monomer predicted from negative-stain tomography proceeds from the N terminus at one vertex, corresponding to the axis of 3-fold symmetry, to the C terminus at the opposite vertex, which forms the prominent 6-fold symmetry axis. Such information will help future efforts to analyze subunit interactions and guide selection of internal sites for display of heterologous protein segments.
View details for DOI 10.1128/JB.00747-10
View details for Web of Science ID 000283559300001
View details for PubMedID 20833802
View details for PubMedCentralID PMC2976456
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RETHINKING DIGITAL DESIGN: WHY DESIGN MUST CHANGE
IEEE MICRO
2010; 30 (6): 9-24
View details for Web of Science ID 000285609700003
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Subtomogram alignment by adaptive Fourier coefficient thresholding
JOURNAL OF STRUCTURAL BIOLOGY
2010; 171 (3): 332-344
Abstract
In the past few years, three-dimensional (3D) subtomogram alignment has become an important tool in cryo-electron tomography (CET). This technique allows one to produce higher resolution images of structures which can not be reconstructed using single-particle methods. Building on previous work, we present a new dissimilarity measure between subtomograms that works well for the noisy images that often occur in CET images. A technique that is more robust to noise provides the ability to analyze macromolecules in thicker samples such as whole cells or lower the defocus in thinner samples to push the first zero of the Contrast Transfer Function (CTF). Our method, Threshold Constrained Cross-Correlation (TCCC), uses statistics of the noise to automatically select only a small percentage of the Fourier coefficients to compute the cross-correlation, which has two main advantages: first, it reduces the influence of the noise by looking at only those peaks dominated by signal; and second, it avoids the missing wedge normalization problem since we consider the same number of coefficients for all possible pairs of subtomograms. We present results with synthetic and real data to compare our approach with other existing methods under different SNR and missing wedge conditions, and show that TCCC improves alignment results for datasets with SNR<0.1. We have made our source code freely available for the community.
View details for DOI 10.1016/j.jsb.2010.05.013
View details for Web of Science ID 000280680100010
View details for PubMedID 20621702
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The Frankencamera: An Experimental Platform for Computational Photography
ACM TRANSACTIONS ON GRAPHICS
2010; 29 (4)
View details for DOI 10.1145/1778765.1778766
View details for Web of Science ID 000279806600001
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Fast, Non-Monte-Carlo Estimation of Transient Performance Variation Due to Device Mismatch
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
2010; 57 (7): 1746-1755
View details for DOI 10.1109/TCSI.2009.2035418
View details for Web of Science ID 000282562000030
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3D segmentation of cell boundaries from whole cell cryogenic electron tomography volumes
JOURNAL OF STRUCTURAL BIOLOGY
2010; 170 (1): 134-145
Abstract
Cryogenic electron tomography (cryo-ET) has gained increasing interest in recent years due to its ability to image whole cells and subcellular structures in 3D at nanometer resolution in their native environment. However, due to dose restrictions and the inability to acquire high tilt angle images, the reconstructed volumes are noisy and have missing information. Thus, features are unreliable, and precision extraction of the cell boundary is difficult, manual and time intensive. This paper presents an efficient recursive algorithm called BLASTED (Boundary Localization using Adaptive Shape and Texture Discovery) to automatically extract the cell boundary using a conditional random field (CRF) framework in which boundary points and shape are jointly inferred. The algorithm learns the texture of the boundary region progressively, and uses a global shape model and shape-dependent features to propose candidate boundary points on a slice of the membrane. It then updates the shape of that slice by accepting the appropriate candidate points using local spatial clustering, the global shape model, and trained boosted texture classifiers. The BLASTED algorithm segmented the cell membrane over an average of 93% of the length of the cell in 19 difficult cryo-ET datasets.
View details for DOI 10.1016/j.jsb.2009.12.015
View details for Web of Science ID 000276329600016
View details for PubMedID 20035877
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Static control logic for microfluidic devices using pressure-gain valves
NATURE PHYSICS
2010; 6 (3): 218-223
View details for DOI 10.1038/NPHYS1513
View details for Web of Science ID 000275024000024
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Timing Robustness in the Budding and Fission Yeast Cell Cycles
PLOS ONE
2010; 5 (2)
Abstract
Robustness of biological models has emerged as an important principle in systems biology. Many past analyses of Boolean models update all pending changes in signals simultaneously (i.e., synchronously), making it impossible to consider robustness to variations in timing that result from noise and different environmental conditions. We checked previously published mathematical models of the cell cycles of budding and fission yeast for robustness to timing variations by constructing Boolean models and analyzing them using model-checking software for the property of speed independence. Surprisingly, the models are nearly, but not totally, speed-independent. In some cases, examination of timing problems discovered in the analysis exposes apparent inaccuracies in the model. Biologically justified revisions to the model eliminate the timing problems. Furthermore, in silico random mutations in the regulatory interactions of a speed-independent Boolean model are shown to be unlikely to preserve speed independence, even in models that are otherwise functional, providing evidence for selection pressure to maintain timing robustness. Multiple cell cycle models exhibit strong robustness to timing variation, apparently due to evolutionary pressure. Thus, timing robustness can be a basis for generating testable hypotheses and can focus attention on aspects of a model that may need refinement.
View details for DOI 10.1371/journal.pone.0008906
View details for Web of Science ID 000274209700002
View details for PubMedID 20126540
View details for PubMedCentralID PMC2813865
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Energy-Performance Tradeoffs in Processor Architecture and Circuit Design: A Marginal Cost Analysis
37th International Symposium on Computer Architecture
ASSOC COMPUTING MACHINERY. 2010: 26–36
View details for Web of Science ID 000287049300004
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Fortifying Analog Models with Equivalence Checking and Coverage Analysis
IEEE. 2010: 425-430
View details for Web of Science ID 000409973500081
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An Integrated Framework for Joint Design Space Exploration of Microarchitecture and Circuits
IEEE. 2010: 250-255
View details for Web of Science ID 000397468600046
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Why Design Must Change: Rethinking Digital Design
IEEE. 2010: 791
View details for Web of Science ID 000397468600152
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An Efficient Test Vector Generation for Checking Analog/Mixed-Signal Functional Models
IEEE. 2010: 767–72
View details for Web of Science ID 000409973500149
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Intent-Leveraged Optimization of Analog Circuits via Homotopy
IEEE. 2010: 1614–19
View details for Web of Science ID 000397468600309
- Chapter Thirteen-Alignment of Cryo-Electron Tomography Datasets Methods in enzymology Elsevier. 2010: 343–367
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2010 Timing Robustness in the Budding and Fission Yeast Cell Cycles.
PLoS ONE
2010; 2 (5): e8906
View details for DOI 10.1371/journal.pone.0008906
- An integrated framework for joint design space exploration of microarchitecture and circuits 2010
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An efficient test vector generation for checking analog/mixed-signal functional models
2010
View details for DOI 10.1145/1837274.1837468
- Intent-leveraged optimization of analog circuits via homotopy 2010
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Fortifying analog models with equivalence checking and coverage analysis
2010
View details for DOI 10.1145/1837274.1837381
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ALIGNMENT OF CRYO-ELECTRON TOMOGRAPHY DATASETS
METHODS IN ENZYMOLOGY, VOL 482: CRYO-EM, PART B: 3-D RECONSTRUCTION
2010; 482: 343-367
Abstract
Data acquisition of cryo-electron tomography (CET) samples described in previous chapters involves relatively imprecise mechanical motions: the tilt series has shifts, rotations, and several other distortions between projections. Alignment is the procedure of correcting for these effects in each image and requires the estimation of a projection model that describes how points from the sample in three-dimensions are projected to generate two-dimensional images. This estimation is enabled by finding corresponding common features between images. This chapter reviews several software packages that perform alignment and reconstruction tasks completely automatically (or with minimal user intervention) in two main scenarios: using gold fiducial markers as high contrast features or using relevant biological structures present in the image (marker-free). In particular, we emphasize the key decision points in the process that users should focus on in order to obtain high-resolution reconstructions.
View details for DOI 10.1016/S0076-6879(10)82014-2
View details for Web of Science ID 000283462200013
View details for PubMedID 20888968
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Understanding Sources of Inefficiency in General-Purpose Chips
37th International Symposium on Computer Architecture
ASSOC COMPUTING MACHINERY. 2010: 37–47
View details for Web of Science ID 000287049300005
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Energy-Performance Tunable Logic
IEEE JOURNAL OF SOLID-STATE CIRCUITS
2009; 44 (9): 2554-2567
View details for DOI 10.1109/JSSC.2009.2025344
View details for Web of Science ID 000269390700027
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On-Die Power Supply Noise Measurement Techniques
IEEE TRANSACTIONS ON ADVANCED PACKAGING
2009; 32 (2): 248-259
View details for DOI 10.1109/TADVP.2009.2012521
View details for Web of Science ID 000266778000003
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Detector and front-end electronics for 1mm(3) resolution breast-dedicated PET system
SOC NUCLEAR MEDICINE INC. 2009
View details for Web of Science ID 000444145701555
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1 mm(3) Resolution Breast-Dedicated PET System
IEEE Nuclear Science Symposium/Medical Imaging Conference
IEEE. 2009: 5378–5381
View details for Web of Science ID 000268656002327
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Using a configurable processor generator for computer architecture prototyping
2009
View details for DOI 10.1145/1669112.1669159
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Area-efficiency in CMP core design: co-optimization of microarchitecture and physical design
SIGARCH Comput. Archit. New
2009; 37 (2): 56-65
View details for DOI 10.1145/1577129.1577138
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A Memory System Design Framework: Creating Smart Memories
36th Annual International Symposium on Computer Architecture
ASSOC COMPUTING MACHINERY. 2009: 406–417
View details for Web of Science ID 000268225000037
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IN FIELD, ENERGY-PERFORMANCE TUNABLE FPGA ARCHITECTURES
19th International Conference on Field Programmable Logic and Applications
IEEE. 2009: 262–267
View details for Web of Science ID 000277506300040
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Stochastic Steady-State and AC Analyses of Mixed-Signal Systems
46th ACM/IEEE Design Automation Conference (DAC 2009)
IEEE. 2009: 376–381
View details for Web of Science ID 000279394200077
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Energy-Performance Tunable Logic
IEEE Custom Integrated Circuits Conference
IEEE. 2009: 183–186
View details for Web of Science ID 000275926300039
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Front-End Electronics for a 1 mm(3) Resolution Avalanche Photodiode-Based PET System with Analog Signal Multiplexing
IEEE Nuclear Science Symposium/Medical Imaging Conference
IEEE. 2009: 3146–3149
View details for Web of Science ID 000268656001256
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Leveraging Designer's Intent: A Path Toward Simpler Analog CAD Tools
IEEE Custom Integrated Circuits Conference
IEEE. 2009: 613–620
View details for Web of Science ID 000275926300133
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Comparative Evaluation of Memory Models for Chip Multiprocessors
ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION
2008; 5 (3)
View details for DOI 10.1145/1455650.1455651
View details for Web of Science ID 000261844300001
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Architecture and inherent robustness of a bacterial cell-cycle control system
PROCEEDINGS OF THE NATIONAL ACADEMY OF SCIENCES OF THE UNITED STATES OF AMERICA
2008; 105 (32): 11340-11345
Abstract
A closed-loop control system drives progression of the coupled stalked and swarmer cell cycles of the bacterium Caulobacter crescentus in a near-mechanical step-like fashion. The cell-cycle control has a cyclical genetic circuit composed of four regulatory proteins with tight coupling to processive chromosome replication and cell division subsystems. We report a hybrid simulation of the coupled cell-cycle control system, including asymmetric cell division and responses to external starvation signals, that replicates mRNA and protein concentration patterns and is consistent with observed mutant phenotypes. An asynchronous sequential digital circuit model equivalent to the validated simulation model was created. Formal model-checking analysis of the digital circuit showed that the cell-cycle control is robust to intrinsic stochastic variations in reaction rates and nutrient supply, and that it reliably stops and restarts to accommodate nutrient starvation. Model checking also showed that mechanisms involving methylation-state changes in regulatory promoter regions during DNA replication increase the robustness of the cell-cycle control. The hybrid cell-cycle simulation implementation is inherently extensible and provides a promising approach for development of whole-cell behavioral models that can replicate the observed functionality of the cell and its responses to changing environmental conditions.
View details for DOI 10.1073/pnas.0805258105
View details for Web of Science ID 000258560700056
View details for PubMedID 18685108
View details for PubMedCentralID PMC2516238
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Integrated regulation for energy-efficient digital circuits
IEEE Custom Integrated Circuits Conference
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. 2008: 1795–1807
View details for DOI 10.1109/JSSC.2008.925403
View details for Web of Science ID 000257950800009
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A 90 nm CMOS 16 Gb/s transceiver for optical interconnects
IEEE Radio Frequency Integrated Circuits Symposium (RFIC)
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. 2008: 1235–46
View details for DOI 10.1109/JSSC.2008.920330
View details for Web of Science ID 000255354300019
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Digital circuit design trends
20th Symposium on VLSI Circuits
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. 2008: 757–61
View details for DOI 10.1109/JSSC.2008.917523
View details for Web of Science ID 000254560300002
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A 24 Gb/s software programmable analog multi-tone transmitter
20th Symposium on VLSI Circuits
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. 2008: 999–1009
View details for DOI 10.1109/JSSC.2008.917520
View details for Web of Science ID 000254560300029
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Markov random field based automatic image alignment for electron tomography
4th International Conference on Electron Tomography
ACADEMIC PRESS INC ELSEVIER SCIENCE. 2008: 260–75
Abstract
We present a method for automatic full-precision alignment of the images in a tomographic tilt series. Full-precision automatic alignment of cryo electron microscopy images has remained a difficult challenge to date, due to the limited electron dose and low image contrast. These facts lead to poor signal to noise ratio (SNR) in the images, which causes automatic feature trackers to generate errors, even with high contrast gold particles as fiducial features. To enable fully automatic alignment for full-precision reconstructions, we frame the problem probabilistically as finding the most likely particle tracks given a set of noisy images, using contextual information to make the solution more robust to the noise in each image. To solve this maximum likelihood problem, we use Markov Random Fields (MRF) to establish the correspondence of features in alignment and robust optimization for projection model estimation. The resulting algorithm, called Robust Alignment and Projection Estimation for Tomographic Reconstruction, or RAPTOR, has not needed any manual intervention for the difficult datasets we have tried, and has provided sub-pixel alignment that is as good as the manual approach by an expert user. We are able to automatically map complete and partial marker trajectories and thus obtain highly accurate image alignment. Our method has been applied to challenging cryo electron tomographic datasets with low SNR from intact bacterial cells, as well as several plastic section and X-ray datasets.
View details for DOI 10.1016/j.jsb.2007.07.007
View details for Web of Science ID 000254349100006
View details for PubMedID 17855124
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Verification of Chip Multiprocessor Memory Systems Using A Relaxed Scoreboard
41st Annual IEEE/ACM International Symposium on Microarchitecture
IEEE COMPUTER SOC. 2008: 294–305
View details for Web of Science ID 000264849800026
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Circuit-Level Requirements for MOSFET-Replacement Devices
IEEE International Electron Devices Meeting
IEEE. 2008: 427–427
View details for Web of Science ID 000265829300100
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The case for simple, visible cache coherency
2008
View details for DOI 10.1145/1353522.1353532
- Circuit-level requirements for MOSFET-replacement devices Electron Devices Meeting, 2008. IEDM 2008. IEEE International 2008: 1-1
- Markov random field based automatic image alignment for electron tomography Journal of Structural Biology 2008; 161 (3): 260-75
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A High-speed, Low-power 3D-SRAM Architecture
IEEE Custom Integrated Circuits Conference
IEEE. 2008: 201–204
View details for Web of Science ID 000262643900045
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Processor performance modeling using symbolic simulation
IEEE International Symposium on Performance Analysis of Systems and Software
IEEE COMPUTER SOC. 2008: 127–138
View details for Web of Science ID 000255984000013
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A 14-mW 6.25-Gb/s transceiver in 90-nm CMOS
IEEE International Solid-State Circuits Conference (ISSCC)
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. 2007: 2745–57
View details for DOI 10.1109/JSSC.2007.908692
View details for Web of Science ID 000251292000012
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A heuristic for optimizing stochastic activity networks with applications to statistical digital circuit sizing
OPTIMIZATION AND ENGINEERING
2007; 8 (4): 397-430
View details for DOI 10.1007/s11081-007-9011-5
View details for Web of Science ID 000249952000003
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An optical interconnect transceiver at 1550 nm using low-voltage electroabsorption modulators directly integrated to CMOS
JOURNAL OF LIGHTWAVE TECHNOLOGY
2007; 25 (12): 3739-3747
View details for DOI 10.1109/JLT.2007.909334
View details for Web of Science ID 000251943600011
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Veiling glare in high dynamic range imaging
ACM SIGGRAPH 2007 Conference
ASSOC COMPUTING MACHINERY. 2007
View details for DOI 10.1145/1239451.1239488
View details for Web of Science ID 000248914000040
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Power optimization for SRAM and its scaling
IEEE TRANSACTIONS ON ELECTRON DEVICES
2007; 54 (4): 715-722
View details for DOI 10.1109/TED.2007.891869
View details for Web of Science ID 000245327900014
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Chip multi-processor generator
44th ACM/IEEE Design Automation Conference
IEEE. 2007: 262–263
View details for Web of Science ID 000249725800052
- 1550nm Optical Interconnect Transceiver with Low Voltage Electroabsorption Modulators Flip-Chip Bonded to 90nm CMOS 2007
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Fast, non-monte-carlo estimation of transient performance variation due to device mismatch
44th ACM/IEEE Design Automation Conference
IEEE. 2007: 440–443
View details for Web of Science ID 000249725800092
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Integrated regulation for energy-efficient digital circuits
IEEE Custom Integrated Circuits Conference
IEEE. 2007: 389–392
View details for Web of Science ID 000252233200090
- Variable domain transformation for linear PAC analysis of mixed-signal systems 2007
- Fast, Non-Monte-Carlo Estimation of Transient Performance Variation Due to Device Mismatch 2007
- Chip Multi-Processor Generator. DAC 2007
- Integrated Regulation for Energy-Efficient Digital Circuits 2007
- A 24Gbps Software Programmable Multi-Channel Transmitter 2007
- A 12GS/S Phase-Calibrated CMOS Digital-to-Analog Coverter 2007
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Variable domain transformation for linear PAC analysis of mixed-signal systems
IEEE/ACM International Conference on Computer-Aided Design
IEEE. 2007: 887–894
View details for Web of Science ID 000253303700142
- A 14mW 6.25Gb/s Transceiver in 90nm CMOS for Serial Chip-to-Chip Communications 2007
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Synthetic aperture focusing using dense camera arrays
Workshop on Advanced 3D Imaging for Safety and Security held in Conjunction with the International Conference on Computer Vision and Pattern Recognition
SPRINGER. 2007: 159-?
View details for Web of Science ID 000250475200007
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A new technique for characterization of digital-to-analog converters in high-speed systems
Design, Automation and Test in Europe Conference and Exhibition (DATE 07)
IEEE. 2007: 433–438
View details for Web of Science ID 000252175700073
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A 24Gb/s software programmable multi-channel transmitter
20th Symposium on VLSI Circuits
JAPAN SOCIETY APPLIED PHYSICS. 2007: 38–39
View details for Web of Science ID 000250541000014
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Comparing Memory Systems for Chip Multiprocessors
34th Annual International Symposium on Computer Architecture
ASSOC COMPUTING MACHINERY. 2007: 358–368
View details for Web of Science ID 000265786200032
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Robust energy-efficient adder topologies
18th IEEE Symposium on Computer Arithmetic
IEEE COMPUTER SOC. 2007: 16–25
View details for Web of Science ID 000248520400003
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Noise analysis of LSO-PSAPD PET detector front-end multiplexing circuits
IEEE Nuclear Science Symposium/Medical Imaging Conference
IEEE. 2007: 3212–3219
View details for Web of Science ID 000257380402138
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Practical limits of multi-tone signaling over high-speed backplane electrical links
IEEE International Conference on Communications (ICC 2007)
IEEE. 2007: 2693–2698
View details for Web of Science ID 000257882501208
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Time-variant characterization and compensation of wideband circuits
IEEE Custom Integrated Circuits Conference
IEEE. 2007: 487–490
View details for Web of Science ID 000252233200109
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Measurement of supply pin current distributions in integrated circuit packages
16th IEEE Topical Meeting on Electrical Performance of Electronic Packaging
IEEE. 2007: 7–10
View details for Web of Science ID 000251017800002
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Light field microscopy
ACM TRANSACTIONS ON GRAPHICS
2006; 25 (3): 924-934
View details for Web of Science ID 000239817400054
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Replica compensated linear regulators for supply-regulated phase-locked loops
IEEE JOURNAL OF SOLID-STATE CIRCUITS
2006; 41 (2): 413-424
View details for DOI 10.1109/JSSC.2005.862347
View details for Web of Science ID 000235372800011
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A heuristic method for statistical digital circuit sizing
4th Conference on Design and Process Integration for Microelectronic Manufacturing
SPIE-INT SOC OPTICAL ENGINEERING. 2006
View details for DOI 10.1117/12.657499
View details for Web of Science ID 000238444200008
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The implementation of a 2-core, multi-threaded Itanium family processor
IEEE International Solid-State Circuits Conference (ISSCC 2005)
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. 2006: 197–209
View details for DOI 10.1109/JSSC.2005.859894
View details for Web of Science ID 000234305600022
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Analog Multi-Tone Signaling for High-Speed Backplane Electrical Links
IEEE Global Telecommunications Conference (GLOBECOM 06)
IEEE. 2006
View details for Web of Science ID 000288765602170
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High-speed transmitters in 90nm CMOS for high-density optical interconnects
32nd European Solid-State Circuits Conference
IEEE. 2006: 508–511
View details for Web of Science ID 000245212800122
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Measurement of via currents in printed circuit boards using inductive loops
15th IEEE Topical Meeting on Electrical Performance of Electronic Packaging
IEEE. 2006: 37–40
View details for Web of Science ID 000243330600009
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Compensation for multimode fiber dispersion by adaptive optics
OPTICS LETTERS
2005; 30 (22): 2985-2987
Abstract
Adaptive optics is used to compensate for modal dispersion in digital transmission through multimode fiber (MMF). At the transmitter, a spatial light modulator (SLM) controls the launched field pattern. An estimate of intersymbol interference (ISI) caused by modal dispersion is formed at the receiver and fed back to the transmitter, where the SLM is adjusted to minimize ISI. Error-free transmission of 10 Gbit/s non-return-to-zero signals through standard 50 microm graded-index MMFs up to 11.1 km long is demonstrated. It is shown that a single SLM can compensate for modal dispersion across a 600 GHz bandwidth.
View details for Web of Science ID 000233258800005
View details for PubMedID 16315696
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Digital circuit optimization via geometric programming
OPERATIONS RESEARCH
2005; 53 (6): 899-932
View details for DOI 10.1287/opre.1050.0254
View details for Web of Science ID 000234756000002
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False coupling exploration in timing analysis
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
2005; 24 (11): 1795-1805
View details for DOI 10.1109/TCAD.2005.852435
View details for Web of Science ID 000232971600012
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Dual photography
ACM SIGGRAPH 2005 Conference
ASSOC COMPUTING MACHINERY. 2005: 745–55
View details for Web of Science ID 000231223700045
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High performance imaging using large camera arrays
ACM SIGGRAPH 2005 Conference
ASSOC COMPUTING MACHINERY. 2005: 765–76
View details for Web of Science ID 000231223700047
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On task mapping optimization for parallel decoding of low-density parity-check codes on message-passing architectures
PARALLEL COMPUTING
2005; 31 (5): 462-490
View details for DOI 10.1016/j.parco.2004.12.009
View details for Web of Science ID 000230195500003
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A 20-Gb/s 0.13-mu m CMOS serial link transmitter using an LC-PLL to directly drive the output multiplexer
Symposium on VLSI Circuits
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. 2005: 1004–11
View details for DOI 10.1109/JSSC.2004.842841
View details for Web of Science ID 000228564400025
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Autonomous dual-mode (PAM2/4) serial link transceiver with adaptive equalization and data recovery
Symposium on VLSI Circuits
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. 2005: 1012–26
View details for DOI 10.1109/JSSC.2004.842863
View details for Web of Science ID 000228564400026
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Circuits and techniques for high-resolution measurement of on-chip power supply noise
Symposium on VLSI Circuits
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. 2005: 820–28
View details for DOI 10.1109/JSSC.2004.842853
View details for Web of Science ID 000228564400003
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Architecture and circuit techniques for a 1.1-GHz 16-kb reconfigurable memory in 0.18-mu m CMOS
IEEE International Solid-State Circuits Conference
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. 2005: 261–75
View details for Web of Science ID 000226124500027
- Clocking and circuit design for a parallel I/O on a first-generation CELL processor 2005
- A new method for design of robust digital circuits. 2005
- Opportunities for optics in integrated circuits applications. Solid-State Circuits Conference 2005
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High-speed videography using a dense camera array
26th International Congress on High-Speed Photography and Photonics
SPIE-INT SOC OPTICAL ENGINEERING. 2005: 913–920
View details for Web of Science ID 000228994200101
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Scaling, power, and the future of CMOS
IEEE International Electron Devices Meeting
IEEE. 2005: 11–17
View details for Web of Science ID 000236225100002
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Scalable circuits for supply noise measurement
31st European Solid-State Circuits Conference
IEEE. 2005: 463–466
View details for Web of Science ID 000235469600109
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A new method for design of robust digital circuits
6th International Symposium on Quality Electronic Design
IEEE COMPUTER SOC. 2005: 676–681
View details for Web of Science ID 000228486600110
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Synthetic aperture confocal imaging
Annual Symposium of the ACM SIGGRAPH
ASSOC COMPUTING MACHINERY. 2004: 825–34
View details for Web of Science ID 000222972600083
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Methods for true energy-performance optimization
IEEE JOURNAL OF SOLID-STATE CIRCUITS
2004; 39 (8): 1282-1293
View details for DOI 10.1109/JSSC.2004.831796
View details for Web of Science ID 000222902600007
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CMOS transceiver with baud rate clock recovery for optical interconnects
Symposium on VLSI Circuits
IEEE. 2004: 410–413
View details for Web of Science ID 000224752900101
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Adaptive equalization and data recovery in a dual-mode (PAM2/4) serial link transceiver
Symposium on VLSI Circuits
IEEE. 2004: 348–351
View details for Web of Science ID 000224752900085
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Common-mode backchannel signaling system for differential high-speed links
Symposium on VLSI Circuits
IEEE. 2004: 352–355
View details for Web of Science ID 000224752900086
- Circuits and techniques for high-resolution measurement of on-chip power supply noise 2004
- Adaptive equalization and data recovery in a dual-mode (PAM2/4) serial link transceiver 2004
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Equalization of modal dispersion in multimode fiber using spatial light modulators
IEEE Global Telecommunications Conference (GLOBECOM 04)
IEEE. 2004: 1023–1029
View details for Web of Science ID 000226689900195
- 20Gb/s 0.13 mu m CMOS serial link transmitter using an LC-PLL to directly drive the output multiplexer 2004
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Burst mode packet receiver using a second order DLL
Symposium on VLSI Circuits
IEEE. 2004: 264–267
View details for Web of Science ID 000224752900064
- Burst mode packet receiver using a second order DLL 2004
- Common-mode backchannel signaling system for differential high-speed links 2004
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Optimal linear precoding with theoretical and practical data rates in high-speed serial-link backplane communication
IEEE International Conference on Communications (ICC 2004)
IEEE. 2004: 2799–2806
View details for Web of Science ID 000223459600546
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High-speed videography using a dense camera array
Conference on Computer Vision and Pattern Recognition
IEEE COMPUTER SOC. 2004: 294–301
View details for Web of Science ID 000223605500039
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Architecture and circuit techniques for a reconfigurable memory block
IEEE International Solid-State Circuits Conference
IEEE. 2004: 500–501
View details for Web of Science ID 000221633800210
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How scaling will change processor architecture
IEEE International Solid-State Circuits Conference
IEEE. 2004: 132–133
View details for Web of Science ID 000221633800047
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The stream virtual machine
13th International Conference on Parallel Architecture and Compilation Techniques
IEEE COMPUTER SOC. 2004: 267–277
View details for Web of Science ID 000224469900025
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Multi-tone signaling for high-speed backplane electrical links
IEEE Global Telecommunications Conference (GLOBECOM 04)
IEEE. 2004: 1111–1117
View details for Web of Science ID 000226689900212
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Equalization and clock recovery for a 2.5-10-Gb/s 2-PAM/4-PAM backplane transceiver cell
IEEE International Solid-State Circuits Conference
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. 2003: 2121–30
View details for DOI 10.1109/JSSC.2003.818572
View details for Web of Science ID 000187569900013
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A 10-GHz global clock distribution using coupled standing-wave oscillators
IEEE International Solid-State Circuits Conference
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. 2003: 1813–20
View details for DOI 10.1109/JSSC.2003.818299
View details for Web of Science ID 000186249100004
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Design of CMOS adaptive-bandwidth PLL/DLLs: A general approach
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
2003; 50 (11): 860-869
View details for DOI 10.1109/TCSII.2003.819120
View details for Web of Science ID 000186646500010
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Scaling Internet routers using optics
SIGCOMM 2003 Conference
ASSOC COMPUTING MACHINERY. 2003: 189–200
View details for Web of Science ID 000188215800017
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Efficient on-chip global interconnects
Symposium on VLSI Circuits
JAPAN SOCIETY APPLIED PHYSICS. 2003: 271–274
View details for Web of Science ID 000185582200075
- Implementing an untrusted operating system on trusted hardware. Operating Systems Review 2003; 37 (5): 178-92
- A framework for designing reusable analog circuits 2003
- Equalization and clock recovery for a 2.5-10-Gb/s 2-PAM/4-PAM backplane transceiver cell. IEEE Journal of Solid-State Circuits 2003; 38 (12): 2121 - 2130
- Design of CMOS adaptive-bandwidth PLL/DLLs: a general approach. Circuits and Systems II: Analog and Digital Signal Processing IEEE Transactions on [see also Circuits and Systems II: Express Briefs, IEEE Transactions on] 2003; 50 (11): 860-869
- Modeling and analysis of high-speed links 2003
- A 0.4-4-Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs. IEEE Journal of Solid-State Circuits 2003; 38 (5): 747-54
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10GHz clock distribution using coupled standing-wave oscillators
IEEE International Solid-State Circuits Conference
IEEE. 2003: 428-?
View details for Web of Science ID 000185583300183
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Design of a 10GHz clock distribution network using coupled standing-wave oscillators
40th Design Automation Conference
ASSOC COMPUTING MACHINERY. 2003: 682–687
View details for Web of Science ID 000184080900125
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Managing wire scaling: A circuit perspective
6th Annual International Interconnect Technology Conference
IEEE. 2003: 177–179
View details for Web of Science ID 000184465800053
- A 10-GHz global clock distribution using coupled standing-wave oscillators Solid-State Circuits IEEE Journal of 2003; 38 (11): 1813-1820
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Specifying and verifying hardware for tamper-resistant software
2003 IEEE Symposium on Security and Privacy
IEEE COMPUTER SOC. 2003: 166–177
View details for Web of Science ID 000183375200012
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Adaptive supply serial links with sub-I-V operation and per-pin clock recovery
IEEE International Solid State Circuits Conference
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. 2002: 1403–13
View details for DOI 10.1109/JSSC.2002.803937
View details for Web of Science ID 000179027300005
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High-frequency characterization of on-chip digital interconnects
IEEE JOURNAL OF SOLID-STATE CIRCUITS
2002; 37 (6): 716-725
View details for Web of Science ID 000175929500006
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An efficient digital sliding controller for adaptive power-supply regulation
Symposium on VLSI Circuits
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. 2002: 639–47
View details for Web of Science ID 000175198900015
- 1.6 Gb/s, 3 mW CMOS receiver for optical communication 2002
- Transmit pre-emphasis for high-speed time-division-multiplexed serial-link transceiver 2002
- Methods for true power minimization 2002
- Energy-delay tradeoffs in combinational logic using gate sizing and supply voltage optimization. ESSCIRC 2002 2002
- Power Aware Design Methodologies. 2002
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A serial-link transceiver based on 8-GSamples/s A/D and D/A converters in 0.25-mu m CMOS
IEEE JOURNAL OF SOLID-STATE CIRCUITS
2001; 36 (11): 1684-1692
View details for Web of Science ID 000171893000010
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Fast low-power decoders for RAMs
IEEE JOURNAL OF SOLID-STATE CIRCUITS
2001; 36 (10): 1506-1515
View details for Web of Science ID 000171192400009
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The future of wires
PROCEEDINGS OF THE IEEE
2001; 89 (4): 490-504
View details for Web of Science ID 000168465500005
- Light field video camera 2001
- Using texture mapping with mipmapping to render a VLSI layout 2001
- Sampling-rate optimization of an interleaved-sampling front-end. ISCAS 2001 2001
- Optimizing iterative decoding of low-density parity check codes on programmable pipelined parallel architectures 2001
- A serial-link transceiver based on 8 GSample/s A/D and D/A converters in 0.25 mu m CMOS 2001
- High-Speed Electrical Signaling in Design of High-Performance Microprocessor Circuits 2001
- Optimizing the mapping of low-density parity check codes on parallel decoding architectures 2001
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Architectural support for copy and tamper resistant software
9th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS_IX)
ASSOC COMPUTING MACHINERY. 2000: 168–77
View details for Web of Science ID 000165257200017
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FLASH vs. (Simulated) FLASH: Closing the simulation loop
9th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS_IX)
ASSOC COMPUTING MACHINERY. 2000: 49–58
View details for Web of Science ID 000165257200006
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A 2.4 gb/s/pin simultaneous bidirectional parallel link with per-pin skew compensation
International Solid-State Circuits Conference
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. 2000: 1619–28
View details for Web of Science ID 000165222500012
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A variable-frequency parallel I/O interface with adaptive power-supply regulation
International Solid-State Circuits Conference
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. 2000: 1600–1610
View details for Web of Science ID 000165222500010
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A 0.3-mu m CMOS 8-Gb/s 4-PAM serial link transceiver
Symposium on VLSI Circuits
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. 2000: 757–64
View details for Web of Science ID 000087046400013
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Speed and power scaling of SRAM's
IEEE JOURNAL OF SOLID-STATE CIRCUITS
2000; 35 (2): 175-185
View details for Web of Science ID 000085393200005
- M. FLASH vs. (simulated) FLASH: closing the simulation loop Operating Systems Review 2000; 34 (5): 49-58
- Adaptive bandwidth DLLs and PLLs using regulated supply CMOS buffers 2000
- Smart Memories: a modular reconfigurable architecture 2000
- An eight channel 35 GSample/s CMOS timing analyzer 2000
- A 2.4 Gb/s/pin simultaneous bidirectional parallel link with per pin skew compensation 2000
- A variable-frequency parallel I/O interface with adaptive power-supply regulation. IEEE Journal of Solid-State Circuits 2000; 35 (11): 1600-10
- 64 Mbit mesochronous hybrid wave pipelined multibank DRAM macro Intelligent Memory Systems. Second International Workshop, IMS 2000. Revised Papers, Cambridge, MA, USA. 2000
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Timing analysis including clock skew
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
1999; 18 (11): 1608-1618
View details for Web of Science ID 000084031600007
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A 0.4-mu m CMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter
Symposium on VLSI Circuits
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. 1999: 580–85
View details for Web of Science ID 000080039500003
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A portable digital DLL for high-speed CMOS interface circuits
Symposium on VLSI Circuits
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. 1999: 632–44
View details for Web of Science ID 000080039500010
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A fully digital, energy-efficient, adaptive power-supply regulator
IEEE JOURNAL OF SOLID-STATE CIRCUITS
1999; 34 (4): 520-528
View details for Web of Science ID 000079369400011
- Using Partitioning to Help Convergence in the Standard-Cell Design Automation Methodology 1999
- A 50 Gb/s 32*32 CMOS crossbar chip using asymmetric serial links 1999
- A 0.3- mu m CMOS 8-Gb/s 4-PAM serial link transceiver 1999
- Using partitioning to help convergence in the standard-cell design automation methodology 1999
- Scaling implications for CAD 1999
- Improving Coverage Analysis and Test Generation for Large Designs 1999
- GAD: A 12-GS/s CMOS 4-bit A/D converter for an equalized multi-level link 1999
- Vex - A CAD Toolbox 1999
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Low-power dividerless frequency synthesis using aperture phase detection
IEEE JOURNAL OF SOLID-STATE CIRCUITS
1998; 33 (12): 2232-2239
View details for Web of Science ID 000077298100043
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Low-power SRAM design using half-swing pulse-mode techniques
IEEE JOURNAL OF SOLID-STATE CIRCUITS
1998; 33 (11): 1659-1671
View details for Web of Science ID 000076702900010
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A replica technique for wordline and sense control in low-power SRAM's
IEEE JOURNAL OF SOLID-STATE CIRCUITS
1998; 33 (8): 1208-1219
View details for Web of Science ID 000075185400010
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A 0.5-mu m CMOS 4.0-Gbit/s serial link transceiver with data recovery using oversampling
1997 Symposium on VLSI Circuits
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. 1998: 713–22
View details for Web of Science ID 000073300400007
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Informing memory operations: Memory performance feedback mechanisms and their applications
ACM TRANSACTIONS ON COMPUTER SYSTEMS
1998; 16 (2): 170-205
View details for Web of Science ID 000074989800003
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High-speed electrical signaling: Overview and limitations
IEEE MICRO
1998; 18 (1): 12-24
View details for Web of Science ID 000071906600005
- A 2Gb/s Asymmetric Serial Link for High-bandwidth Packet Switches 1998
- Applications of On-Chip Samplers for Test and Measurement of Integrated Circuits 1998
- A 0.4-µm CMOS 10-Gb/s 4-PAM Pre-Emphasis Serial Link Transmitter 1998
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Approximate reachability with BDDs using overlapping projections
35th Design Automation Conference
ASSOC COMPUTING MACHINERY. 1998: 451–456
View details for Web of Science ID 000077273700081
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A semidigital dual delay-locked loop
IEEE JOURNAL OF SOLID-STATE CIRCUITS
1997; 32 (11): 1683-1692
View details for Web of Science ID A1997YE47600008
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Skew-tolerant domino circuits
IEEE JOURNAL OF SOLID-STATE CIRCUITS
1997; 32 (11): 1702-1711
View details for Web of Science ID A1997YE47600010
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Circuit techniques for 1.5-V power supply flash memory
IEEE JOURNAL OF SOLID-STATE CIRCUITS
1997; 32 (8): 1217-1230
View details for Web of Science ID A1997XL40400007
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Supply and threshold voltage scaling for low power CMOS
IEEE JOURNAL OF SOLID-STATE CIRCUITS
1997; 32 (8): 1210-1216
View details for Web of Science ID A1997XL40400006
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Optimization of hybrid JJ/CMOS memory operating temperatures
1996 Applied Superconductivity Conference
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. 1997: 3307–10
View details for Web of Science ID A1997XH86700251
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A 700-Mb/s/pin CMOS signaling interface wing current integrating receivers
IEEE JOURNAL OF SOLID-STATE CIRCUITS
1997; 32 (5): 681-690
View details for Web of Science ID A1997WV64100010
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Hardware/software co-design of the Stanford FLASH multiprocessor
PROCEEDINGS OF THE IEEE
1997; 85 (3): 455-466
View details for Web of Science ID A1997WN92900007
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Skew-tolerant domino circuits
1997 IEEE International Solid-State Circuits Conference
I E E E. 1997: 422–423
View details for Web of Science ID A1997BH40E00172
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Hardware fault containment in scalable shared-memory multiprocessors
24th Annual International Symposium on Computer Architecture
ASSOC COMPUTING MACHINERY. 1997: 73–84
View details for Web of Science ID A1997BH95B00007
- A 0.6u CMOS 4.0Gbps Transceiver with Data Recovery using Oversampling 1997
- An Equalization Scheme for 10Gb/s 4-PAM Signaling over Long Cables 1997
- SRT Division Architectures and Implementations 1997
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A semi-digital DLL with unlimited phase shift capability and 0.08-400MHz operating range
1997 IEEE International Solid-State Circuits Conference
I E E E. 1997: 332–333
View details for Web of Science ID A1997BH40E00132
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Tiny Tera: A packet switch core
4th Annual Hot Interconnects Symposium
IEEE COMPUTER SOC. 1997: 26–33
View details for Web of Science ID A1997WF58800009
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A 0.6 mu m CMOS 4Gb/s transceiver with data recovery using oversampling
1997 Symposium on VLSI Circuits
JAPAN SOCIETY APPLIED PHYSICS. 1997: 71–72
View details for Web of Science ID A1997BJ59E00031
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A 0.8-mu m CMOS 2.5 Gb/s oversampling receiver and transmitter for serial links
1996 International Solid-State Circuits Conference (ISSCC)
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. 1996: 2015–23
View details for Web of Science ID A1996VX90200023
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Energy dissipation in general purpose microprocessors
IEEE JOURNAL OF SOLID-STATE CIRCUITS
1996; 31 (9): 1277-1284
View details for Web of Science ID A1996VE60100006
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Informing memory operations: Providing memory performance feedback in modem processors
23rd Annual International Symposium on Computer Architecture
ASSOC COMPUTING MACHINERY. 1996: 260–270
View details for Web of Science ID A1996BF68U00024
- Validation Coverage Analysis for Complex Digital Designs 1996
- Informing Memory Operations: Providing Memory Performance Feedback in Modern Processors 1996
- A 50% Noise Reduction Interface Using Low-Weight Coding 1996
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A 700 Mbps/pin CMOS signalling interface using current integrating receivers
1996 Symposium on VLSI Circuits
I E E E. 1996: 142–143
View details for Web of Science ID A1996BF78R00053
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A low power switching power supply for self-clocked systems
1996 International Symposium on Low Power Electronics and Design (1996 ISLPED)
I E E E. 1996: 313–317
View details for Web of Science ID A1996BG22B00062
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A 0.8 mu m CMOS 2.5Gb/s oversampled receiver for serial links
1996 IEEE International Solid-State Circuits Conference
I E E E. 1996: 200–201
View details for Web of Science ID A1996BF43W00077
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Regenerative feedback repeaters for programmable interconnections
IEEE JOURNAL OF SOLID-STATE CIRCUITS
1995; 30 (11): 1246-1253
View details for Web of Science ID A1995TM39100013
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Architecture validation for processors
22nd Annual International Symposium on Computer Architecture
ASSOC COMPUTING MACHINERY. 1995: 404–413
View details for Web of Science ID A1995BE13F00036
- Clustered Voltage Scaling Technique for Low-Power Design 1995
- Array-of-arrays Architecture for Parallel Floating Point Multiplication Advanced Research in VLSI 1995: 150-157
- Informing Loads: Enabling Software to Observe and React to Memory Behavior Stanford University, Technical Report 1995: CSL-TR-95-673
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Current integrating receivers for high speed system interconnects
IEEE 1995 Custom Integrated Circuits Conference
I E E E. 1995: 107–110
View details for Web of Science ID A1995BD31E00023
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REGENERATIVE FEEDBACK REPEATERS FOR PROGRAMMABLE INTERCONNECTIONS
1995 IEEE International Solid-State Circuits Conference
I E E E. 1995: 116–117
View details for Web of Science ID A1995BD33W00041
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TIMING ANALYSIS FOR PIECEWISE-LINEAR RSIM
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
1994; 13 (12): 1498-1512
View details for Web of Science ID A1994PT59100007
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THE PERFORMANCE IMPACT OF FLEXIBILITY IN THE STANFORD FLASH MULTIPROCESSOR
6th International Conference on Architectural Support for Programming Languages and Operating Systems
ASSOC COMPUTING MACHINERY. 1994: 274–85
View details for Web of Science ID A1994PX02700026
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INTERLEAVING - A MULTITHREADING TECHNIQUE TARGETING MULTIPROCESSORS AND WORKSTATIONS
6th International Conference on Architectural Support for Programming Languages and Operating Systems
ASSOC COMPUTING MACHINERY. 1994: 308–18
View details for Web of Science ID A1994PX02700029
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SELF-TIMED LOGIC USING CURRENT-SENSING COMPLETION DETECTION (CSCD)
JOURNAL OF VLSI SIGNAL PROCESSING
1994; 7 (1-2): 7-16
View details for Web of Science ID A1994NA69100002
- Architectural and Implementation Tradeoffs in the Design of Multiple-Context Processors Multithreaded Computer Architectures Kluwer Academic Publishers. 1994: 1
- Techniques to Reduce Power in Fast Wide Memories (CMOS SRAMS) 1994
- Using Partitioning to Help Convergence in the Standard-cell Design Automation Methodology 1994
- Techniques for Characterizing DRAMS with a 500 MHZ Interface 1994
- Low-Power Digital Design 1994
- Evaluation of Charge Recovery Circuits and Adiabatic Switching for Low Power CMOS Design 1994
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WHO WILL WIN THE WINDOWS NT SILICON SWEEPSTAKES
1994 IEEE International Solid-State Circuits Conference
I E E E. 1994: 234–235
View details for Web of Science ID A1994BA99E00093
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A CMOS 500-MBPS PIN SYNCHRONOUS POINT-TO-POINT LINK INTERFACE
1994 Symposium on VLSI Circuits
I E E E. 1994: 43–44
View details for Web of Science ID A1994BB60F00019
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THE STANFORD FLASH MULTIPROCESSOR
21st Annual International Symposium on Computer Architecture
I E E E, COMPUTER SOC PRESS. 1994: 302–313
View details for Web of Science ID A1994BA93B00027
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PRECISE DELAY GENERATION USING COUPLED OSCILLATORS
IEEE JOURNAL OF SOLID-STATE CIRCUITS
1993; 28 (12): 1273-1282
View details for Web of Science ID A1993MX67800012
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THE DESIGN OF A HIGH-PERFORMANCE CACHE CONTROLLER - A CASE-STUDY IN ASYNCHRONOUS SYNTHESIS
INTEGRATION-THE VLSI JOURNAL
1993; 15 (3): 241-262
View details for Web of Science ID A1993MK62900002
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NONDESTRUCTIVE READOUT ARCHITECTURE FOR A KINETIC INDUCTANCE MEMORY CELL
IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY
1993; 3 (1): 2702-2705
View details for Web of Science ID 000209703300218
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NONDESTRUCTIVE READOUT ARCHITECTURE FOR A KINETIC INDUCTANCE MEMORY CELL
1992 Applied Superconductivity Conference
I E E E. 1993: 2702–2705
View details for Web of Science ID A1993BZ49H00633
- Piecewise Linear Models for Rsim 1993
- PLL Design for a 500 MB/s Interface 1993
- Performance Analysis of a Kinetic Inductance Memory Array 1993
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EFFICIENT SUPERSCALAR PERFORMANCE THROUGH BOOSTING
SIGPLAN NOTICES
1992; 27 (9): 248-259
View details for Web of Science ID A1992JT83700021
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CIRCUIT TECHNIQUES FOR LARGE CSEA SRAMS
IEEE JOURNAL OF SOLID-STATE CIRCUITS
1992; 27 (6): 908-919
View details for Web of Science ID A1992HV42000007
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THE STANFORD DASH MULTIPROCESSOR
COMPUTER
1992; 25 (3): 63-79
View details for Web of Science ID A1992HH04100006
- Circuit Techniques for Large CSEA SRAM's IEEE Journal of Solid-State Circuits 1992; 27 (6): 908-919
- A 500-Megabyte/s Data-Rate 4.5M DRAM 1992
- Clocking Strategies in High Performance Processors 1992
- Architectural and Implementation Tradeoffs in the Design of Multiple-Context Processors 1992
- 500 Mbyte/sec Data-Rate 512 Kbits*9 DRAM Using a Novel I/O Interface 1992
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A ZERO-OVERHEAD SELF-TIMED 160-NS 54-B CMOS DIVIDER
IEEE JOURNAL OF SOLID-STATE CIRCUITS
1991; 26 (11): 1651-1661
View details for Web of Science ID A1991GL70900026
- Dynamic Pointer Allocation for Scalable Cache Coherence Directories 1991
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A 160NS 54BIT CMOS DIVISION IMPLEMENTATION USING SELF-TIMING AND SYMMETRICALLY OVERLAPPED SRT STAGES
10TH IEEE SYMP ON COMPUTER ARITHMETIC
I E E E, COMPUTER SOC PRESS. 1991: 210–217
View details for Web of Science ID A1991BT73A00028
- Asymptotic Waveform Evaluation for Circuits With Redundant DC Equations Stanford University, Technical Report 1991: CSL-TR-91-478
- A 160nS 54bit CMOS Division Implementation Using Self-Timing and Symmetrically Overlapped SRT Stages 1991
- Dynamic Pointer Allocation for Scalable Cache Coherence Directories Stanford University, Technical Report 1991: CSL-TR-91-491
- Efficient Moment-Based Timing Analysis for Variable Accuracy Switch Level Simulation Stanford University, Technical Report 1991: CSL-TR-91-468
- Modeling the Performance of Limited Pointers Directories for Cache Coherence 1991
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A 4-NS BICMOS TRANSLATION-LOOKASIDE BUFFER
IEEE JOURNAL OF SOLID-STATE CIRCUITS
1990; 25 (5): 1093-1101
View details for Web of Science ID A1990EA15600008
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TECHNIQUES FOR CALCULATING CURRENTS AND VOLTAGES IN VLSI POWER-SUPPLY NETWORKS
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
1990; 9 (2): 126-132
View details for Web of Science ID A1990CJ15600002
- A Single-Chip, Functional Tester for VLSI Circuits 1990
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BOOSTING BEYOND STATIC SCHEDULING IN A SUPERSCALAR PROCESSOR
17TH ANNUAL INTERNATIONAL SYMP ON COMPUTER ARCHITECTURE
I E E E, COMPUTER SOC PRESS. 1990: 344–354
View details for Web of Science ID A1990BQ97U00032
- Boosting Beyond Static Scheduling in a Superscalar Processor Stanford University, Technical Report 1990: CSL-TR-90-434
- Design of Scalable Shared-Memory Multiprocessors: the DASH Approach, Held: San Francisco, CA 1990
- Boosting Beyond Static Scheduling in a Superscalar Processor 1990
- BiCMOS Circuit Design 1990
- A 3.5ns, 1 Watt, ECL Register File 1990
- Limits on Multiple Instruction Issue Stanford University, Technical Report 1990: CSL-TR-90-433
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AN ANALYTICAL CACHE MODEL
ACM TRANSACTIONS ON COMPUTER SYSTEMS
1989; 7 (2): 184-215
View details for Web of Science ID A1989U462500003
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SPIM - A PIPELINED 64 X 64-BIT ITERATIVE MULTIPLIER
IEEE JOURNAL OF SOLID-STATE CIRCUITS
1989; 24 (2): 487-493
View details for Web of Science ID A1989T854100037
- Design of the Stanford Dash Multiprocessor Stanford University, Technical Report 1989: CSL-TR-89-403
- IRSIM: An Incremental MOS Switch-Level Simulator, IEEE/ACM 1989
- Rounding Algorithms for IEEE Multipliers 1989
- Characteristics of Performance-Optimal Multi-Level Cache Hierarchies 1989
- A Single-Ended BiCMOS Sense Circuit for Digital Circuit 1989
- The MIPS-X RISC Microprocessor Kluwer Academic Publishers. 1989
- Integrated Pin Electronics for VLSI Functional Testers 1989
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CACHE PERFORMANCE OF OPERATING SYSTEM AND MULTIPROGRAMMING WORKLOADS
ACM TRANSACTIONS ON COMPUTER SYSTEMS
1988; 6 (4): 393-431
View details for Web of Science ID A1988Q844600003
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SPECIAL ISSUE ON LOGIC AND MEMORY - FOREWORD
IEEE JOURNAL OF SOLID-STATE CIRCUITS
1988; 23 (5): 1028-1029
View details for Web of Science ID A1988Q243900001
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A 4-NS 4K X 1-BIT 2-PORT BICMOS SRAM
IEEE JOURNAL OF SOLID-STATE CIRCUITS
1988; 23 (5): 1030-1040
View details for Web of Science ID A1988Q243900002
- Bisim: A Simulator for Custom ECL Circuits 1988
- Performance Tradeoffs in Cache Design, IEEE 1988
- Scalable Directory Schemes for Cache Consistency 1988
- A 4nsec 4Kx1bit Two-Port BiCMOS SRAM 1988
- The Design and Testing of MIPS-X Advanced Research in VLSI, Cambridge, MA MIT Press. 1988: 95–114
- Generalization in Digital Functions International Neural Network Society 1988 First Annual Meeting, Boston, MA, Neural Networks 1988; 1 (1): 101
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CHARGE-SHARING MODELS FOR SWITCH-LEVEL SIMULATION
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
1987; 6 (6): 1053-1061
View details for Web of Science ID A1987K634400013
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MIPS-X - A 20-MIPS PEAK, 32-BIT MICROPROCESSOR WITH ON-CHIP CACHE
IEEE JOURNAL OF SOLID-STATE CIRCUITS
1987; 22 (5): 790-799
View details for Web of Science ID A1987K182100024
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A SINGLE-CHIP LSI HIGH-SPEED FUNCTIONAL TESTER
IEEE JOURNAL OF SOLID-STATE CIRCUITS
1987; 22 (5): 820-828
View details for Web of Science ID A1987K182100027
- Architectural Tradeoffs in the Design of MIPS-X 1987
- A Self Timing SRT Division Chip Advanced Research in VLSI, Stanford, CA MIT Press. 1987: 75–95
- On-Chip Instruction Caches for High Performance Processors 1987
- A Static RAM as a Fault Model Evaluator 1987
- REDS: Resistance Extraction for Digital Stimulation, ACM/IEEE 1987
- Generating Incremental VLSI Compaction Spacing Constraints, ACM/IEEE 1987
- Active Substrate System Integration 1987
- Toriodal Compaction of Symbolic Layouts for Regular Structures 1987
- An Overview of the MIPS-X-MP Project Stanford University, Technical Report 1986: CSL-TR-86-300
- An Analytical Cache Model Stanford University, Technical Report 1986: CSL-TR-86-304
- ATUM: A New Technique for Capturing Address Traces Using Microcode 1986
- SRT Division Diagrams and Their Usage in Designing Custom Integrated Circuits for Division Stanford University, Technical Report 1986: CSL-TR-87-326
- The MIPS-X Microprocessor WESCON 1985, San Francisco, CA Published by Electronic Conventions Management, USA, Distributed by Western Periodicals Co, North Hollywood, CA. 1985: 6. 1
- An Automated Pressure Regulator Review of Scientific Instruments 1984; 55 (9): 1467-1470
- A Low Cost Laser Interferometer System for Machine Tool Applications Precision Engineering 1983; 5 (1): 29-31
- Resistance Extraction from Mask Layout Data IEEE Transactions on Computer-Aided Design 1983; CAD-2 (3): 145-150
- Timing Models for MOS Pass Nets 1983
- Signal Delay in RC Tree Networks IEEE Transactions on Computer-Aided Design 1983; CAD-2 (3): 202-211
- Timing Models for MOS Circuits Stanford University, Ph.D. Thesis, Dec. 1983. Also appears as Stanford University, Technical Report 1983: SEL-83-003
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A 14 BIT DUAL-RAMP DAC FOR DIGITAL-AUDIO SYSTEMS
IEEE JOURNAL OF SOLID-STATE CIRCUITS
1982; 17 (6): 1118-1126
View details for Web of Science ID A1982QA62700020
- A 14 Bit Dual Ramp DAC for Digital Audio IEEE Journal of Solid-State Circuits, Shorter version in Proceedings of International Solid-State Circuits Conference (ISSCC), San Francisco, CA 1982; SC-17 (6): 86-87
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MEASUREMENT OF SERIES COLLECTOR RESISTANCE IN BIPOLAR-TRANSISTORS
IEEE JOURNAL OF SOLID-STATE CIRCUITS
1982; 17 (4): 767-773
View details for Web of Science ID A1982PB83700019
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A 14B PCM DAC
ISSCC DIGEST OF TECHNICAL PAPERS
1982; 25: 86-?
View details for Web of Science ID A1982NY99400032
- Critical Anomaly in the Dielectric Constant of a Non-polar Pure Fluid Phy Rev Letters 1976; 37 (15): 964-967
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Why Design Must Change: Rethinking Digital Design
Micro, IEEE
; PP (99): 1-1
View details for DOI 10.1109/MM.2010.81
- Analyzing CMOS Power Supply Networks Using Ariel, ACM/IEEE
- Measurement of Supply Pin Current Distributions in Integrated Circuit Packages
- Nondestructive Readout Architecture for a Kinetic Inductance Memory Cell 1992, 1993
- SPIM: A Pipelined 64 x 64 Bit Iterative Multiplier 1989, 1988
- Limits on Multiple Instruction Issue 1989, 1990