Bio


Professor Horowitz's initial work focused on designing high-performance digital systems by combining work in computer-aided design tools, circuit design, and system architecture. Dr. Horowitz's current research interests are quite broad and span using EE and CS analysis methods to problems in molecular biology to creating new design methodologies for analog and digital VLSI circuits. He has worked on many processor designs, from early RISC chips, to creating some of the first distributed shared memory multiprocessors, and is currently working on on-chip multiprocessor designs. Recently he has worked on a number of problems in computational photography. In 1990, he took leave from Stanford to help start Rambus Inc., a company designing high-bandwidth memory interface technology, and has continued work in high-speed I/O at Stanford. His current research includes updating both analog and digital design methods, low energy multiprocessor designs, computational photography, and applying engineering to biology.

Academic Appointments


Honors & Awards


  • Elected Fellow, IEEE
  • Elected Fellow, Association for Computing Machinery
  • Jack Kilby Outstanding Paper Award, ISSCC (2003)
  • Most Influential Paper, International Symposium on Computer Architecture (1989)
  • Best Paper Award, ISQED (2005)
  • Donald O. Pederson Technical Field Award, IEEE (2006)
  • Most influential paper, International Symposium of Computer Arch (1994)
  • Faculty Researcher Award, SIA (2010)

Boards, Advisory Committees, Professional Organizations


  • Member, National Academy of Engineering (2013 - Present)
  • Member, American Academy of Arts and Sciences (2013 - Present)

Professional Education


  • PhD, Stanford University (1984)
  • MS, MIT (1978)
  • BS, MIT (1978)

2013-14 Courses


Postdoctoral Advisees


Journal Articles


  • Why Design Must Change: Rethinking Digital Design Micro, IEEE Shacham, O., Azizi, O., Wachs, M., Richardson, S., Horowitz, M. ; PP (99): 1-1

    View details for DOI 10.1109/MM.2010.81

  • GABAergic Lateral Interactions Tune the Early Stages of Visual Processing in Drosophila NEURON Freifeld, L., Clark, D. A., Schnitzer, M. J., Horowitz, M. A., Clandinin, T. R. 2013; 78 (6): 1075-1089

    Abstract

    Early stages of visual processing must capture complex, dynamic inputs. While peripheral neurons often implement efficient encoding by exploiting natural stimulus statistics, downstream neurons are specialized to extract behaviorally relevant features. How do these specializations arise? We use two-photon imaging in Drosophila to characterize a first-order interneuron, L2, that provides input to a pathway specialized for detecting moving dark edges. GABAergic interactions, mediated in part presynaptically, create an antagonistic and anisotropic center-surround receptive field. This receptive field is spatiotemporally coupled, applying differential temporal processing to large and small dark objects, achieving significant specialization. GABAergic circuits also mediate OFF responses and balance these with responses to ON stimuli. Remarkably, the functional properties of L2 are strikingly similar to those of bipolar cells, yet emerge through different molecular and circuit mechanisms. Thus, evolution appears to have converged on a common strategy for processing visual information at the first synapse.

    View details for DOI 10.1016/j.neuron.2013.04.024

    View details for Web of Science ID 000321026900013

    View details for PubMedID 23791198

  • Microfluidic serial digital to analog pressure converter for arbitrary pressure generation and contamination-free flow control LAB ON A CHIP Yu, F., Horowitz, M. A., Quake, S. R. 2013; 13 (10): 1911-1918

    Abstract

    Multilayer microfluidics based on PDMS (polydimethylsiloxane) soft lithography have offered parallelism and integration for biological and chemical sciences, where reduction in reaction volume and consistency of controlled variables across experiments translate into reduced cost, increased quantity and quality of data. One issue with push up or push down microfluidic control concept is the inability to provide multiple control pressures without adding more complex and expensive external pressure controls. We present here a microfluidic serial DAC (Digital to Analog Converter) that can be integrated with any PDMS device to expand the device's functionality by effectively adding an on-chip pressure regulator. The microfluidic serial DAC can be used with any incompressible fluids and operates in a similar fashion compared to an electronic serial DAC. It can be easily incorporated into any existing multilayer microfluidic devices, and the output pressure that the device generates could be held for extensive times. We explore in this paper various factors that affect resolution, speed, and linearity of the DAC output. As an application, we demonstrate microfluidic DAC's ability for on-chip manipulation of flow resistance when integrated with a simple flow network. In addition, we illustrate an added advantage of using the microfluidic serial DAC in preventing back flow and possible contamination.

    View details for DOI 10.1039/c3lc41394b

    View details for Web of Science ID 000317937300011

    View details for PubMedID 23529280

  • The Frankencamera: An Experimental Platform for Computational Photography COMMUNICATIONS OF THE ACM Adams, A., Jacobs, D. E., Dolson, J., Tico, M., Pulli, K., Talvala, E., Ajdin, B., Vaquero, D., Lensch, H. P., Horowitz, M., Park, S. H., Gelfand, N., Baek, J., Matusik, W., Levoy, M. 2012; 55 (11): 90-98
  • Bringing Up a Chip on the Cheap IEEE DESIGN & TEST OF COMPUTERS Wachs, M., Shacham, O., Asgar, Z., Firoozshahian, A., Richardson, S., Horowitz, M. 2012; 29 (6): 57-65
  • Removing high contrast artifacts via digital inpainting in cryo-electron tomography: An application of compressed sensing JOURNAL OF STRUCTURAL BIOLOGY Song, K., Comolli, L. R., Horowitz, M. 2012; 178 (2): 108-120

    Abstract

    To cope with poor quality in cryo-electron tomography images, electron-dense markers, such as colloidal goldbeads, are often used to assist image registration and analysis algorithms. However, these markers can create artifacts that occlude a specimen due to their high contrast, which can also cause failure of some image processing algorithms. One way of reducing these artifacts is to replace high contrast objects with pixel densities that blend into the surroundings in the projection domain before volume reconstruction. In this paper, we propose digital inpainting via compressed sensing (CS) as a new method to achieve this goal. We show that cryo-ET projections are sparse in the discrete cosine transform (DCT) domain, and, by finding the sparsest DCT domain decompositions given uncorrupted pixels, we can fill in the missing pixel values that are occluded by high contrast objects without discontinuities. Our method reduces visual artifacts both in projections and in tomograms better than conventional algorithms, such as polynomial interpolation and random noise inpainting.

    View details for DOI 10.1016/j.jsb.2012.01.003

    View details for Web of Science ID 000304287400006

    View details for PubMedID 22248454

  • CMOS Image Sensors With Multi-Bucket Pixels for Computational Photography IEEE JOURNAL OF SOLID-STATE CIRCUITS Wan, G., Li, X., Agranov, G., Levoy, M., Horowitz, M. 2012; 47 (4): 1031-1042
  • CPU DB: Recording Microprocessor History COMMUNICATIONS OF THE ACM Danowitz, A., Kelley, K., Mao, J., Stevenson, J. P., Horowitz, M. 2012; 55 (4): 55-63
  • Avoiding Game Over: Bringing Design to the Next Level 2012 49TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC) Shacham, O., Galal, S., Sankaranarayanan, S., Wachs, M., Brunhaver, J., Vassiliev, A., Horowitz, M., Danowitz, A., Qadeer, W., Richardson, S. 2012: 623-629
  • Removing Overhead From High-Level Interfaces 2012 49TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC) Kelly, K., Wachs, M., Stevenson, J., Richardson, S., Horowitz, M. 2012: 783-789
  • Towards Energy-Proportional Datacenter Memory with Mobile DRAM 2012 39TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE (ISCA) Malladi, K. T., Nothaft, F. A., Periyathambi, K., Lee, B. C., Kozyrakis, C., Horowitz, M. 2012: 37-48
  • Understanding Sources of Inefficiency in General-Purpose Chips COMMUNICATIONS OF THE ACM Hameed, R., Qadeer, W., Wachs, M., Azizi, O., Solomatnikov, A., Lee, B. C., Richardson, S., Kozyrakis, C., Horowitz, M. 2011; 54 (10): 85-93
  • Energy-Efficient Floating-Point Unit Design IEEE TRANSACTIONS ON COMPUTERS Galal, S., Horowitz, M. 2011; 60 (7): 913-922
  • Defining the Computational Structure of the Motion Detector in Drosophila NEURON Clark, D. A., Bursztyn, L., Horowitz, M. A., Schnitzer, M. J., Clandinin, T. R. 2011; 70 (6): 1165-1177

    Abstract

    Many animals rely on visual motion detection for survival. Motion information is extracted from spatiotemporal intensity patterns on the retina, a paradigmatic neural computation. A phenomenological model, the Hassenstein-Reichardt correlator (HRC), relates visual inputs to neural activity and behavioral responses to motion, but the circuits that implement this computation remain unknown. By using cell-type specific genetic silencing, minimal motion stimuli, and in vivo calcium imaging, we examine two critical HRC inputs. These two pathways respond preferentially to light and dark moving edges. We demonstrate that these pathways perform overlapping but complementary subsets of the computations underlying the HRC. A numerical model implementing differential weighting of these operations displays the observed edge preferences. Intriguingly, these pathways are distinguished by their sensitivities to a stimulus correlation that corresponds to an illusory percept, "reverse phi," that affects many species. Thus, this computational architecture may be widely used to achieve edge selectivity in motion detection.

    View details for DOI 10.1016/j.neuron.2011.05.023

    View details for Web of Science ID 000292410700014

    View details for PubMedID 21689602

  • Cortical representations of olfactory input by trans-synaptic tracing NATURE Miyamichi, K., Amat, F., Moussavi, F., Wang, C., Wickersham, I., Wall, N. R., Taniguchi, H., Tasic, B., Huang, Z. J., He, Z., Callaway, E. M., Horowitz, M. A., Luo, L. 2011; 472 (7342): 191-196

    Abstract

    In the mouse, each class of olfactory receptor neurons expressing a given odorant receptor has convergent axonal projections to two specific glomeruli in the olfactory bulb, thereby creating an odour map. However, it is unclear how this map is represented in the olfactory cortex. Here we combine rabies-virus-dependent retrograde mono-trans-synaptic labelling with genetics to control the location, number and type of 'starter' cortical neurons, from which we trace their presynaptic neurons. We find that individual cortical neurons receive input from multiple mitral cells representing broadly distributed glomeruli. Different cortical areas represent the olfactory bulb input differently. For example, the cortical amygdala preferentially receives dorsal olfactory bulb input, whereas the piriform cortex samples the whole olfactory bulb without obvious bias. These differences probably reflect different functions of these cortical areas in mediating innate odour preference or associative memory. The trans-synaptic labelling method described here should be widely applicable to mapping connections throughout the mouse nervous system.

    View details for DOI 10.1038/nature09714

    View details for Web of Science ID 000289469100036

    View details for PubMedID 21179085

  • Energy-efficient floating point unit design Computers, IEEE Transactions on Galal, S., Horowitz, M. 2011; 99: 1-1
  • Latency Sensitive FMA Design 2011 20TH IEEE SYMPOSIUM ON COMPUTER ARITHMETIC (ARITH-20) Galal, S., Horowitz, M. 2011: 129-138
  • Global convergence analysis of mixed-signal systems Design Automation Conference (DAC) Youn, S., Kim, J., Horowitz, M. 2011: 498-503
  • Analog signal multiplexing for PSAPD-based PET detectors: simulation and experimental validation PHYSICS IN MEDICINE AND BIOLOGY Lau, F. W., Vandenbroucke, A., Reynolds, P. D., Olcott, P. D., Horowitz, M. A., Levin, C. S. 2010; 55 (23): 7149-7174

    Abstract

    A 1 mm(3) resolution clinical positron emission tomography (PET) system employing 4608 position-sensitive avalanche photodiodes (PSAPDs) is under development. This paper describes a detector multiplexing technique that simplifies the readout electronics and reduces the density of the circuit board design. The multiplexing scheme was validated using a simulation framework that models the PSAPDs and front-end multiplexing circuits to predict the signal-to-noise ratio and flood histogram performance. Two independent experimental setups measured the energy resolution, time resolution, crystal identification ability and count rate both with and without multiplexing. With multiplexing, there was no significant degradation in energy resolution, time resolution and count rate. There was a relative 6.9 ± 1.0% and 9.4 ± 1.0% degradation in the figure of merit that characterizes the crystal identification ability observed in the measured and simulated ceramic-mounted PSAPD module flood histograms, respectively.

    View details for DOI 10.1088/0031-9155/55/23/001

    View details for Web of Science ID 000284261000015

    View details for PubMedID 21081831

  • Analysis of the Intact Surface Layer of Caulobacter crescentus by Cryo-Electron Tomography JOURNAL OF BACTERIOLOGY Amat, F., Comolli, L. R., Nomellini, J. F., Moussavi, F., Downing, K. H., Smit, J., Horowitz, M. 2010; 192 (22): 5855-5865

    Abstract

    The surface layers (S layers) of those bacteria and archaea that elaborate these crystalline structures have been studied for 40 years. However, most structural analysis has been based on electron microscopy of negatively stained S-layer fragments separated from cells, which can introduce staining artifacts and allow rearrangement of structures prone to self-assemble. We present a quantitative analysis of the structure and organization of the S layer on intact growing cells of the Gram-negative bacterium Caulobacter crescentus using cryo-electron tomography (CET) and statistical image processing. Instead of the expected long-range order, we observed different regions with hexagonally organized subunits exhibiting short-range order and a broad distribution of periodicities. Also, areas of stacked double layers were found, and these increased in extent when the S-layer protein (RsaA) expression level was elevated by addition of multiple rsaA copies. Finally, we combined high-resolution amino acid residue-specific Nanogold labeling and subtomogram averaging of CET volumes to improve our understanding of the correlation between the linear protein sequence and the structure at the 2-nm level of resolution that is presently available. The results support the view that the U-shaped RsaA monomer predicted from negative-stain tomography proceeds from the N terminus at one vertex, corresponding to the axis of 3-fold symmetry, to the C terminus at the opposite vertex, which forms the prominent 6-fold symmetry axis. Such information will help future efforts to analyze subunit interactions and guide selection of internal sites for display of heterologous protein segments.

    View details for DOI 10.1128/JB.00747-10

    View details for Web of Science ID 000283559300001

    View details for PubMedID 20833802

  • RETHINKING DIGITAL DESIGN: WHY DESIGN MUST CHANGE IEEE MICRO Shacham, O., Azizi, O., Wachs, M., Qadeer, W., Asgar, Z., Kelley, K., Stevenson, J. P., Richardson, S., Horowitz, M., Lee, B., Solomatnikov, A., Firoozshahian, A. 2010; 30 (6): 9-24
  • Subtomogram alignment by adaptive Fourier coefficient thresholding JOURNAL OF STRUCTURAL BIOLOGY Amat, F., Comolli, L. R., Moussavi, F., Smit, J., Downing, K. H., Horowitz, M. 2010; 171 (3): 332-344

    Abstract

    In the past few years, three-dimensional (3D) subtomogram alignment has become an important tool in cryo-electron tomography (CET). This technique allows one to produce higher resolution images of structures which can not be reconstructed using single-particle methods. Building on previous work, we present a new dissimilarity measure between subtomograms that works well for the noisy images that often occur in CET images. A technique that is more robust to noise provides the ability to analyze macromolecules in thicker samples such as whole cells or lower the defocus in thinner samples to push the first zero of the Contrast Transfer Function (CTF). Our method, Threshold Constrained Cross-Correlation (TCCC), uses statistics of the noise to automatically select only a small percentage of the Fourier coefficients to compute the cross-correlation, which has two main advantages: first, it reduces the influence of the noise by looking at only those peaks dominated by signal; and second, it avoids the missing wedge normalization problem since we consider the same number of coefficients for all possible pairs of subtomograms. We present results with synthetic and real data to compare our approach with other existing methods under different SNR and missing wedge conditions, and show that TCCC improves alignment results for datasets with SNR<0.1. We have made our source code freely available for the community.

    View details for DOI 10.1016/j.jsb.2010.05.013

    View details for Web of Science ID 000280680100010

    View details for PubMedID 20621702

  • The Frankencamera: An Experimental Platform for Computational Photography ACM TRANSACTIONS ON GRAPHICS Adams, A., Jacobs, D. E., Dolson, J., Tico, M., Pulli, K., Talvala, E., Ajdin, B., Vaquero, D., Lensch, H. P., Horowitz, M., Park, S. H., Gelfand, N., Baek, J., Matusik, W., Levoy, M. 2010; 29 (4)
  • Fast, Non-Monte-Carlo Estimation of Transient Performance Variation Due to Device Mismatch IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS Kim, J., Jones, K. D., Horowitz, M. A. 2010; 57 (7): 1746-1755
  • 3D segmentation of cell boundaries from whole cell cryogenic electron tomography volumes JOURNAL OF STRUCTURAL BIOLOGY Moussavi, F., Heitz, G., Amat, F., Comolli, L. R., Koller, D., Horowitz, M. 2010; 170 (1): 134-145

    Abstract

    Cryogenic electron tomography (cryo-ET) has gained increasing interest in recent years due to its ability to image whole cells and subcellular structures in 3D at nanometer resolution in their native environment. However, due to dose restrictions and the inability to acquire high tilt angle images, the reconstructed volumes are noisy and have missing information. Thus, features are unreliable, and precision extraction of the cell boundary is difficult, manual and time intensive. This paper presents an efficient recursive algorithm called BLASTED (Boundary Localization using Adaptive Shape and Texture Discovery) to automatically extract the cell boundary using a conditional random field (CRF) framework in which boundary points and shape are jointly inferred. The algorithm learns the texture of the boundary region progressively, and uses a global shape model and shape-dependent features to propose candidate boundary points on a slice of the membrane. It then updates the shape of that slice by accepting the appropriate candidate points using local spatial clustering, the global shape model, and trained boosted texture classifiers. The BLASTED algorithm segmented the cell membrane over an average of 93% of the length of the cell in 19 difficult cryo-ET datasets.

    View details for DOI 10.1016/j.jsb.2009.12.015

    View details for Web of Science ID 000276329600016

    View details for PubMedID 20035877

  • Static control logic for microfluidic devices using pressure-gain valves NATURE PHYSICS Weaver, J. A., Melin, J., Stark, D., Quake, S. R., Horowitz, M. A. 2010; 6 (3): 218-223

    View details for DOI 10.1038/NPHYS1513

    View details for Web of Science ID 000275024000024

  • Timing Robustness in the Budding and Fission Yeast Cell Cycles PLOS ONE Mangla, K., Dill, D. L., Horowitz, M. A. 2010; 5 (2)

    Abstract

    Robustness of biological models has emerged as an important principle in systems biology. Many past analyses of Boolean models update all pending changes in signals simultaneously (i.e., synchronously), making it impossible to consider robustness to variations in timing that result from noise and different environmental conditions. We checked previously published mathematical models of the cell cycles of budding and fission yeast for robustness to timing variations by constructing Boolean models and analyzing them using model-checking software for the property of speed independence. Surprisingly, the models are nearly, but not totally, speed-independent. In some cases, examination of timing problems discovered in the analysis exposes apparent inaccuracies in the model. Biologically justified revisions to the model eliminate the timing problems. Furthermore, in silico random mutations in the regulatory interactions of a speed-independent Boolean model are shown to be unlikely to preserve speed independence, even in models that are otherwise functional, providing evidence for selection pressure to maintain timing robustness. Multiple cell cycle models exhibit strong robustness to timing variation, apparently due to evolutionary pressure. Thus, timing robustness can be a basis for generating testable hypotheses and can focus attention on aspects of a model that may need refinement.

    View details for DOI 10.1371/journal.pone.0008906

    View details for Web of Science ID 000274209700002

    View details for PubMedID 20126540

  • ALIGNMENT OF CRYO-ELECTRON TOMOGRAPHY DATASETS METHODS IN ENZYMOLOGY, VOL 482: CRYO-EM, PART B: 3-D RECONSTRUCTION Amat, F., Castano-Diez, D., Lawrence, A., Moussavi, F., Winkler, H., Horowitz, M. 2010; 482: 343-367

    Abstract

    Data acquisition of cryo-electron tomography (CET) samples described in previous chapters involves relatively imprecise mechanical motions: the tilt series has shifts, rotations, and several other distortions between projections. Alignment is the procedure of correcting for these effects in each image and requires the estimation of a projection model that describes how points from the sample in three-dimensions are projected to generate two-dimensional images. This estimation is enabled by finding corresponding common features between images. This chapter reviews several software packages that perform alignment and reconstruction tasks completely automatically (or with minimal user intervention) in two main scenarios: using gold fiducial markers as high contrast features or using relevant biological structures present in the image (marker-free). In particular, we emphasize the key decision points in the process that users should focus on in order to obtain high-resolution reconstructions.

    View details for DOI 10.1016/S0076-6879(10)82014-2

    View details for Web of Science ID 000283462200013

    View details for PubMedID 20888968

  • Understanding Sources of Inefficiency in General-Purpose Chips ISCA 2010: THE 37TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE Hameed, R., Qadeer, W., Wachs, M., Azizi, O., Solomatnikov, A., Lee, B. C., Richardson, S., Kozyrakis, C., Horowitz, M. 2010: 37-47
  • Energy-Performance Tradeoffs in Processor Architecture and Circuit Design: A Marginal Cost Analysis ISCA 2010: THE 37TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE Azizi, O., Mahesri, A., Lee, B. C., Patel, S. J., Horowitz, M. 2010: 26-36
  • 2010 Timing Robustness in the Budding and Fission Yeast Cell Cycles.  PLoS ONE K, M., DL, D., A, H. M. 2010; 2 (5): e8906
  • Energy-Performance Tunable Logic IEEE JOURNAL OF SOLID-STATE CIRCUITS Nezamfar, B., Alon, E., Horowitz, M. 2009; 44 (9): 2554-2567
  • On-Die Power Supply Noise Measurement Techniques IEEE TRANSACTIONS ON ADVANCED PACKAGING Alon, E., Abramzon, V., Nezamfar, B., Horowitz, M. 2009; 32 (2): 248-259
  • Area-efficiency in CMP core design: co-optimization of microarchitecture and physical design SIGARCH Comput. Archit. New Azizi, O., Mahesri, A., Patel, S., J., Horowitz, M. 2009; 37 (2): 56-65

    View details for DOI 10.1145/1577129.1577138

  • Energy-Performance Tunable Logic PROCEEDINGS OF THE IEEE 2009 CUSTOM INTEGRATED CIRCUITS CONFERENCE Nezamfar, B., Horowitz, M. 2009: 183-186
  • A Memory System Design Framework: Creating Smart Memories ISCA 2009: 36TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE Firoozshahian, A., Solomatnikov, A., Shacham, O., Asgar, Z., Richardson, S., Kozyrakis, C., Horowitz, M. 2009: 406-417
  • Front-End Electronics for a 1 mm(3) Resolution Avalanche Photodiode-Based PET System with Analog Signal Multiplexing 2008 IEEE NUCLEAR SCIENCE SYMPOSIUM AND MEDICAL IMAGING CONFERENCE (2008 NSS/MIC), VOLS 1-9 Lau, F. W., Vandenbroucke, A., Reynolds, P. D., Olcott, P. D., Horowitz, M. A., Levin, C. S. 2009: 3146-3149
  • IN FIELD, ENERGY-PERFORMANCE TUNABLE FPGA ARCHITECTURES FPL: 2009 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS Nezamfar, B., Horowitz, M. 2009: 262-267
  • Stochastic Steady-State and AC Analyses of Mixed-Signal Systems DAC: 2009 46TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2 Kim, J., Ren, J., Horowitz, M. A. 2009: 376-381
  • Leveraging Designer's Intent: A Path Toward Simpler Analog CAD Tools PROCEEDINGS OF THE IEEE 2009 CUSTOM INTEGRATED CIRCUITS CONFERENCE Kim, J., Jeeradit, M., Lim, B., Horowitz, M. A. 2009: 613-620
  • 1 mm(3) Resolution Breast-Dedicated PET System 2008 IEEE NUCLEAR SCIENCE SYMPOSIUM AND MEDICAL IMAGING CONFERENCE (2008 NSS/MIC), VOLS 1-9 Lau, F. W., Fang, C., Reynolds, P. D., Olcott, P. D., Vandenbroucke, A., Spanoudaki, V. C., Olutade, F., Horowitz, M. A., Levin, C. S. 2009: 5378-5381
  • Comparative Evaluation of Memory Models for Chip Multiprocessors ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION Leverich, J., Arakida, H., Solomatnikov, A., Firoozshahian, A., Horowitz, M., Kozyrakis, C. 2008; 5 (3)
  • Architecture and inherent robustness of a bacterial cell-cycle control system PROCEEDINGS OF THE NATIONAL ACADEMY OF SCIENCES OF THE UNITED STATES OF AMERICA Shen, X., Collier, J., Dill, D., Shapiro, L., Horowitz, M., McAdams, H. H. 2008; 105 (32): 11340-11345

    Abstract

    A closed-loop control system drives progression of the coupled stalked and swarmer cell cycles of the bacterium Caulobacter crescentus in a near-mechanical step-like fashion. The cell-cycle control has a cyclical genetic circuit composed of four regulatory proteins with tight coupling to processive chromosome replication and cell division subsystems. We report a hybrid simulation of the coupled cell-cycle control system, including asymmetric cell division and responses to external starvation signals, that replicates mRNA and protein concentration patterns and is consistent with observed mutant phenotypes. An asynchronous sequential digital circuit model equivalent to the validated simulation model was created. Formal model-checking analysis of the digital circuit showed that the cell-cycle control is robust to intrinsic stochastic variations in reaction rates and nutrient supply, and that it reliably stops and restarts to accommodate nutrient starvation. Model checking also showed that mechanisms involving methylation-state changes in regulatory promoter regions during DNA replication increase the robustness of the cell-cycle control. The hybrid cell-cycle simulation implementation is inherently extensible and provides a promising approach for development of whole-cell behavioral models that can replicate the observed functionality of the cell and its responses to changing environmental conditions.

    View details for DOI 10.1073/pnas.0805258105

    View details for Web of Science ID 000258560700056

    View details for PubMedID 18685108

  • Markov random field based automatic image alignment for electron tomography Journal of Structural Biology Amat, F., Moussavi, F., Comolli, L., R., Elidan, G., Downing et al, K., H. 2008; 161 (3): 260-75
  • A High-speed, Low-power 3D-SRAM Architecture PROCEEDINGS OF THE IEEE 2008 CUSTOM INTEGRATED CIRCUITS CONFERENCE Nho, H. H., Horowitz, M., Wong, S. S. 2008: 201-204
  • Processor performance modeling using symbolic simulation ISPASS 2008: IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE Azizi, O., Collins, J., Patil, D., Wang, H., Horowitz, M. 2008: 127-138
  • Verification of Chip Multiprocessor Memory Systems Using A Relaxed Scoreboard 2008 PROCEEDINGS OF THE 41ST ANNUAL IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE: MICRO-41 Shacham, O., Wachs, M., Solomatnikov, A., Firoozshahian, A., Richardson, S., Horowitz, M. 2008: 294-305
  • Circuit-level requirements for MOSFET-replacement devices Electron Devices Meeting, 2008. IEDM 2008. IEEE International Kam, H., King-Liu, T., Alon, E., Horowitz, M. 2008: 1-1
  • An optical interconnect transceiver at 1550 nm using low-voltage electroabsorption modulators directly integrated to CMOS JOURNAL OF LIGHTWAVE TECHNOLOGY Roth, J. E., Palermo, S., Helman, N. C., Bour, D. P., Miller, D. A., Horowitz, M. 2007; 25 (12): 3739-3747
  • A heuristic for optimizing stochastic activity networks with applications to statistical digital circuit sizing OPTIMIZATION AND ENGINEERING Kim, S., Boyd, S. P., Yun, S., Patil, D. D., Horowitz, M. A. 2007; 8 (4): 397-430
  • Power optimization for SRAM and its scaling IEEE TRANSACTIONS ON ELECTRON DEVICES Morifuji, E., Patil, D., Horowitz, M., Nishi, Y. 2007; 54 (4): 715-722
  • Chip multi-processor generator 2007 44TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2 Solomatnikov, A., Firoozshahian, A., Qadeer, W., Shacham, O., Kelley, K., Asgar, Z., Wachs, M., Hameed, R., Horowitz, M. 2007: 262-263
  • Comparing Memory Systems for Chip Multiprocessors ISCA'07: 34TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE, CONFERENCE PROCEEDINGS Leverich, J., Arakida, H., Solomatnikov, A., Firoozshahian, A., Horowitz, M., Kozyrakis, C. 2007: 358-368
  • Noise analysis of LSO-PSAPD PET detector front-end multiplexing circuits 2007 IEEE NUCLEAR SCIENCE SYMPOSIUM CONFERENCE RECORD, VOLS 1-11 Lau, F. W., Olcott, P. D., Horowitz, M. A., Peng, H., Levin, C. S. 2007: 3212-3219
  • Practical limits of multi-tone signaling over high-speed backplane electrical links 2007 IEEE INTERNATIONAL CONFERENCE ON COMMUNICATIONS, VOLS 1-14 Amirkhany, A., Abbasfar, A., Stojanovic, V., Horowitz, M. A. 2007: 2693-2698
  • Time-variant characterization and compensation of wideband circuits PROCEEDINGS OF THE IEEE 2007 CUSTOM INTEGRATED CIRCUITS CONFERENCE Amirkhany, A., Abbasfar, A., Savoj, J., Horowitz, M. A. 2007: 487-490
  • Robust energy-efficient adder topologies 18TH IEEE SYMPOSIUM ON COMPUTER ARITHMETIC, PROCEEDINGS Patil, D., Azizi, O., Horowitz, M., Ho, R., Ananthraman, R. 2007: 16-25
  • Measurement of supply pin current distributions in integrated circuit packages ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING Weaver, J. A., Horowitz, M. A. 2007: 7-10
  • Chip Multi-Processor Generator. DAC Solomatnikov, A., Firoozshahian, A., Qadeer, W., Shacham, O., Kelley, K., Asgar, Z., Horowitz, M. A. 2007
  • Synthetic aperture focusing using dense camera arrays 3D IMAGING FOR SAFETY AND SECURITY Vaish, V., Garg, G., Talvala, E., Antunez, E., Wilburn, B., Horowitz, M., Levoy, M. 2007; 35: 159-?
  • A new technique for characterization of digital-to-analog converters in high-speed systems 2007 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION, VOLS 1-3 Savoj, J., Abbasfar, A., Amirkhany, A., Garlepp, B. W., Horowitz, M. A. 2007: 433-438
  • A 24Gb/s software programmable multi-channel transmitter 2007 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS Amirkhany, A., Abbasfar, A., Savoj, J., Jeeradit, M., Garlepp, B., Stoianovic, V., Horowitz, M. 2007: 38-39
  • Light field microscopy ACM TRANSACTIONS ON GRAPHICS Levoy, M., Ng, R., Adams, A., Footer, M., Horowitz, M. 2006; 25 (3): 924-934
  • Replica compensated linear regulators for supply-regulated phase-locked loops IEEE JOURNAL OF SOLID-STATE CIRCUITS Alon, E., Kim, J., Pamarti, S., Chang, K., Horowitz, M. 2006; 41 (2): 413-424
  • Analog Multi-Tone Signaling for High-Speed Backplane Electrical Links GLOBECOM 2006 - 2006 IEEE GLOBAL TELECOMMUNICATIONS CONFERENCE Amirkhany, A., Abbasfar, A., Stojanovic, V., Horowitz, M. A. 2006
  • High-speed transmitters in 90nm CMOS for high-density optical interconnects ESSCIRC 2006: PROCEEDINGS OF THE 32ND EUROPEAN SOLID-STATE CIRCUITS CONFERENCE Palermo, S., Horowitz, M. 2006: 508-511
  • Measurement of via currents in printed circuit boards using inductive loops ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING Weaver, J. A., Horowitz, M. A. 2006: 37-40
  • A heuristic method for statistical digital circuit sizing DESIGN AND PROCESS INTEGRATION FOR MICROELECTRONIC MANUFACTURING IV Boyd, S., Kim, S., Patil, D., Horowitz, M. 2006; 6156

    View details for DOI 10.1117/12.657499

    View details for Web of Science ID 000238444200008

  • Compensation for multimode fiber dispersion by adaptive optics OPTICS LETTERS Shen, X. L., Kahn, J. M., Horowitz, M. A. 2005; 30 (22): 2985-2987

    Abstract

    Adaptive optics is used to compensate for modal dispersion in digital transmission through multimode fiber (MMF). At the transmitter, a spatial light modulator (SLM) controls the launched field pattern. An estimate of intersymbol interference (ISI) caused by modal dispersion is formed at the receiver and fed back to the transmitter, where the SLM is adjusted to minimize ISI. Error-free transmission of 10 Gbit/s non-return-to-zero signals through standard 50 microm graded-index MMFs up to 11.1 km long is demonstrated. It is shown that a single SLM can compensate for modal dispersion across a 600 GHz bandwidth.

    View details for Web of Science ID 000233258800005

    View details for PubMedID 16315696

  • Digital circuit optimization via geometric programming OPERATIONS RESEARCH Boyd, S. P., Kim, S. J., Patil, D. D., Horowitz, M. A. 2005; 53 (6): 899-932
  • False coupling exploration in timing analysis IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS Tseng, K., Horowitz, M. 2005; 24 (11): 1795-1805
  • On task mapping optimization for parallel decoding of low-density parity-check codes on message-passing architectures PARALLEL COMPUTING Al-Rawi, G., Cioffi, J., Horowitz, M. 2005; 31 (5): 462-490
  • High-speed videography using a dense camera array 26TH INTERNATIONAL CONGRESS ON HIGH SPEED PHOTOGRAPHY AND PHOTONICS Wilburn, B., Joshi, N., Vaish, V., Levoy, M., Horowitz, M. 2005; 5580: 913-920
  • A new method for design of robust digital circuits 6TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, PROCEEDINGS Patil, D., Yun, S. H., Kim, S. J., Cheung, A., Horowitz, M., Boyd, S. 2005: 676-681
  • Scaling, power, and the future of CMOS IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2005, TECHNICAL DIGEST Horowitz, M., Alon, E., Patil, D., Naffziger, S., Kumar, R., Bernstein, K. 2005: 11-17
  • Scalable circuits for supply noise measurement ESSCIRC 2005: PROCEEDINGS OF THE 31ST EUROPEAN SOLID-STATE CIRCUITS CONFERENCE Abramzon, V., Alon, E., Nezamfar, B., Horowitz, M. 2005: 463-466
  • Methods for true energy-performance optimization IEEE JOURNAL OF SOLID-STATE CIRCUITS Markovic, D., Stojanovic, V., Nikolic, B., Horowitz, M. A., Brodersen, R. W. 2004; 39 (8): 1282-1293
  • High-speed videography using a dense camera array PROCEEDINGS OF THE 2004 IEEE COMPUTER SOCIETY CONFERENCE ON COMPUTER VISION AND PATTERN RECOGNITION, VOL 2 Wilburn, B., Joshi, N., Vaish, V., Levoy, M., Horowitz, M. 2004: 294-301
  • Architecture and circuit techniques for a reconfigurable memory block 2004 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, DIGEST OF TECHNICAL PAPERS Mai, K., Ho, R., Alon, E., Liu, D., Kim, Y., Patil, D., Horowitz, M. 2004; 47: 500-501
  • How scaling will change processor architecture 2004 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, DIGEST OF TECHNICAL PAPERS Horowitz, M., Daily, W. 2004; 47: 132-133
  • The stream virtual machine 13TH INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURE AND COMPILATION TECHNIQUES, PROCEEDINGS Labonte, F., Mattson, P., Thies, W., Buck, I., Kozyrakis, C., Horowitz, M. 2004: 267-277
  • Equalization of modal dispersion in multimode fiber using spatial light modulators GLOBECOM '04: IEEE GLOBAL TELECOMMUNICATIONS CONFERENCE, VOLS 1-6 Alon, E., Stojanovic, V., Kahn, J. M., Boyd, S., Horowitz, M. 2004: 1023-1029
  • Optimal linear precoding with theoretical and practical data rates in high-speed serial-link backplane communication 2004 IEEE INTERNATIONAL CONFERENCE ON COMMUNICATIONS, VOLS 1-7 Stojanovic, V., Amirkhany, A., Horowitz, M. A. 2004: 2799-2806
  • Multi-tone signaling for high-speed backplane electrical links GLOBECOM '04: IEEE GLOBAL TELECOMMUNICATIONS CONFERENCE, VOLS 1-6 Amirkhany, A., Stojanovic, V., Horowitz, M. A. 2004: 1111-1117
  • CMOS transceiver with baud rate clock recovery for optical interconnects 2004 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS Emami-Neyestanak, A., Palermo, S., Lee, H. C., Horowitz, M. 2004: 410-413
  • Design of CMOS adaptive-bandwidth PLL/DLLs: A general approach IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS Kim, J., Horowitz, M. A., Wei, G. Y. 2003; 50 (11): 860-869
  • Specifying and verifying hardware for tamper-resistant software 2003 IEEE SYMPOSIUM ON SECURITY AND PRIVACY, PROCEEDINGS Lie, D., Mitchell, J., Thekkath, C. A., Horowitz, M. 2003: 166-177
  • 10GHz clock distribution using coupled standing-wave oscillators 2003 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE: DIGEST OF TECHNICAL PAPERS O'Mahony, F., Yue, C. P., Horowitz, M., Wong, S. S. 2003; 46: 428-?
  • Design of a 10GHz clock distribution network using coupled standing-wave oscillators 40TH DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2003 O'Mahony, F., Yue, C. P., Horowitz, M. A., Wong, S. S. 2003: 682-687
  • Managing wire scaling: A circuit perspective PROCEEDINGS OF THE IEEE 2003 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE Ho, R., Mai, K., Horowitz, M. 2003: 177-179
  • Efficient on-chip global interconnects 2003 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS Ho, R., Mai, K., Horowitz, M. 2003: 271-274
  • Implementing an untrusted operating system on trusted hardware. Operating Systems Review Lie, D., Thekkath, C. A., Horowitz, M. 2003; 37 (5): 178-92
  • Equalization and clock recovery for a 2.5-10-Gb/s 2-PAM/4-PAM backplane transceiver cell. IEEE Journal of Solid-State Circuits Zerbe, J., L., Werner, C., W., Stojanovic, V., Chen, F., Wei, J., Tsang, G., Horowitz, M. A. 2003; 38 (12): 2121 - 2130
  • Design of CMOS adaptive-bandwidth PLL/DLLs: a general approach. Circuits and Systems II: Analog and Digital Signal Processing IEEE Transactions on [see also Circuits and Systems II: Express Briefs, IEEE Transactions on] Kim, J., Horowitz, M., A., Wei, G. 2003; 50 (11): 860-869
  • A 10-GHz global clock distribution using coupled standing-wave oscillators Solid-State Circuits IEEE Journal of O'Mahony, F., Yue, C., P., Horowitz, M., A., Wong, S., S. 2003; 38 (11): 1813-1820
  • A 0.4-4-Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs. IEEE Journal of Solid-State Circuits Chang, K.-Y., K., Wei, J., Huang, C., Li, S., Donnelly, K., Horowitz, M. 2003; 38 (5): 747-54
  • High-frequency characterization of on-chip digital interconnects IEEE JOURNAL OF SOLID-STATE CIRCUITS Kleveland, B., Qi, X. N., Madden, L., Furusawa, T., DUTTON, R. W., Horowitz, M. A., Wong, S. S. 2002; 37 (6): 716-725
  • A serial-link transceiver based on 8-GSamples/s A/D and D/A converters in 0.25-mu m CMOS IEEE JOURNAL OF SOLID-STATE CIRCUITS Yang, C. K., Stojanovic, V., Modjtahedi, S., Horowitz, M. A., Ellersick, W. F. 2001; 36 (11): 1684-1692
  • Fast low-power decoders for RAMs IEEE JOURNAL OF SOLID-STATE CIRCUITS Amrutur, B. S., Horowitz, M. A. 2001; 36 (10): 1506-1515
  • The future of wires PROCEEDINGS OF THE IEEE Ho, R., Mai, K. W., Horowitz, M. A. 2001; 89 (4): 490-504
  • High-Speed Electrical Signaling in Design of High-Performance Microprocessor Circuits Horowitz, M., A. 2001
  • Speed and power scaling of SRAM's IEEE JOURNAL OF SOLID-STATE CIRCUITS Amrutur, B. S., Horowitz, M. A. 2000; 35 (2): 175-185
  • M. FLASH vs. (simulated) FLASH: closing the simulation loop Operating Systems Review Gibson, J., Kunz, R., Ofelt, D., Horowitz, M., Hennessy, J., Heinrich, M., FLASH 2000; 34 (5): 49-58
  • A variable-frequency parallel I/O interface with adaptive power-supply regulation. IEEE Journal of Solid-State Circuits Wei, G., Kim, J., Liu, D., Sidiropoulos, S., Horowitz, M., A. 2000; 35 (11): 1600-10
  • 64 Mbit mesochronous hybrid wave pipelined multibank DRAM macro Intelligent Memory Systems. Second International Workshop, IMS 2000. Revised Papers, Cambridge, MA, USA. Ogawa, J., Horowitz, M., A. 2000
  • Timing analysis including clock skew IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS Harris, D., Horowitz, M., Liu, D. 1999; 18 (11): 1608-1618
  • A fully digital, energy-efficient, adaptive power-supply regulator IEEE JOURNAL OF SOLID-STATE CIRCUITS Wei, G. Y., Horowitz, M. 1999; 34 (4): 520-528
  • Low-power dividerless frequency synthesis using aperture phase detection IEEE JOURNAL OF SOLID-STATE CIRCUITS Shahani, A. R., Shaeffer, D. K., Mohan, S. S., Samavati, H., Rategh, H. R., Hershenson, M. D., Xu, M., Yue, C. P., Eddleman, D. J., Horowitz, M. A., Lee, T. N. 1998; 33 (12): 2232-2239
  • Low-power SRAM design using half-swing pulse-mode techniques IEEE JOURNAL OF SOLID-STATE CIRCUITS Mai, K. W., Mori, T., Amrutur, B. S., Ho, R., Wilburn, B., Horowitz, M. A., Fukushi, I., Izawa, T., Mitarai, S. 1998; 33 (11): 1659-1671
  • A replica technique for wordline and sense control in low-power SRAM's IEEE JOURNAL OF SOLID-STATE CIRCUITS Amrutur, B. S., Horowitz, M. A. 1998; 33 (8): 1208-1219
  • Informing memory operations: Memory performance feedback mechanisms and their applications ACM TRANSACTIONS ON COMPUTER SYSTEMS Horowitz, M., Martonosi, M., Mowry, T. C., Smith, M. D. 1998; 16 (2): 170-205
  • High-speed electrical signaling: Overview and limitations IEEE MICRO Horowitz, M., Yang, C. K., Sidiropoulos, S. 1998; 18 (1): 12-24
  • Approximate reachability with BDDs using overlapping projections 1998 DESIGN AUTOMATION CONFERENCE, PROCEEDINGS Govindaraju, S. G., Dill, D. L., Hu, A. J., Horowitz, M. A. 1998: 451-456
  • A semidigital dual delay-locked loop IEEE JOURNAL OF SOLID-STATE CIRCUITS Sidiropoulos, S., Horowitz, M. A. 1997; 32 (11): 1683-1692
  • Skew-tolerant domino circuits IEEE JOURNAL OF SOLID-STATE CIRCUITS Harris, D., Horowitz, M. A. 1997; 32 (11): 1702-1711
  • Circuit techniques for 1.5-V power supply flash memory IEEE JOURNAL OF SOLID-STATE CIRCUITS Otsuka, N., Horowitz, M. A. 1997; 32 (8): 1217-1230
  • Supply and threshold voltage scaling for low power CMOS IEEE JOURNAL OF SOLID-STATE CIRCUITS GONZALEZ, R., Gordon, B. M., Horowitz, M. A. 1997; 32 (8): 1210-1216
  • A 700-Mb/s/pin CMOS signaling interface wing current integrating receivers IEEE JOURNAL OF SOLID-STATE CIRCUITS Sidiropoulos, S., Horowitz, M. 1997; 32 (5): 681-690
  • Hardware/software co-design of the Stanford FLASH multiprocessor PROCEEDINGS OF THE IEEE Heinrich, M., Ofelt, D., Horowitz, M. A., Hennessy, J. 1997; 85 (3): 455-466
  • A 0.6 mu m CMOS 4Gb/s transceiver with data recovery using oversampling 1997 SYMPOSIUM ON VLSI CIRCUITS Yang, C. K., FarjadRad, R., Horowitz, M. 1997: 71-72
  • Energy dissipation in general purpose microprocessors IEEE JOURNAL OF SOLID-STATE CIRCUITS GONZALEZ, R., Horowitz, M. 1996; 31 (9): 1277-1284
  • Regenerative feedback repeaters for programmable interconnections IEEE JOURNAL OF SOLID-STATE CIRCUITS Dobbelaere, I., Horowitz, M., Elgamal, A. 1995; 30 (11): 1246-1253
  • Informing Loads: Enabling Software to Observe and React to Memory Behavior Stanford University, Technical Report Horowitz, M., Martonosi, M., Mowry, T., C., Smith, M., D. 1995: CSL-TR-95-673
  • Array-of-arrays Architecture for Parallel Floating Point Multiplication Advanced Research in VLSI Dhanesha, H., Falakshahi, K., Horowitz, M. 1995: 150-157
  • TIMING ANALYSIS FOR PIECEWISE-LINEAR RSIM IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS Kao, R., Horowitz, M. 1994; 13 (12): 1498-1512
  • SELF-TIMED LOGIC USING CURRENT-SENSING COMPLETION DETECTION (CSCD) JOURNAL OF VLSI SIGNAL PROCESSING Dean, M. E., Dill, D. L., Horowitz, M. 1994; 7 (1-2): 7-16
  • PRECISE DELAY GENERATION USING COUPLED OSCILLATORS IEEE JOURNAL OF SOLID-STATE CIRCUITS Maneatis, J. G., Horowitz, M. A. 1993; 28 (12): 1273-1282
  • THE DESIGN OF A HIGH-PERFORMANCE CACHE CONTROLLER - A CASE-STUDY IN ASYNCHRONOUS SYNTHESIS INTEGRATION-THE VLSI JOURNAL Nowick, S. M., Dean, M. E., Dill, D. L., Horowitz, M. 1993; 15 (3): 241-262
  • EFFICIENT SUPERSCALAR PERFORMANCE THROUGH BOOSTING SIGPLAN NOTICES Smith, M. D., Horowitz, M., Lam, M. S. 1992; 27 (9): 248-259
  • CIRCUIT TECHNIQUES FOR LARGE CSEA SRAMS IEEE JOURNAL OF SOLID-STATE CIRCUITS WINGARD, D. E., Stark, D. C., Horowitz, M. A. 1992; 27 (6): 908-919
  • THE STANFORD DASH MULTIPROCESSOR COMPUTER Lenoski, D., LAUDON, J., Gharachorloo, K., Weber, W. D., Gupta, A., Hennessy, J., Horowitz, M., Lam, M. S. 1992; 25 (3): 63-79
  • Circuit Techniques for Large CSEA SRAM's IEEE Journal of Solid-State Circuits Wingard, D., E., Stark, D., C., Horowitz, M., A. 1992; 27 (6): 908-919
  • A ZERO-OVERHEAD SELF-TIMED 160-NS 54-B CMOS DIVIDER IEEE JOURNAL OF SOLID-STATE CIRCUITS Williams, T. E., Horowitz, M. A. 1991; 26 (11): 1651-1661
  • Asymptotic Waveform Evaluation for Circuits With Redundant DC Equations Stanford University, Technical Report Kao, R., Horowitz, M. 1991: CSL-TR-91-478
  • Efficient Moment-Based Timing Analysis for Variable Accuracy Switch Level Simulation Stanford University, Technical Report Kao, R., Horowitz, M. 1991: CSL-TR-91-468
  • Dynamic Pointer Allocation for Scalable Cache Coherence Directories Stanford University, Technical Report Simoni, R., Horowitz, M. 1991: CSL-TR-91-491
  • A 4-NS BICMOS TRANSLATION-LOOKASIDE BUFFER IEEE JOURNAL OF SOLID-STATE CIRCUITS TAMURA, L. R., Yang, T. S., WINGARD, D. E., Horowitz, M. A., Wooley, B. A. 1990; 25 (5): 1093-1101
  • TECHNIQUES FOR CALCULATING CURRENTS AND VOLTAGES IN VLSI POWER-SUPPLY NETWORKS IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS Stark, D., Horowitz, M. 1990; 9 (2): 126-132
  • Boosting Beyond Static Scheduling in a Superscalar Processor Stanford University, Technical Report Smith, M., D., Lam, M., S., Horowitz, M., A. 1990: CSL-TR-90-434
  • Limits on Multiple Instruction Issue Stanford University, Technical Report Smith, M., D., Johnson, M., Horowitz, M., A. 1990: CSL-TR-90-433
  • AN ANALYTICAL CACHE MODEL ACM TRANSACTIONS ON COMPUTER SYSTEMS Agarwal, A., Horowitz, M., Hennessy, J. 1989; 7 (2): 184-215
  • SPIM - A PIPELINED 64 X 64-BIT ITERATIVE MULTIPLIER IEEE JOURNAL OF SOLID-STATE CIRCUITS Santoro, M. R., Horowitz, M. A. 1989; 24 (2): 487-493
  • Design of the Stanford Dash Multiprocessor Stanford University, Technical Report Lenoski, D., Laudon, J., Gharachorloo, K., Gupta, A., Hennessy, J., Horowitz, M. 1989: CSL-TR-89-403
  • CACHE PERFORMANCE OF OPERATING SYSTEM AND MULTIPROGRAMMING WORKLOADS ACM TRANSACTIONS ON COMPUTER SYSTEMS Agarwal, A., Hennessy, J., Horowitz, M. 1988; 6 (4): 393-431
  • A 4-NS 4K X 1-BIT 2-PORT BICMOS SRAM IEEE JOURNAL OF SOLID-STATE CIRCUITS Yang, T. S., Horowitz, M. A., Wooley, B. A. 1988; 23 (5): 1030-1040
  • SPECIAL ISSUE ON LOGIC AND MEMORY - FOREWORD IEEE JOURNAL OF SOLID-STATE CIRCUITS Shah, A. H., Horowitz, M. A. 1988; 23 (5): 1028-1029
  • Generalization in Digital Functions International Neural Network Society 1988 First Annual Meeting, Boston, MA, Neural Networks Horowitz, M., Huyser et al, Karen, A. 1988; 1 (1): 101
  • CHARGE-SHARING MODELS FOR SWITCH-LEVEL SIMULATION IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS Chu, C. Y., Horowitz, M. A. 1987; 6 (6): 1053-1061
  • MIPS-X - A 20-MIPS PEAK, 32-BIT MICROPROCESSOR WITH ON-CHIP CACHE IEEE JOURNAL OF SOLID-STATE CIRCUITS Horowitz, M., Chow, P., Stark, D., SIMONI, R. T., SALZ, A., PRZYBYLSKI, S., Hennessy, J., Gulak, G., Agarwal, A., Acken, J. M. 1987; 22 (5): 790-799
  • A SINGLE-CHIP LSI HIGH-SPEED FUNCTIONAL TESTER IEEE JOURNAL OF SOLID-STATE CIRCUITS MIYAMOTO, J. I., Horowitz, M. A. 1987; 22 (5): 820-828
  • An Overview of the MIPS-X-MP Project Stanford University, Technical Report Hennessy, J., Horowitz, M. 1986: CSL-TR-86-300
  • An Analytical Cache Model Stanford University, Technical Report Agarwal, A., Horowitz, M., Hennessy, J. 1986: CSL-TR-86-304
  • SRT Division Diagrams and Their Usage in Designing Custom Integrated Circuits for Division Stanford University, Technical Report Williams, T., Horowitz, M. 1986: CSL-TR-87-326
  • An Automated Pressure Regulator Review of Scientific Instruments Waxman, M., Davis, H., A., Horowitz, M., Everhart, B. 1984; 55 (9): 1467-1470
  • A Low Cost Laser Interferometer System for Machine Tool Applications Precision Engineering Dorsey, A., Hocken, R. 1983; 5 (1): 29-31
  • Resistance Extraction from Mask Layout Data IEEE Transactions on Computer-Aided Design Horowitz, M., Dutton, R. 1983; CAD-2 (3): 145-150
  • Timing Models for MOS Circuits Stanford University, Ph.D. Thesis, Dec. 1983. Also appears as Stanford University, Technical Report Horowitz, M. 1983: SEL-83-003
  • Signal Delay in RC Tree Networks IEEE Transactions on Computer-Aided Design Rubinstein, J., Penfield, P., Horowitz, M. 1983; CAD-2 (3): 202-211
  • A 14B PCM DAC ISSCC DIGEST OF TECHNICAL PAPERS Mack, B., Horowitz, M., BLAUSCHILD, R. 1982; 25: 86-?
  • A 14 BIT DUAL-RAMP DAC FOR DIGITAL-AUDIO SYSTEMS IEEE JOURNAL OF SOLID-STATE CIRCUITS Mack, W. D., Horowitz, M., BLAUSCHILD, R. A. 1982; 17 (6): 1118-1126
  • MEASUREMENT OF SERIES COLLECTOR RESISTANCE IN BIPOLAR-TRANSISTORS IEEE JOURNAL OF SOLID-STATE CIRCUITS Mack, W. D., Horowitz, M. 1982; 17 (4): 767-773
  • A 14 Bit Dual Ramp DAC for Digital Audio IEEE Journal of Solid-State Circuits, Shorter version in Proceedings of International Solid-State Circuits Conference (ISSCC), San Francisco, CA Mack, W., Horowitz, M., Blauschild, R. 1982; SC-17 (6): 86-87
  • Critical Anomaly in the Dielectric Constant of a Non-polar Pure Fluid Phy Rev Letters Hocken, R., Horowitz, M., Greer, S. 1976; 37 (15): 964-967

Books and Book Chapters


  • Chapter Thirteen-Alignment of Cryo-Electron Tomography Datasets Methods in enzymology Amat, F., Castaño-Diez, D., Lawrence, A., Moussavi, F., Winkler, H., Horowitz, M. Elsevier. 2010: 343-367
  • Power Aware Design Methodologies. Pedram, M. 2002
  • Architectural and Implementation Tradeoffs in the Design of Multiple-Context Processors Multithreaded Computer Architectures Laudon, J., Gupta, A., Horowitz, M. Kluwer Academic Publishers. 1994: 1
  • The MIPS-X RISC Microprocessor Acken, J., Agarwal, A., Gulak, G., Horowitz, M., McFarling, S., Richardson, S. Kluwer Academic Publishers. 1989
  • The Design and Testing of MIPS-X Advanced Research in VLSI, Cambridge, MA Chow, P., Horowitz, M. MIT Press. 1988: 95-114
  • A Self Timing SRT Division Chip Advanced Research in VLSI, Stanford, CA Williams, T., E., Horowitz, M., Alverson, R., L., Yang, T., S. MIT Press. 1987: 75-95
  • The MIPS-X Microprocessor WESCON 1985, San Francisco, CA Horowitz, M., Chow, P. Published by Electronic Conventions Management, USA, Distributed by Western Periodicals Co, North Hollywood, CA. 1985: 6. 1

Conference Proceedings


  • Measurement of Supply Pin Current Distributions in Integrated Circuit Packages Weaver, James, A., Horowitz, Mark, A.
  • Analyzing CMOS Power Supply Networks Using Ariel, ACM/IEEE Stark, D., Horowitz, M.
  • Fortifying analog models with equivalence checking and coverage analysis Horowitz, M., Jeeradit, M., Lau, F., Liao, S., Lim, B., Mao, J. 2010

    View details for DOI 10.1145/1837274.1837381

  • An integrated framework for joint design space exploration of microarchitecture and circuits Azizi, O., Mahesri, A., Stevenson, J., P., Patel, S., J., Horowitz, M. 2010
  • An efficient test vector generation for checking analog/mixed-signal functional models Lim, B., C., Kim, J., Horowitz, M., A. 2010

    View details for DOI 10.1145/1837274.1837468

  • Intent-leveraged optimization of analog circuits via homotopy Jeeradit, M., Kim, J., Horowitz, M. 2010
  • Using a configurable processor generator for computer architecture prototyping Solomatnikov, A., Firoozshahian, A., Shacham, O., Asgar, Z., Wachs, M., Qadeer, W., Horowitz, M. A. 2009

    View details for DOI 10.1145/1669112.1669159

  • Integrated regulation for energy-efficient digital circuits Alon, E., Horowitz, M. IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. 2008: 1795-1807
  • A 90 nm CMOS 16 Gb/s transceiver for optical interconnects Palermo, S., Emami-Neyestanak, A., Horowitz, M. IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. 2008: 1235-1246
  • Digital circuit design trends Horowitz, M., Stark, D., Alon, E. IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. 2008: 757-761
  • A 24 Gb/s software programmable analog multi-tone transmitter Amirkhany, A., Abbasfar, A., Savoj, J., Jeeradit, M., Garlepp, B., Kollipara, R. T., Stojanovic, V., Horowitz, M. IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. 2008: 999-1009
  • Markov random field based automatic image alignment for electron tomography Amat, F., Moussavi, F., Comolli, L. R., Elidan, G., Downing, K. H., Horowitz, M. ACADEMIC PRESS INC ELSEVIER SCIENCE. 2008: 260-275

    Abstract

    We present a method for automatic full-precision alignment of the images in a tomographic tilt series. Full-precision automatic alignment of cryo electron microscopy images has remained a difficult challenge to date, due to the limited electron dose and low image contrast. These facts lead to poor signal to noise ratio (SNR) in the images, which causes automatic feature trackers to generate errors, even with high contrast gold particles as fiducial features. To enable fully automatic alignment for full-precision reconstructions, we frame the problem probabilistically as finding the most likely particle tracks given a set of noisy images, using contextual information to make the solution more robust to the noise in each image. To solve this maximum likelihood problem, we use Markov Random Fields (MRF) to establish the correspondence of features in alignment and robust optimization for projection model estimation. The resulting algorithm, called Robust Alignment and Projection Estimation for Tomographic Reconstruction, or RAPTOR, has not needed any manual intervention for the difficult datasets we have tried, and has provided sub-pixel alignment that is as good as the manual approach by an expert user. We are able to automatically map complete and partial marker trajectories and thus obtain highly accurate image alignment. Our method has been applied to challenging cryo electron tomographic datasets with low SNR from intact bacterial cells, as well as several plastic section and X-ray datasets.

    View details for DOI 10.1016/j.jsb.2007.07.007

    View details for Web of Science ID 000254349100006

    View details for PubMedID 17855124

  • The case for simple, visible cache coherency Kunz, R., Horowitz, M. 2008

    View details for DOI 10.1145/1353522.1353532

  • A 14-mW 6.25-Gb/s transceiver in 90-nm CMOS Poulton, J., Palmer, R., Fuller, A. M., Greer, T., Eyles, J., Dally, W. J., Horowitz, M. IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. 2007: 2745-2757
  • Veiling glare in high dynamic range imaging Talvala, E., Adams, A., Horowitz, M., Levoy, M. ASSOC COMPUTING MACHINERY. 2007
  • Variable domain transformation for linear PAC analysis of mixed-signal systems Kim, J., Jones, K., D., Horowitz, M., A. 2007
  • Fast, Non-Monte-Carlo Estimation of Transient Performance Variation Due to Device Mismatch Kim, J., Jones, K., D., Horowitz, M., A. 2007
  • 1550nm Optical Interconnect Transceiver with Low Voltage Electroabsorption Modulators Flip-Chip Bonded to 90nm CMOS Roth, J., E., Palermo, S., Helman, N., C., Bour, D., P., Miller, D., A. B., Horowitz, M. 2007
  • Integrated Regulation for Energy-Efficient Digital Circuits Alon, E., Horowitz, M. 2007
  • A 24Gbps Software Programmable Multi-Channel Transmitter Amirkhany, A., Abbasfar, A., Savoj, J., Jeeradit, M., Garlepp, B., Stojanovic, V., Horowitz, M. A. 2007
  • A 12GS/S Phase-Calibrated CMOS Digital-to-Analog Coverter Savoj, J., Abbasfar, A., Amirkhany, A., Garlepp, B., Jeeradit, M. 2007
  • A 14mW 6.25Gb/s Transceiver in 90nm CMOS for Serial Chip-to-Chip Communications Palmer, R., Poulton, J., Dally, W., J., Eyles, J., Fuller, A., M., Greer, T., Horowitz, M. A. 2007
  • The implementation of a 2-core, multi-threaded Itanium family processor Naffziger, S., Stackhouse, B., Grutkowski, T., Josephson, D., Desai, J., Alon, E., Horowitz, M. IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. 2006: 197-209
  • Dual photography Sen, P., Chen, B., Garg, G., Marschner, S. R., Horowitz, M., Levoy, M., Lensch, H. P. ASSOC COMPUTING MACHINERY. 2005: 745-755
  • High performance imaging using large camera arrays Wilburn, B., Joshi, N., Vaish, V., Talvala, E. V., Antunez, E., Barth, A., Adams, A., Horowitz, M., Levoy, M. ASSOC COMPUTING MACHINERY. 2005: 765-776
  • A 20-Gb/s 0.13-mu m CMOS serial link transmitter using an LC-PLL to directly drive the output multiplexer Chiang, P., Dally, W. J., Lee, M. J., Senthinathan, R., Oh, Y., Horowitz, M. A. IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. 2005: 1004-1011
  • Autonomous dual-mode (PAM2/4) serial link transceiver with adaptive equalization and data recovery Stojanovic, V., Ho, A., Garlepp, B. W., Chen, F., Wei, J., Tsang, G., Alon, E., Kollipara, R. T., Werner, C. W., Zerbe, J. L., Horowitz, M. A. IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. 2005: 1012-1026
  • Circuits and techniques for high-resolution measurement of on-chip power supply noise Alon, E., Stojanovic, V., Horowitz, M. A. IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. 2005: 820-828
  • Architecture and circuit techniques for a 1.1-GHz 16-kb reconfigurable memory in 0.18-mu m CMOS Mai, K., Ho, R., Alon, E., Liu, D., Kim, Y., Patil, D., Horowitz, M. A. IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. 2005: 261-275
  • Clocking and circuit design for a parallel I/O on a first-generation CELL processor Chang, K., Pamarti, S., Kaviani, K., Alon, E., Xudong, S., Chin, T., J., Horowitz, M. A. 2005
  • A new method for design of robust digital circuits. Patil, D., Yun, S., Kim, S., J, Cheung, A., Horowitz, M., Boyd, S. 2005
  • Opportunities for optics in integrated circuits applications. Solid-State Circuits Conference Miller, D., A. B., Bhatnagar, A., Palermo, S., Emami-Neyestanak, A., Horowitz, M., A. 2005
  • Synthetic aperture confocal imaging Levoy, M., Chen, B., Vaish, V., Horowitz, M., McDowall, I., Bolas, M. ASSOC COMPUTING MACHINERY. 2004: 825-834
  • Circuits and techniques for high-resolution measurement of on-chip power supply noise Alon, E., Stojanovic, V., Horowitz, M. 2004
  • Adaptive equalization and data recovery in a dual-mode (PAM2/4) serial link transceiver Stojanovic, V., Ho, A., Garlepp, B., Chen, F., Wei, J., Alon, E., Horowitz, M. A. 2004
  • 20Gb/s 0.13 mu m CMOS serial link transmitter using an LC-PLL to directly drive the output multiplexer Chiang, P., Dally, W., J., Lee, M., J. E., Senthinathan, R., Yangjin, O., Horowitz, M. 2004
  • Burst mode packet receiver using a second order DLL Lee, H., C., Yue, C., H., Palermo, S., Mai, K., W., Horowitz, M. 2004
  • Common-mode backchannel signaling system for differential high-speed links Ho, A., Stojanovic, V., Chen, F., Werner, C., Tsang, G., Alon, E., Horowitz, M. A. 2004
  • Equalization and clock recovery for a 2.5-10-Gb/s 2-PAM/4-PAM backplane transceiver cell Zerbe, J. L., Werner, C. W., Stojanovic, V., Chen, F., Wei, J., Tsang, G., Kim, D., Stonecypher, W. F., Ho, A., Thrush, T. P., Kollipara, R. T., Horowitz, M. A., Donnelly, K. S. IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. 2003: 2121-2130
  • A 10-GHz global clock distribution using coupled standing-wave oscillators O'Mahony, F., Yue, C. P., Horowitz, M. A., Wong, S. S. IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. 2003: 1813-1820
  • Scaling Internet routers using optics Keslassy, I., Chuang, S. T., Yu, K., Miller, D., Horowitz, M., Solgaard, O., McKeown, N. ASSOC COMPUTING MACHINERY. 2003: 189-200
  • A framework for designing reusable analog circuits Liu, D., Sidiropoulos, S., Horowitz, M. 2003
  • Modeling and analysis of high-speed links Stojanovic, V., Horowitz, M. 2003
  • Adaptive supply serial links with sub-I-V operation and per-pin clock recovery Kim, J., Horowitz, M. A. IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. 2002: 1403-1413
  • An efficient digital sliding controller for adaptive power-supply regulation Kim, J., Horowitz, M. A. IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. 2002: 639-647
  • 1.6 Gb/s, 3 mW CMOS receiver for optical communication Emami-Neyestanak, A., Liu, D., Keeler, G., Helman, N., Horowitz, M., A. 2002
  • Transmit pre-emphasis for high-speed time-division-multiplexed serial-link transceiver Stojanovic, V., Ginis, G., Horowitz, M., A. 2002
  • Methods for true power minimization Brodersen, R., W., Horowitz, M., A., Markovic, D., Nikolic, B., Stojanovic, V. 2002
  • Energy-delay tradeoffs in combinational logic using gate sizing and supply voltage optimization. ESSCIRC 2002 Stojanovic, V., Markovic, D., Nikolic, B., Horowitz, M., A., Brodersen, R., W. 2002
  • Light field video camera Wilburn, B., S., Smulski, M., Lee, H., K., Horowitz, M., A. 2001
  • Using texture mapping with mipmapping to render a VLSI layout Solomon, J., Horowitz, M. 2001
  • Sampling-rate optimization of an interleaved-sampling front-end. ISCAS 2001 H., M., O., Johansson 2001
  • Optimizing iterative decoding of low-density parity check codes on programmable pipelined parallel architectures Al-Rawi, G., Cioffi, J., Motwani, R., Horowitz, M. 2001
  • A serial-link transceiver based on 8 GSample/s A/D and D/A converters in 0.25 mu m CMOS Ellersick, W., Yang, C., K. K., Stojanovic, V., Modjtahedi, S., Horowitz, M., A. 2001
  • Optimizing the mapping of low-density parity check codes on parallel decoding architectures Al-Rawi, G., Cioffi, J., Horowitz, M. 2001
  • Architectural support for copy and tamper resistant software Lie, D., Thekkath, C., Mitchell, M., Lincoln, P., Boneh, D., Mitchell, J., Horowitz, M. ASSOC COMPUTING MACHINERY. 2000: 168-177
  • FLASH vs. (Simulated) FLASH: Closing the simulation loop Gibson, J., Kunz, R., Ofelt, D., Horowitz, M., Hennessy, J., Heinrich, M. ASSOC COMPUTING MACHINERY. 2000: 49-58
  • A 2.4 gb/s/pin simultaneous bidirectional parallel link with per-pin skew compensation Yeung, E., Horowitz, M. A. IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. 2000: 1619-1628
  • A variable-frequency parallel I/O interface with adaptive power-supply regulation Wei, G. Y., Kim, J., Liu, D., Sidiropoulos, S., Horowitz, M. A. IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. 2000: 1600-1610
  • A 0.3-mu m CMOS 8-Gb/s 4-PAM serial link transceiver Farjad-Rad, R., Yang, C. K., Horowitz, M. A., Lee, T. H. IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. 2000: 757-764
  • Adaptive bandwidth DLLs and PLLs using regulated supply CMOS buffers Sidiropoulos, S., Liu, D., Kim, J., Wei, G., Horowitz, M. 2000
  • Smart Memories: a modular reconfigurable architecture Mai, K., Paaske, T., Jayasena, N., Ho, R., Dally, W., J., Horowitz, M. 2000
  • An eight channel 35 GSample/s CMOS timing analyzer Weinlader, D., Ron, H., Yang, C. K., Horowitz, M. 2000
  • A 2.4 Gb/s/pin simultaneous bidirectional parallel link with per pin skew compensation Yeung, E., Horowitz, M. 2000
  • A 0.4-mu m CMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter Farjad-Rad, R., Yang, C. K., Horowitz, M. A., Lee, T. H. IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. 1999: 580-585
  • A portable digital DLL for high-speed CMOS interface circuits Garlepp, B. W., Donnelly, K. S., Kim, J., Chau, P. S., Zerbe, J. L., Huang, C., Tran, C. V., Portmann, C. L., Stark, D., Chan, Y. F., Lee, T. H., Horowitz, M. A. IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. 1999: 632-644
  • Using Partitioning to Help Convergence in the Standard-Cell Design Automation Methodology Kapadia, H., Horowitz, M. 1999
  • A 50 Gb/s 32*32 CMOS crossbar chip using asymmetric serial links Chang, K. K., Chuang, S., McKeown, N., Horowitz, M. 1999
  • A 0.3- mu m CMOS 8-Gb/s 4-PAM serial link transceiver Farjad-Rad, R., Yang, C. K., Horowitz, M., Lee, T. 1999
  • Using partitioning to help convergence in the standard-cell design automation methodology Kapadia, H., Horowitz, M. 1999
  • Scaling implications for CAD Ho, R., Mai, K., Horowitz, M. 1999
  • Improving Coverage Analysis and Test Generation for Large Designs Bergmann, J., Horowitz, M. 1999
  • GAD: A 12-GS/s CMOS 4-bit A/D converter for an equalized multi-level link Ellersick, W., Yang, C. K., Horowitz, M., Dally, W. 1999
  • Vex - A CAD Toolbox Bergmann, J., P., Horowitz, M., A. 1999
  • A 0.5-mu m CMOS 4.0-Gbit/s serial link transceiver with data recovery using oversampling Yang, C. K., Farjad-Rad, R., Horowitz, M. A. IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. 1998: 713-722
  • A 0.4-µm CMOS 10-Gb/s 4-PAM Pre-Emphasis Serial Link Transmitter Farjad-Rad, R., Yang, C-K, K., Horowitz, M. 1998
  • A 2Gb/s Asymmetric Serial Link for High-bandwidth Packet Switches Chang, K., K.-Y, Ellersick, W., Chuang, T., S., Sidiropoulos, S., Horowitz, M., McKeown, N. 1998
  • Applications of On-Chip Samplers for Test and Measurement of Integrated Circuits Ho, R., Amrutur, B., Mai, K., Wilburn, B., Mori 1998
  • Optimization of hybrid JJ/CMOS memory operating temperatures Gupta, D., Amrutur, B., Terzioglu, E., Ghoshal, U., Beasley, M. R., Horowitz, M. IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. 1997: 3307-3310
  • Skew-tolerant domino circuits Harris, D., Horowitz, M. A. I E E E. 1997: 422-423
  • A semi-digital DLL with unlimited phase shift capability and 0.08-400MHz operating range Sidiropoulos, S., Horowitz, M. I E E E. 1997: 332-333
  • Tiny Tera: A packet switch core McKeown, N., IZZARD, M., Mekkittikul, A., Ellersick, W., Horowitz, M. IEEE COMPUTER SOC. 1997: 26-33
  • Hardware fault containment in scalable shared-memory multiprocessors Teodosiu, D., Baxter, J., Govil, K., Chapin, J., Rosenblum, M., Horowitz, M. ASSOC COMPUTING MACHINERY. 1997: 73-84
  • A 0.6u CMOS 4.0Gbps Transceiver with Data Recovery using Oversampling Yang, C., K, Farjad-Rad, R., Horowitz, M. 1997
  • An Equalization Scheme for 10Gb/s 4-PAM Signaling over Long Cables Farjad-Rad, K., Yu, Yang, C., K., Ellersick, W., Horowitz, M., Lee, T., H. 1997
  • SRT Division Architectures and Implementations Harris, D., L., Oberman, S., F., Horowitz, M., A. 1997
  • A 0.8-mu m CMOS 2.5 Gb/s oversampling receiver and transmitter for serial links Yang, C. K., Horowitz, M. A. IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. 1996: 2015-2023
  • A 50% Noise Reduction Interface Using Low-Weight Coding Nakamura, K., Horowitz, M., A. 1996
  • Informing memory operations: Providing memory performance feedback in modem processors Horowitz, M., Martonosi, M., Mowry, T. C., Smith, M. D. ASSOC COMPUTING MACHINERY. 1996: 260-270
  • A 700 Mbps/pin CMOS signalling interface using current integrating receivers Sidiropoulos, S., Horowitz, M. I E E E. 1996: 142-143
  • A low power switching power supply for self-clocked systems Wei, G. Y., Horowitz, M. I E E E. 1996: 313-317
  • A 0.8 mu m CMOS 2.5Gb/s oversampled receiver for serial links Yang, C. K., Horowitz, M. A. I E E E. 1996: 200-201
  • Validation Coverage Analysis for Complex Digital Designs Ho, R., C., Horowitz, M., A. 1996
  • Informing Memory Operations: Providing Memory Performance Feedback in Modern Processors Horowitz, M., Martonosi, M., Mowry, T., C., Smith, M., D. 1996
  • Architecture validation for processors Ho, R. C., Yang, C. H., Horowitz, M. A., Dill, D. L. ASSOC COMPUTING MACHINERY. 1995: 404-413
  • Current integrating receivers for high speed system interconnects Sidiropoulos, S., Horowitz, M. I E E E. 1995: 107-110
  • REGENERATIVE FEEDBACK REPEATERS FOR PROGRAMMABLE INTERCONNECTIONS Dobbelaere, I., Horowitz, M., Elgamal, A. I E E E. 1995: 116-117
  • Clustered Voltage Scaling Technique for Low-Power Design Usami, K., Horowitz, M. 1995
  • THE PERFORMANCE IMPACT OF FLEXIBILITY IN THE STANFORD FLASH MULTIPROCESSOR Heinrich, M., KUSKIN, J., Ofelt, D., Heinlein, J., Baxter, J., Singh, J. P., Simoni, R., Gharachorloo, K., NAKAHIRA, D., Horowitz, M., Gupta, A., Rosenblum, M., Hennessy, J. ASSOC COMPUTING MACHINERY. 1994: 274-285
  • INTERLEAVING - A MULTITHREADING TECHNIQUE TARGETING MULTIPROCESSORS AND WORKSTATIONS LAUDON, J., Gupta, A., Horowitz, M. ASSOC COMPUTING MACHINERY. 1994: 308-318
  • THE STANFORD FLASH MULTIPROCESSOR KUSKIN, J., Ofelt, D., Heinrich, M., Heinlein, J., Simoni, R., Gharachorloo, K., Chapin, J., NAKAHIRA, D., Baxter, J., Horowitz, M., Gupta, A., Rosenblum, M., Hennessy, J. I E E E, COMPUTER SOC PRESS. 1994: 302-313
  • WHO WILL WIN THE WINDOWS NT SILICON SWEEPSTAKES Horowitz, M., Slager, J., Heller, A., Tredennick, N., Riordan, T., Dobberpuhl, D., DHAM, V., MOTHERSOLE, D. I E E E. 1994: 234-235
  • A CMOS 500-MBPS PIN SYNCHRONOUS POINT-TO-POINT LINK INTERFACE Sidiropoulos, S., Yang, C. K., Horowitz, M. I E E E. 1994: 43-44
  • Techniques to Reduce Power in Fast Wide Memories (CMOS SRAMS) Amrutur, B., S., Horowitz, M. 1994
  • Using Partitioning to Help Convergence in the Standard-cell Design Automation Methodology Kapadia, H., Horowitz, M. 1994
  • Techniques for Characterizing DRAMS with a 500 MHZ Interface Gasbarro, J., A., Horowitz, M., A. 1994
  • Low-Power Digital Design Horowitz et al, M. 1994
  • Evaluation of Charge Recovery Circuits and Adiabatic Switching for Low Power CMOS Design Indermaur, T., Horowitz, M. 1994
  • Performance Analysis of a Kinetic Inductance Memory Array Chen, G., J., Beasley, M., R., Horowitz, M. 1993
  • NONDESTRUCTIVE READOUT ARCHITECTURE FOR A KINETIC INDUCTANCE MEMORY CELL Chen, G. J., Beasley, M. R., Horowitz, M., Rosenthal, P., Whiteley, S. I E E E. 1993: 2702-2705
  • Piecewise Linear Models for Rsim Kao, R., Horowitz, M. 1993
  • PLL Design for a 500 MB/s Interface Horowitz et al, M. 1993
  • A 500-Megabyte/s Data-Rate 4.5M DRAM Kushiyama et al, N. 1992
  • Nondestructive Readout Architecture for a Kinetic Inductance Memory Cell Chen, G., J., Beasley, M., R., Rosenthal, P., R., Horowitz, M., Whiteley, S. 1992, 1993
  • Clocking Strategies in High Performance Processors Horowitz et al., M. 1992
  • Architectural and Implementation Tradeoffs in the Design of Multiple-Context Processors Laudon et al., J. 1992
  • 500 Mbyte/sec Data-Rate 512 Kbits*9 DRAM Using a Novel I/O Interface Kushiyama et al., N. 1992
  • Dynamic Pointer Allocation for Scalable Cache Coherence Directories Simoni, R., Horowitz, M. 1991
  • A 160nS 54bit CMOS Division Implementation Using Self-Timing and Symmetrically Overlapped SRT Stages Williams, T., E., Horowitz, M., A. 1991
  • Modeling the Performance of Limited Pointers Directories for Cache Coherence Simoni, R., Horowitz, M. 1991
  • A Single-Chip, Functional Tester for VLSI Circuits Gasbarro, J., Horowitz, M., A., Testarossa, M. 1990
  • Design of Scalable Shared-Memory Multiprocessors: the DASH Approach, Held: San Francisco, CA Lenoski et al., D. 1990
  • Boosting Beyond Static Scheduling in a Superscalar Processor Horowitz, M., D. 1990
  • BiCMOS Circuit Design Horowitz et al., M. 1990
  • A 3.5ns, 1 Watt, ECL Register File Horowitz, M., Slamowitz, M., Rose, B., Johnson, M. 1990
  • Limits on Multiple Instruction Issue Smith, M., Johnson, M., Horowitz, M. 1989, 1990
  • IRSIM: An Incremental MOS Switch-Level Simulator, IEEE/ACM Salz, A., Horowitz, M. 1989
  • Rounding Algorithms for IEEE Multipliers Santoro, M., Bewick, G., Horowitz, M. 1989
  • Characteristics of Performance-Optimal Multi-Level Cache Hierarchies Przybylski, S., Horowitz, M., Hennessy, J. 1989
  • SPIM: A Pipelined 64 x 64 Bit Iterative Multiplier Santoro, M., Horowitz, M. 1989, 1988
  • A Single-Ended BiCMOS Sense Circuit for Digital Circuit Rosseel, G., Horowitz, M., Cline, R., Dutton, R. 1989
  • Integrated Pin Electronics for VLSI Functional Testers Gasbarro, J., Horowitz, M. 1989
  • Bisim: A Simulator for Custom ECL Circuits Kao, R., Alverson, R., Horowitz, M., Stark, D. 1988
  • Performance Tradeoffs in Cache Design, IEEE Przybylski, S., Horowitz, M., Hennessy, J. 1988
  • Scalable Directory Schemes for Cache Consistency Agarwal, A., Simoni, R., Hennessy, J., Horowitz, M. 1988
  • A 4nsec 4Kx1bit Two-Port BiCMOS SRAM Yang, T. S., Horowitz, M., Wooley, B. 1988
  • Architectural Tradeoffs in the Design of MIPS-X Chow, P., Horowitz, M. 1987
  • Toriodal Compaction of Symbolic Layouts for Regular Structures Eichenberger, P., Horowitz, M. 1987
  • On-Chip Instruction Caches for High Performance Processors Horowitz, M., Agarwal et al, A. 1987
  • A Static RAM as a Fault Model Evaluator Acken, J., Horowitz, M. 1987
  • REDS: Resistance Extraction for Digital Stimulation, ACM/IEEE Stark, D., Horowitz, M. 1987
  • Generating Incremental VLSI Compaction Spacing Constraints, ACM/IEEE Carpenter, C., Horowitz, M. 1987
  • Active Substrate System Integration Wooley, B., Horowitz, M., Pease, R., Yang, T. 1987
  • ATUM: A New Technique for Capturing Address Traces Using Microcode Agarwal, A., Sites, R., Horowitz, M. 1986
  • Timing Models for MOS Pass Nets Horowitz, M. 1983