Bio

Navid Anjum Aadit is a postdoctoral scholar in Electrical Engineering at Stanford University, working with Prof. Subhasish Mitra on monolithic 3D CMOS+X integration and multi-chiplet systems for energy-efficient AI hardware, spanning architecture and chiplet design through tape-out, emulation-based verification, and post-silicon measurement.

He completed his PhD in Electrical and Computer Engineering at UC Santa Barbara in 2025 with Prof. Kerem Y. Camsari, where his work established probabilistic computing with p-bits as a practical hardware platform. He led the design of the first programmable probabilistic computer at the one-million p-bit scale, a distributed machine built from networked FPGAs, which was featured by IEEE Spectrum. His work spans combinatorial optimization, energy-based machine learning, and quantum simulation, and includes first-author papers in Nature Electronics and Nature Communications.

He is a recipient of the 2025 Misha Mahowald Prize for neuromorphic engineering, a 2023 Bell Labs Prize (Bronze), and the 2025 UCSB ECE Outstanding Dissertation Award.

Honors & Awards

  • Bell Labs Prize, Bronze, Nokia Bell Labs (2023)
  • Misha Mahowald Prize for Neuromorphic Engineering (OPUS team, UC Santa Barbara), Misha Mahowald Prize Committee (2025)
  • UCSB ECE Outstanding Dissertation Award, Department of Electrical and Computer Engineering, University of California, Santa Barbara (2025)
  • PhD Dissertation Fellowship, Graduate Division, University of California, Santa Barbara (2025)
  • DTEI Fellowship, Division of Teaching Excellence and Innovation, University of California, Irvine (2020)
  • NSF MRSEC Research Fellowship, University of California, Irvine (2020)

Boards, Advisory Committees, Professional Organizations

  • Scientific Committee Member, International Workshop on Ising Machines (IISM) (2026 - 2026)
  • Reviewer, Nature Scientific Reports; Communications Physics; PLOS ONE; Digital Discovery (2021 - Present)
  • Reviewer, IEEE journals: Journal on Exploratory Solid-State Computational Devices and Circuits (JXCDC); Transactions on Nanotechnology; Transactions on Computer-Aided Design of Integrated Circuits and Systems; Transactions on Affective Computing; Access (2021 - Present)

Professional Education

  • PhD, University of California, Santa Barbara, Electrical and Computer Engineering (2025)
  • MS, University of California, Irvine, Electrical and Computer Engineering (2020)
  • B.Sc., Bangladesh University of Engineering and Technology, Electrical and Electronic Engineering (2016)

Stanford Advisors

Contact

Additional Info

Links

Research Interests

  • Artificial intelligence (AI)

Current Research and Scholarly Interests

Navid Anjum Aadit builds computing hardware for problems that resist conventional acceleration: high-dimensional sampling, combinatorial search, and large AI models under hard energy budgets. His research spans the full stack these problems demand, from the Monte Carlo algorithms that solve them, through the architectures that execute them efficiently, down to the device physics that makes those architectures possible. Two commitments organize the work: that a computation should exploit the physics of its substrate rather than abstract away from it, and that memory and compute belong co-located rather than separated by a package boundary.

Monolithic 3D integration. At Stanford, working with Prof. Subhasish Mitra, Aadit works on monolithic 3D CMOS+X: silicon CMOS, carbon nanotube transistors, and resistive memory fabricated as one vertically integrated stack. Placing dense non-volatile memory immediately above compute reduces the off-chip traffic that dominates inference energy and changes how much of a model a single die can hold. He contributes across accelerator architecture and chiplet design, tape-out, emulation-based verification, bring-up, debug, and post-silicon characterization, including multi-chiplet systems engineered so that many physical dies behave as one logical device.

Probabilistic computing. A probabilistic bit, or p-bit, fluctuates between 0 and 1 with a tunable probability, and networks of p-bits sample from distributions rather than evaluating functions. Algorithmically, his work maps adaptive parallel tempering, discrete-time simulated quantum annealing, and non-equilibrium Monte Carlo onto massively parallel hardware, and develops the sparsification and higher-order embedding techniques that allow sparse hardware to represent densely connected problems without sacrificing solution quality. Architecturally, he has designed sparse Ising machines on CMOS and FPGAs, heterogeneous systems pairing CMOS with stochastic magnetic tunnel junctions, and the first programmable probabilistic computer at the million p-bit scale, distributed across networked chips. The applications extend well past optimization, to energy-based machine learning and the training of deep Boltzmann networks, to Bayesian inference, and to sampling the quantum states of many-body systems. This work has appeared in Nature Electronics, Nature Communications, Physical Review Applied, IEDM and the VLSI Symposium, and has been featured by IEEE Spectrum. It was recognized with the 2025 Misha Mahowald Prize for neuromorphic engineering and the 2025 UCSB ECE Outstanding Dissertation Award.

Convergence. Probabilistic machines have so far been built largely from FPGAs, which caps their density and energy efficiency. Dense stochastic memory, which monolithic 3D integration makes manufacturable, is a more compelling substrate, and the two research directions therefore converge. Aadit's program follows from that convergence: co-designing Monte Carlo algorithms, probabilistic architectures, and three-dimensionally integrated stochastic devices into accelerators for sampling and inference that no single layer of the stack reaches alone. The longer aim is hardware in which probability is the computational primitive and vertical integration supplies the density to make it competitive with conventional machines on energy and cost, and with quantum annealers on time to solution for the problems both target.

Lab Affiliations

All Publications

  • Pushing the boundary of quantum advantage in hard combinatorial optimization with probabilistic computers NATURE COMMUNICATIONS Chowdhury, S., Aadit, N., Grimaldi, A., Raimondo, E., Raut, A., Lott, P., Mentink, J. H., Rams, M. M., Ricci-Tersenghi, F., Chiappini, M., Theogarajan, L. S., Srimani, T., Finocchio, G., Mohseni, M., Camsari, K. Y. 2025; 16 (1): 9193

    Abstract

    Recent demonstrations on specialized benchmarks have reignited excitement for quantum computers, yet their advantage for real-world problems remains an open question. Here, we show that probabilistic computers, co-designed with hardware to implement Monte Carlo algorithms, provide a scalable classical pathway for solving hard optimization problems. We focus on two algorithms applied to three-dimensional spin glasses: discrete-time simulated quantum annealing and adaptive parallel tempering. We benchmark these methods against a leading quantum annealer. For simulated quantum annealing, increasing replicas improves residual energy scaling, consistent with extreme value theory. Adaptive parallel tempering, supported by non-local isoenergetic cluster moves, scales more favorably and outperforms simulated quantum annealing. Field Programmable Gate Arrays or specialized chips can implement these algorithms in modern hardware, leveraging massive parallelism to accelerate them while improving energy efficiency. Our results establish a rigorous classical baseline for assessing practical quantum advantage and present probabilistic computers as a scalable platform for real-world optimization challenges.

    View details for DOI 10.1038/s41467-025-64235-y

    View details for Web of Science ID 001596640300012

    View details for PubMedID 41102159

    View details for PubMedCentralID PMC12533262

  • Scalable connectivity for Ising machines: Dense to sparse PHYSICAL REVIEW APPLIED Sajeeb, M., Aadit, N., Chowdhury, S., Wu, T., Smith, C., Chinmay, D., Raut, A., Camsari, K. Y., Delacour, C., Srimani, T. 2025; 24 (1)

    View details for DOI 10.1103/kx8m-5h3h

    View details for Web of Science ID 001531350400006

  • All-to-all reconfigurability with sparse and higher-order Ising machines NATURE COMMUNICATIONS Nikhar, S., Kannan, S., Aadit, N., Chowdhury, S., Camsari, K. Y. 2024; 15 (1): 8977

    Abstract

    Domain-specific hardware to solve computationally hard optimization problems has generated tremendous excitement. Here, we evaluate probabilistic bit (p-bit) based Ising Machines (IM) on the 3-Regular 3-Exclusive OR Satisfiability (3R3X), as a representative hard optimization problem. We first introduce a multiplexed architecture that emulates all-to-all network functionality while maintaining highly parallelized chromatic Gibbs sampling. We implement this architecture in a single Field-Programmable Gate Array (FPGA) and show that running the adaptive parallel tempering algorithm demonstrates competitive algorithmic and prefactor advantages over alternative IMs by D-Wave, Toshiba, and Fujitsu. We also implement higher-order interactions that lead to better prefactors without changing algorithmic scaling for the XORSAT problem. Even though FPGA implementations of p-bits are still not quite as fast as the best possible greedy algorithms accelerated on Graphics Processing Units (GPU), scaled magnetic versions of p-bit IMs could lead to orders of magnitude improvements over the state of the art for generic optimization.

    View details for DOI 10.1038/s41467-024-53270-w

    View details for Web of Science ID 001338950000015

    View details for PubMedID 39419987

    View details for PubMedCentralID PMC11487278

  • Training deep Boltzmann networks with sparse Ising machines NATURE ELECTRONICS Niazi, S., Chowdhury, S., Aadit, N., Mohseni, M., Qin, Y., Camsari, K. Y. 2024; 7 (7)

    View details for DOI 10.1038/s41928-024-01182-4

    View details for Web of Science ID 001248585300002

  • CMOS plus stochastic nanomagnets enabling heterogeneous computers for probabilistic inference and learning NATURE COMMUNICATIONS Singh, N., Kobayashi, K., Cao, Q., Selcuk, K., Hu, T., Niazi, S., Aadit, N., Kanai, S., Ohno, H., Fukami, S., Camsari, K. Y. 2024; 15 (1): 2685

    Abstract

    Extending Moore's law by augmenting complementary-metal-oxide semiconductor (CMOS) transistors with emerging nanotechnologies (X) has become increasingly important. One important class of problems involve sampling-based Monte Carlo algorithms used in probabilistic machine learning, optimization, and quantum simulation. Here, we combine stochastic magnetic tunnel junction (sMTJ)-based probabilistic bits (p-bits) with Field Programmable Gate Arrays (FPGA) to create an energy-efficient CMOS + X (X = sMTJ) prototype. This setup shows how asynchronously driven CMOS circuits controlled by sMTJs can perform probabilistic inference and learning by leveraging the algorithmic update-order-invariance of Gibbs sampling. We show how the stochasticity of sMTJs can augment low-quality random number generators (RNG). Detailed transistor-level comparisons reveal that sMTJ-based p-bits can replace up to 10,000 CMOS transistors while dissipating two orders of magnitude less energy. Integrated versions of our approach can advance probabilistic computing involving deep Boltzmann machines and other energy-based learning algorithms with extremely high throughput and energy efficiency.

    View details for DOI 10.1038/s41467-024-46645-6

    View details for Web of Science ID 001195542300021

    View details for PubMedID 38538599

    View details for PubMedCentralID PMC10973401

  • A Full-Stack View of Probabilistic Computing With p-Bits: Devices, Architectures, and Algorithms IEEE JOURNAL ON EXPLORATORY SOLID-STATE COMPUTATIONAL DEVICES AND CIRCUITS Chowdhury, S., Grimaldi, A., Aadit, N., Niazi, S., Mohseni, M., Kanai, S., Ohno, H., Fukami, S., Theogarajan, L., Finocchio, G., Datta, S., Camsari, K. Y. 2023; 9 (1): 1-11

    View details for DOI 10.1109/JXCDC.2023.3256981

    View details for Web of Science ID 001000245200001

  • Efficient Probabilistic Computing with Stochastic Perovskite Nickelates NANO LETTERS Park, T., Selcuk, K., Zhang, H., Manna, S., Batra, R., Wang, Q., Yu, H., Aadit, N., Sankaranarayanan, S. S., Zhou, H., Camsari, K. Y., Ramanathan, S. 2022: 8654-8661

    Abstract

    Probabilistic computing has emerged as a viable approach to solve hard optimization problems. Devices with inherent stochasticity can greatly simplify their implementation in electronic hardware. Here, we demonstrate intrinsic stochastic resistance switching controlled via electric fields in perovskite nickelates doped with hydrogen. The ability of hydrogen ions to reside in various metastable configurations in the lattice leads to a distribution of transport gaps. With experimentally characterized p-bits, a shared-synapse p-bit architecture demonstrates highly parallelized and energy-efficient solutions to optimization problems such as integer factorization and Boolean satisfiability. The results introduce perovskite nickelates as scalable potential candidates for probabilistic computing and showcase the potential of light-element dopants in next-generation correlated semiconductors.

    View details for DOI 10.1021/acs.nanolett.2c03223

    View details for Web of Science ID 000880803400001

    View details for PubMedID 36315005

  • Massively parallel probabilistic computing with sparse Ising machines NATURE ELECTRONICS Aadit, N., Grimaldi, A., Carpentieri, M., Theogarajan, L., Martinis, J. M., Finocchio, G., Camsari, K. Y. 2022; 5 (7): 460-468

    View details for DOI 10.1038/s41928-022-00774-2

    View details for Web of Science ID 000805096900001

  • Spintronics-compatible Approach to Solving Maximum-Satisfiability Problems with Probabilistic Computing, Invertible Logic, and Parallel Tempering PHYSICAL REVIEW APPLIED Grimaldi, A., Sanchez-Tejerina, L., Aadit, N., Chiappini, S., Carpentieri, M., Camsari, K., Finocchio, G. 2022; 17 (2)

    View details for DOI 10.1103/PhysRevApplied.17.024052

    View details for Web of Science ID 000761410500004

  • Computing with Invertible Logic: Combinatorial Optimization with Probabilistic Bits Aadit, N., Grimaldi, A., Carpentieri, M., Theogarajan, L., Finocchio, G., Camsari, K. Y., IEEE IEEE. 2021

    View details for DOI 10.1109/IEDM19574.2021.9720514

    View details for Web of Science ID 000812325400020

https://orcid.org/0000-0001-9933-0728