Bio

Po-Han Chen is an EE Ph.D. student at Stanford University supervised by Prof. Priyanka Raina. He received his B.S. in Electrical Engineering and Computer Science (EECS) and M.S. in Electrical Engineering from National Tsing Hua University (Taiwan) in 2016 and 2018 respectively. Before joining Stanford, he was a digital circuit designer at MediaTek where he worked on developing hardware architectures of image processing pipeline. He is interested in designing hardware accelerators. Most of his previous works were related to computational photography algorithms such as digital refocusing. Currently, He is focusing on analyzing and designing architecture of CGRAs to create high-performance, energy-efficient, and reconfigurable computing platforms.

Contact

  • Academic
    pohan@stanford.edu
    University - Student Department: Electrical Engineering Position: Graduate
    University - Student Department: Electrical Engineering Position: Graduate

Additional Info

All Publications

  • Amber: A 16-nm System-on-Chip With a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra IEEE JOURNAL OF SOLID-STATE CIRCUITS Feng, K., Kong, T., Koul, K., Melchert, J., Carsello, A., Liu, Q., Nyengele, G., Strange, M., Zhang, K., Nayak, A., Setter, J., Thomas, J., Sreedhar, K., Chen, P., Bhagdikar, N., Myers, Z. A., D'Agostino, B., Joshi, P., Richardson, S., Torng, C., Horowitz, M., Raina, P. 2023

    View details for DOI 10.1109/JSSC.2023.3313116

    View details for Web of Science ID 001078350700001

  • AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers ACM Transactions on Embedded Computing Systems Koul, K., Melchert, J., Sreedhar, K., Truong, L., Nyengele, G., Zhang, K., Liu, Q., Setter, J., Chen, P., Mei, Y., Strange, M., Daly, R., Donovick, C., Carsello, A., Kong, T., Feng, K., Huff, D., Nayak, A., Setaluri, R., Thomas, J., Bhagdikar, N., Durst, D., Myers, Z., Tsiskaridze, N., Richardson, S., et al 2023; 22 (2)

    View details for DOI 10.1145/3534933

  • An Open-Source 4x8 Coarse-Grained Reconfigurable Array Using SkyWater 130 nm Technology and Agile Hardware Design Flow Chen, P., Tsao, C., Raina, P., IEEE IEEE. 2023

    View details for DOI 10.1109/ISCAS46773.2023.10182052

    View details for Web of Science ID 001038214602125

  • mflowgen: a modular flow generator and ecosystem for community-driven physical design DAC '22: Proceedings of the 59th ACM/IEEE Design Automation Conference Carsello, A., Thomas, J., Nayak, A., Chen, P., Horowitz, M., Raina, P., Torng, C. 2022: 1339–1342

    View details for DOI 10.1145/3489517.3530633

  • SAPIENS: A 64-kb RRAM-Based Non-Volatile Associative Memory for One-Shot Learning and Inference at the Edge IEEE TRANSACTIONS ON ELECTRON DEVICES Li, H., Chen, W., Levy, A., Wang, C., Wang, H., Chen, P., Wan, W., Khwa, W., Chuang, H., Chih, Y., Chang, M., Wong, H., Raina, P. 2021; 68 (12): 6637-6643

    View details for DOI 10.1109/TED.2021.3110464

    View details for Web of Science ID 000724501000107

https://orcid.org/0000-0001-9760-9565