Priyanka Raina

All Publications

• Onyx: A 12-nm Programmable Accelerator for Dense and Sparse Applications IEEE JOURNAL OF SOLID-STATE CIRCUITS Koul, K., Hsu, O., Mei, Y., Ravipati, S., Strange, M., Melchert, J., Carsello, A., Kong, T., Chen, P., Ke, H., Zhang, K., Liu, Q., Nyengele, G., Xie, Z., Balasingam, A., Adivarahan, J., Sharma, R., Torng, C., Emer, J. S., Kjolstad, F., Horowitz, M., Raina, P. 2025

  View details for DOI 10.1109/JSSC.2025.3604724

  View details for Web of Science ID 001566830000001

• Designing Programmable Accelerators for Sparse Tensor Algebra IEEE MICRO Koul, K., Xie, Z., Strange, M., Ravipati, S., Cheng, B., Hsu, O., Chen, P., Horowitz, M., Kjolstad, F., Raina, P. 2025; 45 (3): 58-65

  View details for DOI 10.1109/MM.2025.3556611

  View details for Web of Science ID 001523482200015

• Monolithic 3-D Integration of Diverse Memories: Resistive Switching (RRAM) and Gain Cell (GC) Memory Integrated on Si CMOS IEEE TRANSACTIONS ON ELECTRON DEVICES Liu, S., Radway, R. M., Wang, X., Moro, F., Nodin, J., Jana, K., Yan, L., Du, S., Upton, L. R., Chen, W., Kang, J., Chen, J., Li, H., Andrieu, F., Vianello, E., Raina, P., Mitra, S., Wong, H. 2025

  View details for DOI 10.1109/TED.2025.3556113

  View details for Web of Science ID 001480280000001

• MINOTAUR: A Posit-Based 0.42-0.50-TOPS/W Edge Transformer Inference and Training Accelerator IEEE JOURNAL OF SOLID-STATE CIRCUITS Prabhu, K., Radway, R. M., Yu, J., Bartolone, K., Giordano, M., Peddinghaus, F., Urman, Y., Khwa, W., Chih, Y., Chang, M., Mitra, S., Raina, P. 2025; 60 (4): 1311-1323

  View details for DOI 10.1109/JSSC.2025.3545731

  View details for Web of Science ID 001456403900020

• Automated Translation Validation of a Compiler for Statically Scheduled Accelerators Formal Methods in Computer-Aided Design (FMCAD) Melchert, J., et al 2025
• Aspen: A 630 FPS Real-Time Posit-Based Unified Accelerator for Extended Reality Perception Workloads IEEE Custom Integrated Circuits Conference (CICC) Feng, K., et al 2025

  View details for DOI 10.1109/CICC63670.2025.10983799

• Opal: A 16nm Coarse-Grained Reconfigurable Array for Full Sparse ML Applications IEEE Custom Integrated Circuits Conference (CICC) Chen, P., et al 2025
• Birch: A Real-Time Accelerator for Multi-Task Mixed-Domain Extended Reality Perception Workloads IEEE Asian Solid-State Circuits Conference (A-SSCC) Feng, K., et al 2025
• Opal: A 16-nm Coarse-Grained Reconfigurable Array SoC for Full Sparse Machine Learning Applications IEEE SOLID-STATE CIRCUITS LETTERS Chen, P., Wun Cheng, B., Oduoza, M., Xie, Z., Lu, R., Gautham Ravipati, S., Koul, K., Carsello, A., Mei, Y., Horowitz, M., Raina, P. 2025; 8: 293-296

  View details for DOI 10.1109/LSSC.2025.3613245

  View details for Web of Science ID 001586180000001

• Cascade: An Application Pipelining Toolkit for Coarse-Grained Reconfigurable Arrays IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS Melchert, J., Mei, Y., Koul, K., Liu, Q., Horowitz, M., Raina, P. 2024; 43 (10): 3055-3067

  View details for DOI 10.1109/TCAD.2024.3390542

  View details for Web of Science ID 001319522900009

• EMBER: Efficient Multiple-Bits-Per-Cell Embedded RRAM Macro for High-Density Digital Storage IEEE JOURNAL OF SOLID-STATE CIRCUITS Levy, A., Upton, L. R., Scott, M. D., Rich, D., Khwa, W., Chih, Y., Chang, M., Mitra, S., Murmann, B., Raina, P. 2024

  View details for DOI 10.1109/JSSC.2024.3387566

  View details for Web of Science ID 001205858500001

• Cascade: An Application Pipelining Toolkit for Coarse-Grained Reconfigurable Arrays Melchert, J., et al Languages, Tools, and Techniques for Accelerator Design (LATTE) Workshop at the ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS). 2024
• AHA: An Open-Source Framework for Co-design of Programmable Accelerators and Compilers Open-Source Computer Architecture Research (OSCAR) Workshop at the International Symposium on Computer Architecture (ISCA) Koul, K., et al 2024
• PEak: A Single Source of Truth for Hardware Design and Verification ACM Transactions on Embedded Computing Systems (TECS) Donovick, C., et al 2024
• 8-bit Transformer Inference and Fine-tuning for Edge Accelerators Yu, J., Prabhu, K., Urman, Y., Radway, R. M., Han, E., Raina, P., ACM ASSOC COMPUTING MACHINERY. 2024: 5-21

  View details for DOI 10.1145/3620666.3651368

  View details for Web of Science ID 001481645600005

• A High-Level Synthesis Based Framework for Design Space Exploration and Generation of Neural Network Accelerators AI for Fully-Automated Chip Design (AI4FACD) Workshop at the International Symposium on Computer Architecture (ISCA) Prabhu, K., et al 2024
• Onyx: A Programmable Accelerator for Sparse Tensor Algebra IEEE Hot Chips Symposium (Hot Chips) Koul, K., et al 2024
• Efficiently Synthesizing Lowest Cost Rewrite Rules for Instruction Selection Formal Methods in Computer-Aided Design (FMCAD) Daly, R., et al 2024
• Edge Continual Training and Inference with RRAM-Gain Cell Memory Integrated on Si CMOS IEEE International Electron Devices Meeting (IEDM) Liu, S., et al 2024

  View details for DOI 10.1109/IEDM50854.2024.10873546

• FastPASE: An AI-Driven Fast PPA Speculation Engine for RTL Design Space Optimization Levy, A., Walston, J., Samanta, S., Raina, P., Diamantidis, S., IEEE IEEE. 2024

  View details for DOI 10.1109/ISQED60706.2024.10528750

  View details for Web of Science ID 001229692400079

• MINOTAUR: An Edge Transformer Inference and Training Accelerator with 12 MBytes On-Chip Resistive RAM and Fine-Grained Spatiotemporal Power Gating IEEE Symposium on VLSI Technology & Circuits (VLSI) Prabhu, K., et al 2024
• Onyx: A 12nm 756 GOPS/W Coarse-Grained Reconfigurable Array for Accelerating Dense and Sparse Applications IEEE Symposium on VLSI Technology & Circuits (VLSI) Koul, K., Strange, M., Melchert, J., Carsello, A., Mei, Y., Hsu, O., Kong, T., Chen, P., Ke, H., Zhang, K., Liu, Q., Nyengele, G., Balasingam, A., Adivarahan, J., Sharma, R., Xie, Z., Torng, C., Emer, J., Kjolstad, F., Horowitz, M., Raina, P., et al 2024: 1-2

  View details for DOI 10.1109/VLSITechnologyandCir46783.2024.10631383

• Amber: A 16-nm System-on-Chip With a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra IEEE JOURNAL OF SOLID-STATE CIRCUITS Feng, K., Kong, T., Koul, K., Melchert, J., Carsello, A., Liu, Q., Nyengele, G., Strange, M., Zhang, K., Nayak, A., Setter, J., Thomas, J., Sreedhar, K., Chen, P., Bhagdikar, N., Myers, Z. A., D'Agostino, B., Joshi, P., Richardson, S., Torng, C., Horowitz, M., Raina, P. 2023

  View details for DOI 10.1109/JSSC.2023.3313116

  View details for Web of Science ID 001078350700001

• 3-D coarse-grained reconfigurable array using multi-pole NEM relays for programmable routing INTEGRATION-THE VLSI JOURNAL Levy, A., Oduoza, M., Balasingam, A., Howe, R. T., Raina, P. 2023; 88: 249-261

  View details for DOI 10.1016/j.vlsi.2022.10.001

  View details for Web of Science ID 000882493600001

• Canal: A Flexible Interconnect Generator for Coarse-Grained Reconfigurable Arrays IEEE Computer Architecture Letters Melchert, J., Zhang, K., Mei, Y., Horowitz, M., Torng, C., Raina, P. 2023

  View details for DOI 10.1109/LCA.2023.3268126

• Ultra-Dense 3D Physical Design Unlocks New Architectural Design Points with Large Benefits Srimani, T., Radway, R. M., Kim, J., Prabhu, K., Rich, D., Gilardi, C., Raina, P., Shulaker, M., Lim, S., Mitra, S. edited by IEEE IEEE. 2023

  View details for Web of Science ID 001027444200118

• Unified Buffer: Compiling Image Processing and Machine Learning Applications to Push-Memory Accelerators ACM Transactions on Architecture and Code Optimization Liu, Q., Setter, J., Huff, D., Strange, M., Feng, K., Horowitz, M., Raina, P., Kjolstad, F. 2023: 26

  View details for DOI 10.1145/3572908

• An Open-Source 4x8 Coarse-Grained Reconfigurable Array Using SkyWater 130 nm Technology and Agile Hardware Design Flow Chen, P., Tsao, C., Raina, P., IEEE IEEE. 2023

  View details for DOI 10.1109/ISCAS46773.2023.10182052

  View details for Web of Science ID 001038214602125

• EMBER: A 100 MHz, 0.86 mm<SUP>2</SUP>, Multiple-Bits-per-Cell RRAM Macro in 40 nm CMOS with Compact Peripherals and 1.0 pJ/bit Read Circuitry Upton, L. R., Levy, A., Scott, M. D., Rich, D., Khwa, W., Chih, Y., Chang, M., Mitra, S., Raina, P., Murmann, B., IEEE IEEE. 2023: 469-472

  View details for DOI 10.1109/ESSCIRC59616.2023.10268807

  View details for Web of Science ID 001088613100118

• AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers ACM Transactions on Embedded Computing Systems Koul, K., Melchert, J., Sreedhar, K., Truong, L., Nyengele, G., Zhang, K., Liu, Q., Setter, J., Chen, P., Mei, Y., Strange, M., Daly, R., Donovick, C., Carsello, A., Kong, T., Feng, K., Huff, D., Nayak, A., Setaluri, R., Thomas, J., Bhagdikar, N., Durst, D., Myers, Z., Tsiskaridze, N., Richardson, S., et al 2023; 22 (2)

  View details for DOI 10.1145/3534933

• PEak: A Single Source of Truth for Hardware Design and Verification Donovick, C., et al Programming Languages for Architecture (PLARCH) Workshop at PLDI. 2023
• APEX: A Framework for Automated Processing Element Design Space Exploration using Frequent Subgraph Analysis ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) Melchert, J., et al 2023
• PBA: Percentile-Based Level Allocation for Multiple-Bits-Per-Cell RRAM Wei, A., Levy, A., Yi, P., Radway, R. M., Raina, P., Mitra, S., Achour, S., IEEE IEEE. 2023

  View details for DOI 10.1109/ICCAD57390.2023.10323967

  View details for Web of Science ID 001116715100189

• High-density analog image storage in an analog-valued non-volatile memory array NEUROMORPHIC COMPUTING AND ENGINEERING Zheng, X., Zarcone, R., Levy, A., Khwa, W., Raina, P., Olshausen, B. A., Wong, H. 2022; 2 (4)

  View details for DOI 10.1088/2634-4386/aca92c

  View details for Web of Science ID 001062521400001

• A compute-in-memory chip based on resistive random-access memory. Nature Wan, W., Kubendran, R., Schaefer, C., Eryilmaz, S. B., Zhang, W., Wu, D., Deiss, S., Raina, P., Qian, H., Gao, B., Joshi, S., Wu, H., Wong, H. P., Cauwenberghs, G. 2022; 608 (7923): 504-512

  Abstract

  Realizing increasingly complex artificial intelligence (AI) functionalities directly on edge devices calls for unprecedented energy efficiency of edge hardware. Compute-in-memory (CIM) based on resistive random-access memory (RRAM)1 promises to meet such demand by storing AI model weights in dense, analogue and non-volatile RRAM devices, and by performing AI computation directly within RRAM, thus eliminating power-hungry data movement between separate compute and memory2-5. Although recent studies have demonstrated in-memory matrix-vector multiplication on fully integrated RRAM-CIM hardware6-17, it remains a goal for a RRAM-CIM chip to simultaneously deliver high energy efficiency, versatility to support diverse models and software-comparable accuracy. Although efficiency, versatility and accuracy are all indispensable for broad adoption of the technology, the inter-related trade-offs among them cannot be addressed by isolated improvements on any single abstraction level of the design. Here, by co-optimizing across all hierarchies of the design from algorithms and architecture to circuits and devices, we present NeuRRAM-a RRAM-based CIM chip that simultaneously delivers versatility in reconfiguring CIM cores for diverse model architectures, energy efficiency that is two-times better than previous state-of-the-art RRAM-CIM chips across various computational bit-precisions, and inference accuracy comparable to software models quantized to four-bit weights across various AI tasks, including accuracy of 99.0percent on MNIST18 and 85.7percent on CIFAR-1019 image classification, 84.7-percent accuracy on Google speech command recognition20, and a 70-percent reduction in image-reconstruction error on a Bayesian image-recovery task.

  View details for DOI 10.1038/s41586-022-04992-8

  View details for PubMedID 35978128

• CHIMERA: A 0.92-TOPS, 2.2-TOPS/W Edge AI Accelerator With 2-MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference IEEE JOURNAL OF SOLID-STATE CIRCUITS Prabhu, K., Gural, A., Khan, Z. F., Radway, R. M., Giordano, M., Koul, K., Doshi, R., Kustin, J. W., Liu, T., Lopes, G. B., Turbiner, V., Khwa, W., Chih, Y., Chang, M., Lallement, G., Murmann, B., Mitra, S., Raina, P. 2022

  View details for DOI 10.1109/JSSC.2022.3140753

  View details for Web of Science ID 000750226200001

• Efficient Routing for Coarse-Grained Reconfigurable Arrays using Multi-Pole NEM Relays IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC) Levy, A., Oduoza, M., Balasingam, A., Howe, R., Raina, P. 2022
• mflowgen: a modular flow generator and ecosystem for community-driven physical design DAC '22: Proceedings of the 59th ACM/IEEE Design Automation Conference Carsello, A., Thomas, J., Nayak, A., Chen, P., Horowitz, M., Raina, P., Torng, C. 2022: 1339–1342

  View details for DOI 10.1145/3489517.3530633

• Synthesizing Instruction Selection Rewrite Rules from RTL using SMT Daly, R., Donovick, C., Melchert, J., Setaluri, R., Bullock, N., Raina, P., Barrett, C., Hanrahan, P. edited by Griggio, A., Rungta, N. TU Wien Acad Press. 2022: 139-150

  View details for DOI 10.34727/2022/isbn.978-3-85448-053-2_20

  View details for Web of Science ID 001062691400020

• Improving Energy Efficiency of CGRAs with Low-Overhead Fine-Grained Power Domains ACM Transactions on Reconfigurable Technology and Systems Nayak, A., Zhang, K., Setaluri, R., Carsello, A., Mann, M., Torng, C., Richardson, S., Bahr, R., Hanrahan, P., Horowitz, M., Raina, P. 2022

  View details for DOI 10.1145/3558394

• Canal: A Flexible Interconnect Generator for Coarse-Grained Reconfigurable Arrays Melchert, J., et al Workshop on Democratizing Domain-Specific Accelerators (WDDSA) at MICRO. 2022
• Hardware Abstractions and Hardware Mechanisms to Support Multi-Task Execution on Coarse-Grained Reconfigurable Arrays Kong, T., et al Workshop on Democratizing Domain-Specific Accelerators (WDDSA) at MICRO. 2022
• Amber: Coarse-Grained Reconfigurable Array-Based SoC for Dense Linear Algebra Acceleration IEEE Hot Chips Symposium (Hot Chips) Feng, K., et al 2022
• Amber: A 367 GOPS, 538 GOPS/W 16nm SoC with a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra IEEE Symposium on VLSI Technology & Circuits (VLSI) Carsello, A., et al 2022
• An Agile Approach to the Design of Hardware Accelerators and Adaptable Compilers GOMACTech Daly, R., Melchert, J., Koul, K., Raina, P., et al 2022
• SAPIENS: A 64-kb RRAM-Based Non-Volatile Associative Memory for One-Shot Learning and Inference at the Edge IEEE TRANSACTIONS ON ELECTRON DEVICES Li, H., Chen, W., Levy, A., Wang, C., Wang, H., Chen, P., Wan, W., Khwa, W., Chuang, H., Chih, Y., Chang, M., Wong, H., Raina, P. 2021; 68 (12): 6637-6643

  View details for DOI 10.1109/TED.2021.3110464

  View details for Web of Science ID 000724501000107

• RADAR: A Fast and Energy-Efficient Programming Technique for Multiple Bits-Per-Cell RRAM Arrays IEEE TRANSACTIONS ON ELECTRON DEVICES Le, B. Q., Levy, A., Wu, T. F., Radway, R. M., Hsieh, E., Zheng, X., Nelson, M., Raina, P., Wong, H., Wong, S., Mitra, S. 2021; 68 (9): 4397-4403

  View details for DOI 10.1109/TED.2021.3097975

  View details for Web of Science ID 000686761500038

• Simba: Scaling Deep-Learning Inference with Chiplet-Based Architecture COMMUNICATIONS OF THE ACM Shao, Y., Cemons, J., Venkatesan, R., Zimmer, B., Fojtik, M., Jiang, N., Keller, B., Klinefelter, A., Pinckney, N., Raina, P., Tell, S. G., Zhang, Y., Dally, W. J., Emer, J., Gray, C., Khailany, B., Keckler, S. W. 2021; 64 (6): 107-116

  View details for DOI 10.1145/3460227

  View details for Web of Science ID 000656072300024

• Automated Codesign of Domain-Specific Hardware Accelerators and Compilers Raina, P., Kjolstad, F. B., Horowitz, M., Barrett, C., Fatahalian, K. ASCR Workshop on Reimagining Codesign. 2021
• CHIMERA: A 0.92 TOPS, 2.2 TOPS/W Edge AI Accelerator with 2 MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference Symposium on VLSI Circuits (VLSI) Giordano, M., Prabhu, K., Koul, K., Radway, R. M., Gural, A., Doshi, R., Khan, Z. F., Kustin, J. W., Liu, T., Lopes, G. B., Turbiner, V., Khwa, W., Chih, Y., Chang, M., Lallement, G., Murmann, B., Mitra, S., Raina, P. 2021
• One-Shot Learning with Memory-Augmented Neural Networks Using a 64-kbit, 118 GOPS/W RRAM-Based Non-Volatile Associative Memory Symposium on VLSI Technology (VLSI) Li, H., Chen, W., Levy, A., Wang, C., Wang, H., Chen, P., Wan, W., Wong, H., Raina, P. 2021
• A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm IEEE JOURNAL OF SOLID-STATE CIRCUITS Zimmer, B., Venkatesan, R., Shao, Y., Clemons, J., Fojtik, M., Jiang, N., Keller, B., Klinefelter, A., Pinckney, N., Raina, P., Tell, S. G., Zhang, Y., Dally, W. J., Emer, J. S., Gray, C., Keckler, S. W., Khailany, B. 2020; 55 (4): 920–32

  View details for DOI 10.1109/JSSC.2019.2960488

  View details for Web of Science ID 000522446300009

• Automating Vitiligo Skin Lesion Segmentation Using Convolutional Neural Networks Low, M., Raina, P. IEEE International Symposium on Biomedical Imaging (ISBI). 2020
• A Voltage-Mode Sensing Scheme with Differential-Row Weight Mapping For Energy-Efficient RRAM-Based In-Memory Computing Wan, W., Kubendran, R., Gao, B., Joshi, S., Raina, P., Wu, H., Cauwenberghs, G., Wong, H., IEEE IEEE. 2020

  View details for Web of Science ID 000668063000053

• Monte Carlo Simulation of a Three-Terminal RRAM with Applications to Neuromorphic Computing Balasingam, A., Levy, A., Li, H., Raina, P., IEEE IEEE. 2020: 197–99

  View details for Web of Science ID 000636981000050

• Creating an Agile Hardware Design Flow Bahr, R., Barrett, C., Bhagdikar, N., Carsello, A., Daly, R., Donovick, C., Durst, D., Fatahalian, K., Feng, K., Hanrahan, P., Hofstee, T., Horowitz, M., Huff, D., Kjolstad, F., Kong, T., Liu, Q., Mann, M., Melchert, J., Nayak, A., Niemetz, A., Nyengele, G., Raina, P., Richardson, S., Setaluri, R., Setter, J., Sreedhar, K., Strange, M., Thomas, J., Torng, C., Truong, L., Tsiskaridze, N., Zhang, K., IEEE IEEE. 2020

  View details for Web of Science ID 000628528400063

• A-QED Verification of Hardware Accelerators Singh, E., Lonsing, F., Chattopadhyay, S., Strange, M., Wei, P., Zhang, X., Zhou, Y., Chen, D., Cong, J., Raina, P., Zhang, Z., Barrett, C., Mitra, S., IEEE IEEE. 2020

  View details for Web of Science ID 000628528400220

• A 74TMACS/W CMOS-ReRAM Neurosynaptic Core with Dynamically Reconfigurable Dataflow and In-Situ Transposable Weights for Probabilistic Graphical Models Wan, W., Kubendran, R., Eryilmaz, S., Zhang, W., Liao, Y., Wu, D., Deiss, S., Gao, B., Raina, P., Joshi, S., Wu, H., Cauwenberghs, G., Wong, H. International Solid-State Circuits Conference (ISSCC). 2020
• A Framework for Adding Low-Overhead, Fine-Grained Power Domains to CGRAs Nayak, A., Zhang, K., Setaluri, R., Carsello, A., Mann, M., Richardson, S., Bahr, R., Hanrahan, P., Horowitz, M., Raina, P. Design, Automation and Test in Europe Conference (DATE). 2020
• Using Halide’s Scheduling Language to Analyze DNN Accelerators Yang, X., Gao, M., Liu, Q., Pu, J., Nayak, A., Setter, J., Bell, S., Cao, K., Ha, H., Raina, P., Kozyrakis, C., Horowitz, M. International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS). 2020
• A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm Zimmer, B., Venkatesan, R., Shao, Y., Clemons, J., Fojtik, M., Jiang, N., Keller, B., Klinefelter, A., Pinckney, N., Raina, P., Tell, S. G., Zhang, Y., Dally, W. J., Emer, J. S., Gray, C., Keckler, S. W., Khailany, B., IEEE IEEE. 2019: C300–C301

  View details for Web of Science ID 000531736500102

• MAGNet: A Modular Accelerator Generator for Neural Networks Venkatesan, R., Shao, Y., Wang, M., Clemons, J., Dai, S., Fojtik, M., Keller, B., Klinefelter, A., Pinckney, N., Raina, P., Zhang, Y., Zimmer, B., Dally, W. J., Emer, J., Keckler, S. W., Khailany, B., IEEE IEEE. 2019

  View details for Web of Science ID 000524676400085

• Neuro-inspired computing with emerging memories: where device physics meets learning algorithms Li, H., Raina, P., Wong, H. edited by Drouhin, H. J., Wegrowe, J. E., Razeghi, M., Jaffres, H. SPIE-INT SOC OPTICAL ENGINEERING. 2019

  View details for DOI 10.1117/12.2529916

  View details for Web of Science ID 000511161100014

• A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator Designed with a High-Productivity VLSI Methodology Khailany, B., Venkatesan, R., Shao, Y., Zimmer, B., Clemons, J., Fojtik, M., Jiang, N., Keller, B., Klinefelter, A., Pinckney, N., Raina, P., Tell, S., Zhang, Y., Dally, W., Emer, J., Gray, C., Keckler, S. Hot Chips: A Symposium on High Performance Chips (HotChips). 2019
• Creating An Agile Hardware Flow Bahr, R., Barrett, C., Bhagdikar, N., Carsello, A., Chizgi, N., Daly, R., Donovick, C., Durst, D., Fatahalian, K., Hanrahan, P., Hofstee, T., Horowitz, M., Huff, D., Kong, T., Liu, Q., Mann, M., Nayak, A., Niemetz, A., Nyengele, G., Richardson, S., Setaluri, R., Setter, J., Stanley, D., Strange, M., Thomas, J., et al Hot Chips: A Symposium on High Performance Chips (HotChips). 2019
• Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture Shao, S., Clemons, J., Venkatesan, R., Zimmer, B., Fojtik, M., Jiang, N., Keller, B., Klinefelter, A., Pinckney, N., Raina, P., Tell, S., Zhang, Y., Dally, B., Emer, J., Gray, C., Khailany, B., Keckler, S. International Symposium on Microarchitecture (MICRO). 2019
• Timeloop: A Systematic Approach to DNN Accelerator Evaluation Parashar, A., Raina, P., Shao, Y., Chen, Y., Ying, V. A., Mukkara, A., Venkatesan, R., Khailany, B., Keckler, S. W., Emer, J., IEEE IEEE. 2019: 304–15

  View details for DOI 10.1109/ISPASS.2019.00042

  View details for Web of Science ID 000470201600034

• An Energy-Scalable Accelerator for Blind Image Deblurring Raina, P., Tikekar, M., Chandrakasan, A. P. IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. 2017: 1849–62

  View details for DOI 10.1109/JSSC.2017.2682842

  View details for Web of Science ID 000404301300012

• A 0.6V 8mW 3D Vision Processor for a Navigation Device for the Visually Impaired Jeon, D., Ickes, N., Raina, P., Wang, H., Rus, D., Chandrakasan, A., IEEE IEEE. 2016: 416–U584

  View details for Web of Science ID 000382151400172

• An Energy-Scalable Accelerator for Blind Image Deblurring Raina, P., Tikekar, M., Chandrakasan, A. P., IEEE IEEE. 2016: 113–16

  View details for Web of Science ID 000386656300026

• Reconfigurable Processor for Energy-Efficient Computational Photography Rithe, R., Raina, P., Ickes, N., Tenneti, S. V., Chandrakasan, A. P. IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. 2013: 2908–19

  View details for DOI 10.1109/JSSC.2013.2282614

  View details for Web of Science ID 000326265100030

• Reconfigurable Processor for Energy-Scalable Computational Photography Rithe, R., Raina, P., Ickes, N., Tenneti, S. V., Chandrakasan, A. P., IEEE IEEE. 2013: 164–U972

  View details for Web of Science ID 000366612300065