Robert Dutton
Robert and Barbara Kleist Professor in the School of Engineering, Emeritus
Electrical Engineering
Bio
Dutton's group develops and applies computer aids to process modeling and device analysis. His circuit design activities emphasize layout-related issues of parameter extraction and electrical behavior for devices that affect system performance. Activities include primarily silicon technology modeling both for digital and analog circuits, including OE/RF applications. New emerging area now includes bio-sensors and the development of computer-aided bio-sensor design.
Academic Appointments
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Emeritus Faculty, Acad Council, Electrical Engineering
Honors & Awards
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J.J. Ebers Award, Institute of Electrical and Electronics Engineers (1987)
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Jack A. Morton Award, Institute of Electrical and Electronics Engineers (1996)
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SIA University Researcher Award, Semiconductor Industry Association (2000)
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Phil Kaufman Award, Electronic Design Automation Consortium (2006)
Boards, Advisory Committees, Professional Organizations
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member, National Academy of Engineering (1991 - Present)
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Member, Semiconductor Industries Association (2005 - Present)
Professional Education
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PhD, UC Berkeley (1970)
All Publications
- Workload Dependent NBTI and PBTI Analysis for a Sub-45nm Commercial Microprocessor IEEE IRPS, Anaheim, CA 2013: 3A.1.1-3A.1.6
- Applications of NanoNewton Dielectrophoretic Forces using Atomic Layer Deposited Oxides for Microfluidic Sample Preparation and Proteomics 2013
- Smart surfaces: Use of electrokinetics for selective modulation of biomolecular affinities 2012
- Efficient Control of DNA Transport in Nanopore-based Nanofluidic Transistors 2011
- An Electronic Microfluidic Switch using Dielectrophoresis for Control of Microparticles 2011
- Smart Surfaces: Use of Electrokinetics for Selective Modulation of Biomolecular Affinities MRS Fall Meeting, Boston, MA 2011; 1414
- Field Effect Resistor, a Single-Device-at-Pad Solution for ESD Protection in Deeply Scaled SOI Technology 2010
- Modeling and RF Analysis of Silicon Inter-band Tunnel Diode with THz Cut-off Frequency 2010
- Investigation on Output Driver with Stacked Devices for ESD Design Window Engineering 2010
- Optimized Self-Tuning for Circuit Aging 2010
- Electrical Modulation of Ion Concentration in Dual-Gated Nanochannels 2010
- ESD Design Challenges and Strategies in Deeply-Scaled Integrated Circuits 2009
- Field Effect Diode for Effective CDM ESD Protection in 45nm SOI Technology 2009
- Numerical Flicker Noise Model for Dual Channel FETs 2009
- The Role of Surface Charge and Binding Properties in Silicon-Based Field Effect Nanowire Biosensors Transducers 2009, Denver, CO 2009: 1678-1681
- Modeling and Simulation of Orientation-Dependent Fluctuations in Nanowire Field-Effect Biosensors Using the Stochastic Linearized Poisson-Boltzmann Equation 2009
- Lateral Ge/SiGe/Si Hetero-channel p-Type MOSFETs 2009
- Double-Well Field Effect Diode vs. SCR Behavior under CDM Stress in 45nm SOI Technology 2008
- Overcoming the Screen-induced Performance Limits of Nanowire Biosensors: A Simulation Study on the Effect of Electro-Diffusion Flow 2008
- Progress in Biosensor and Bioelectronics Simulations: New Applications for TCAD 2008
- Effect of Electrodiffusion Current Flow on Electrostatic Screening in Aqueous Pores J. Appl. Phys. 2008; 8 (103)
- An Effective Algorithm for Numerical Schrodinger Solver of Quantum Well Structures Journal of Computational Electronics 2008; 1 (7): 1-5
- Foreword Special Issue on Simulation and Modeling of Nanoelectronics Devices IEEE Trans. Electron Devices 2007; 9 (54): 2072 - 2078
- A Circuit-Based Noise Parameter Extraction Technique for MOSFETs 2007
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Macro-model for post-breakdown 90nm and 130nm transistors and its applications in predicting chip-level function failure after ESD-CDM events
45th Annual IEEE International Reliability Physics Symposium
IEEE. 2007: 78–85
View details for Web of Science ID 000246989600013
- Thermal Modeling and Device Noise Properties of 3D-SOI Technology 2007
- Electro-Thermal, Transient, Mixed-Mode 2D Simulation Study of SiC Power Thyristors Operating Under Pulsed-Power Conditions 2007
- Gate Oxide Reliability Characterization in the 100ps Regime with Ultra-fast Transmission Line Pulsing System 2007
- Simulation of p-n Junction Properties of Nanowires and Nanowire Arrays 2007
- RF ESD Protection Strategies: Codesign vs. Low-C Protection Microelectronics Reliability 2007; 7 (47): 1008-1015
- Physics-based Numerical Simulation for Design of High-voltage, Extremely-high Current Density SiC Power Devices 2007
- A Simple Technique for the Monte Carlo Simulation of Transport in Quantum Wells 2007
- Modeling and Measurements of Electrical and Thermal Memory Effects for RF power LDMOS 2007
- Simulations of Flicker Noise in SiGe HMOS: Body Bias Dependence SASIMI, Sapporo, Japan 2006: 238-241
- Silencer Pro: A Synthesized Compact Models-Enabled CAD Tool for Substrate Noise Analysis SASIMI, Nagoya, Japan 2006
- Modeling of Charge Trapping Induced Threshold-Voltage Instability in High-k Gate Dielectric FETs IEEE Electron Dev. Lett 2006; 6 (27): 489-491
- Numerical Simulation of Field-Induced Inter-Band Tunneling Effect Transistor Using TCAD-Based Device Simulator 64th Device Research Conference, State College, PA 2006: 119-120
- Numerical Investigation of Low Frequency Noise in MOSFETs with High-k Gate Stacks IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Monterey, CA 2006: 99-102
- Device Analysis of Linearity in RF Power Devices by Harmonic Balance Device Simulation 2006
- A Frequency-Domain VFTLP Pulse Characterization Methodology and Its Application to CDM ESD Modeling 2006
- Erratum: “Comprehensive Study of Noise Processes in Electrode Electrolyte Interfaces” [J. Appl. Phys. 96, 1074 (2004)] J. Appl. Phys. 2005; 6 (98)
- Coupled Optical and Electronic Simulations of Electrically Pumped Photonic-Crystal-Based LEDs 2005
- Coupled Electron-Phonon Transport in Nanometer-Scale Silicon Devices SRC TechCon, Portland OR 2005
- Synthesized Compact Model and Experimental Results for Substrate Noise Coupling in Lightly Doped Processes 2005
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Joule heating under quasi-ballistic transport conditions in bulk and strained silicon devices
International Conference on Simulation of Semiconductor Processes and Devices
JAPAN SOCIETY APPLIED PHYSICS. 2005: 307–310
View details for Web of Science ID 000234260200076
- Linearity Analysis of RF LDMOS Devices Utilizing Harmonic Balance Device Simulation 2005
- Electro-Thermal Simulations of Nanoscale Transistors with Optical and Acoustic Phonon Head Conduction 2005
- Effects of Local Electric Field and Effective Tunnel Mass on the Simulation of Band-to-band Tunnel Diode Model 2005
- Modeling and Simulation of Jitter in Phase-Locked Loops due to Substrate Noise 2005
- A New Method for Sensitivity Analysis of Photonic Crystal Devices 2005
- Small-Signal Modeling of RF CMOS IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Munich, Germany 2004
- Effects of Scaling on the SNR and Speed of Biosensors 2004
- New Capabilities for Verilog-A Implementations of Compact Device Models Nanotech, Boston, MA 2004
- Compact Modeling and Experimental Verification of Substrate Resistance in Lightly Doped Substrates 2004
- Synthesized Compact Models (SCM) for Substrate Noise Coupling in Mixed-Signal Ics Design, Automation and Test in Europe 2004 (DATE ’04), CNIT La Defence, Paris, France 2004: 836-841
- Technology Limits and Compact Model for SiGe Scaled FETs Nanotech, Boston, MA 2004
- Realization of Digital Noise Emulator for Characterization of Systems Exposed to Substrate Noise SASIMI, Kanazawa, Japan 2004
- Modeling of Wave Behavior of Substrate Noise Coupling for Mixed-Signal IC Design ISQED, San Jose, CA 2004: 303-308
- Electro-thermal Simulations of Strained-Si MOSFETs under ESD Conditions 2004
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Electro-thermal comparison and performance optimization of thin-body SOI and GOI MOSFETs
50th IEEE International Electron Devices Meeting
IEEE. 2004: 411–414
View details for Web of Science ID 000227158500093
- Close-in Phase Noise in Electrical Oscillators 2004
- A PMOSFET ESD Failure Caused by Localized Charge Injection 2004
- Reprogrammable, Wide Tuning Range 1.6GHz CMOS VCO with Low Phase Noise Variation 2004
- Synthesized Compact Models for Mixed Signal Design and Noise Analysis AFRA/SNDM NeoCAD Final Report 2004
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Accurate small-signal model and its parameter extraction in RF silicon MOSFETs
IEEE MTT-S International Microwave Symposium
IEEE. 2003: 2109–2111
View details for Web of Science ID 000184045100545
- Implementation of Temperature Dependent Contact Resistance Model for the Analysis of Deep Submicron Devices under ESD 2003
- A CAD-Oriented Modeling Approach of Frequency-Dependent Behavior of Substrate Noise Coupling for Mixed-Signal IC Design 2003
- Algorithm for Evaluating Nodal Vector Quantities in Device Simulation and its Applications to Modeling Quantum Mechanical Effects in Sub-50nm MOSFETs 2003
- Interconnect Parasitic Extraction of Resistance, Capacitance, and Inductance Interconnect Technology and Design for Gigascale Integration edited by Davis, J., Meindl, J., D. Kluwer Academic Publishers. 2003: 1
- Implications of Gate Tunneling and Quantum Effects on Compact Modeling in the Gate-Channel Stack NanoTech 2003
- Hydrodynamic Modeling of RF Noise in CMOS Devices 2003
- Efficient Techniques for Reducing Substrate Model Complexity in Mixed-Signal IC’s 2003
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Detailed heat generation simulations via the Monte Carlo method
IEEE International Conference on Simulation of Semiconductor Processes and Devices
IEEE. 2003: 121–124
View details for Web of Science ID 000185660800030
- Lumped, Inductorless Oscillators: How Far Can They Go 2003
- Compact Modeling and Design Using Ultra-thin SOI Devices-Implications of Gate Tunneling and Quantum Effects 2003
- Circuit Impact of Gate Leakage and Thermal Modeling for Ultra-scaled MOS Devices 2003
- Behavioral Simulation Techniques for Substrate Noise Analysis in PLL Circuits 2003
- Characterization of Zener-Tunneling Drain Leakage Current in High-Dose Halo Implants 2003
- Investigation of Thermal Breakdown Mechanism in 0.13/spl mu/m Technology ggNMOS under ESD Condition 2003
- Hydrodynamic Simulation of RF Noise in Deep-submicron MOSFETs 2003
- Modeling of Temperature Dependent Contact Resistance for Analysis of ESD Reliability 2003
- Monte Carlo Simulation of Heat Generation in Silicon Nano-Devices SRC TechCon, Dallas, TX 2003
- Device Design of SiGe HBTs with Low Distortion Characteristics using Harmonic Balance Device Simulator 2003
- Thermal Analysis of Ultra-Thin Body Device Scaling [SOI and FinFet Devices] IEEE International Electron Devices Meeting (IEDM) Technical Digest, Washington, D.C. 2003: 36.6.1-36.6.4
- Analysis of Gate Bias Induced Heating Effects in Deep Submicron ESD Protection Designs IEEE Trans. on Device and Materials Reliability 2002; 2 (2): 36-42
- AC Analysis of Thin Gate Oxide MOS with Quantum Mechanical Corrections 2002
- Performance Improvement in Larger RF LDMOSFET Power Amplifiers 2002
- Hot-Carrier Energy Distribution Model and its Application to the MOSFET Substrate Current 2002
- The Physical Phenomena Responsible for Excess Noise in Short-Channel MOS Devices 2002
- Investigation of Gate to Contact Spacing Effect on ESD Robustness of Salicided Deep Submicron Single Finger NMOS Transistors 2002
- Non-Uniform Conduction Induced Reverse Channel Length Dependence of ESD Reliability for Silicided NMOS Transistors IEEE International Electron Devices Meeting (IEDM) Technical Digest, San Francisco, CA 2002: 341-344
- An OO-PDE Solver for TCAD Apps IEEE Potentials 2002; 2 (21): 25-29
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Two-dimensional polysilicon quantum-mechanical effects in double-gate SOI
IEEE International Electron Devices Meeting
IEEE. 2002: 723–726
View details for Web of Science ID 000185143400166
- Series Resistance Calculation for Source/Drain Extension Using 2-D Device Simulation IEEE Trans. Electron Devices 2002; 7 (49): 1219-1226
- Accurate Model of Metal-Insulator-Semiconductor Interconnects 2002
- What Can Computer Aided Engineering Do for the SOC Era? 2002
- Nanoscale Heat Generation in Silicon via the Monte Carlo Method 2002
- Analytical Analysis of Short-Channel Effects in MOSFETs for sub-100nm Technology Electronics Letters 2002; 20 (38): 1222-1223
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RF LDMOS characterization and its compact modeling
IEEE MTT-S International Microwave Symposium
IEEE. 2001: 967–970
View details for Web of Science ID 000175125500225
- Localized Heating Effects and Scaling of Sub-0.18 Micron CMOS Devices 2001
- High Frequency Characterization and Modeling of VLSI On-Chip Interconnects 2001
- A Fast Analytical Technique for Estimating the Bounds of On-Chip Clock Wire Inductance 2001
- Non-uniform Bipolar Conduction in Single Finger NMOS Transistors and Implications for Deep Submicron ESD Design 2001
- Quantum Transport Model for sub-100nm CMOS Devices 2001
- Analysis and Design of ESD Protection Circuits for High-Frequency/RF Applications 2001
- Gate Bias Induced Heating Effect and Implications for the Design of Deep Submicron ESD Protection 2001
- Density Functional Theory Study of Hf and Zr Aluminates as High-k Gate Dielectrics 2001
- Impact of Gate Tunneling Current in Scaled MOS on Circuit Performance: A Simulation Study 2001
- Design Methodology for Power-Constrained Low Noise RF Circuits 2001
- Fast Placement-Dependent Full Chip Thermal Simulation 2001
- Analysis and Optimization of Distributed ESD Protection Circuits for High-Speed Mixed Signal and RF Applications 2001
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Impact of substrate resistance on drain current noise in MOSFETs
International Conference on Simulation of Semiconductor Processes and Devices (SISPAD 01)
SPRINGER-VERLAG WIEN. 2001: 182–185
View details for Web of Science ID 000172900500040
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Macroscopic quantum carrier transport modeling
International Conference on Simulation of Semiconductor Processes and Devices (SISPAD 01)
SPRINGER-VERLAG WIEN. 2001: 1–9
View details for Web of Science ID 000172900500001
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Large signal analysis of on-chip interconnects using transport based approach
5th International Symposium on Antennas, Propagation and EM Theory (ISAPE 2000)
IEEE. 2000: 309–312
View details for Web of Science ID 000165985500079
- Qualification of Hemodynamics in the Human Abdominal Aorta using Level Set Based Vascular Modeling 2000
- Advanced Electro-Thermal Modeling and Simulation Techniques for Deep Sub-Micron Devices 2000
- Well-tempered MOSFETs: 1D Versus 2D Quantum Analysis 2000
- Atomic Scale Effects of Zirconium and Hafnium Incorporation at a Model Silicon/silicate Interface by First Principles Calculations 2000
- Internet Based Modeling of Micro-Electro-Mechanical Systems 2000
- Shallow Source/Drain Extension Effects on External Resistance in Sub-0.1mm MOSFET's IEEE Trans. Elect. Dev. 2000; 3 (47): 655-658
- Effect of Surface Properties on the Effective Electrical Gap of Electrostatically Actuated Micromechanical Devices MSM 2000
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Issues in high frequency noise simulation for deep submicron MOSFETs
2nd International Conference on Unsolved Problems of Noise and Fluctuations (UPoN 99)
AMER INST PHYSICS. 2000: 401–406
View details for Web of Science ID 000086805200045
- Equivalence of van der Ziel and BSIM4 Models in Modeling the Induced Gate Noise of MOSFETs 2000
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Guidelines for the power constrained design of a CMOS tuned LNA
International Conference on Simulation of Semiconductor Processes and Devices
IEEE. 2000: 269–272
View details for Web of Science ID 000166421700067
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Sub-continuum thermal simulations of deep sub-micron devices under ESD conditions
International Conference on Simulation of Semiconductor Processes and Devices
IEEE. 2000: 54–57
View details for Web of Science ID 000166421700013
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Modeling and simulation of phonon boundary scattering in PDE-based device simulators
International Conference on Simulation of Semiconductor Processes and Devices
IEEE. 2000: 58–61
View details for Web of Science ID 000166421700014
- GEODESIC: A New and Extensible Geometry Tool and Framework with Application to MEMS 2000
- Compact Electrothermal Modeling of RF Power LDMOS 2000
- On-chip Inductance Modeling and RLC Extraction of VLSI Interconnects for Circuit Simulations 2000
- CMOS and Possible “Replacements” for 2010 2000
- Process and Layout Dependent Substrate Resistance Modeling for Deep Sub-Micron ESD Protection Devices 2000
- Full Chip Thermal Simulation 2000
- On-chip Inductance Modeling of VLSI Interconnects 2000
- Fast Wavelet Multigrid Algorithm for Solution of Electromagnetic Integral Equations Microwave and Optical Technology Letters 2000; 2 (24): 86-91
- Modelling, Calibration and Validation of Contributions to Stress in the Shallow Trench Isolation Process Sequence 1999
- A Bias Dependent Source/Drain Resistance Model in LDD MOSFET Devices for Distortion Analysis 1999
- Modeling of MOS Scaling with Emphasis on Gate Tunneling and Source/Drain External Resistance Third NASA Workshop on Device Modeling 1999
- A Novel Method to Utilize Existing TCAD Tools to Build Accurate Geometry Required for MEMS Simulation MSM, San Juan, Puerto Rico 1999
- Integration of TCAD Tools into CAD Tools for MEMS 1999
- Line Inductance Extraction and Modeling in a Real Chip with Power Grid 1999
- Investigation of Tetrahedral Automatic Mesh Generation for Finite-Element Simulation of Micro-Electro-Mechanical Switches 1999
- Complete Characterization of Electrostatically-Actuated Beams Including Effects of Multiple Discontinuities and Buckling 1999
- A Quasi-Mixed-Mode MOSFET Model for Simulation and Prediction of Substrate Resistance under ESD Stress and Layout Variations 1999
- Density-Gradient Analysis of Tunneling in MOS Structures with Ultra-Thin Oxides 1999
- Circuit Model for Power LDMOS Including Quasi-Saturation 1999
- Level Sets for Vascular Model Construction in Computational Hemodynamics 1999
- Effects of Capacitors, Resistors and Residual Charge on the static and Dynamic Performance of Electrostatically-Actuated Devices 1999
- TCAD--Yesterday, Today and Tomorrow,” Invited Paper, Special Issue on TCAD for Semiconductor Industries IEICE Trans. Electron 1999; 6 (E82-C): 791-799
- Direct Tunneling Current Model for Circuit Simulation IEEE International Electron Devices Meeting (IEDM) Technical Digest, Washington, D.C. 1999: 735-738
- Analysis of Distortion Behavior Considering Polydepletion Effect in MOS Transistors SSDM '99, Tokyo, Japan 1999
- Issues in High Frequency Noise Simulation for Deep Submicron MOSFETs 1999
- C-V and Gate Tunneling Current Characterization of Ultra-Thin Gate Oxide MOS (tox+1.3-1.8nm) 1999
- RF Noise Simulation for Submicron MOSFET's Based on Hydrodynamic Model 1999
- Utilizing Existing TCAD Simulation Tools to Create Solid Models for the Simulation Based Design of MEMS Devices 1998
- Modeling and Simulation of an RF LDMOS Device Using Harmonic Balance PISCES 1998
- Characterization of Electrostatically-Actuated Beams Through Capacitance-Voltage Measurements and Simulations 1998
- A Heterogeneous Environment for Computational Prototyping and Simulation Based Design of MEMS Devices 1998
- Elimination of Non-Simultaneous Triggering Effects in Finger-type ESD Protection Transistors Using Heterojunction Buried Layer 1998
- Layout-based 3D Solid Modeling of IC Structures and Interconnects including Electrical Parameter Extraction 1998
- Substrate Resistance Model for Simulating MOSFET Breakdown in ESD Protection TECHCON '98, Las Vegas, NV 1998
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A fast 3D modeling approach to parasitics extraction of bonding wires for RF circuits
International Electron Devices Meeting (IEDM)
IEEE. 1998: 299–302
View details for Web of Science ID 000078581800069
- Hierarchical Process Simulation for Nano-Electronics 1998
- Level Set Methods and MR Image Segmentation for Geometric Modeling in Computational Hemodynamics 1998
- A Common Mesh Implementation for Both Static and Moving Boundary Process Simulations 1998
- Design Optimization of RF Power MOSFET's Using Large Signal Analysis Device Simulation of Matching Networks 1998
- Multi-dimensional Quantum Effect Simulation Using a Density-Gradient Model and Script-level Programming Techniques 1998
- Challenges in Process Modeling for MEMS 1998
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Improved performance and thermal stability of interdigitated power RF bipolar transistors with nonlinear base ballasting
1997 Bipolar/BiCMOS Circuits and Technology Meeting
I E E E. 1997: 143–146
View details for Web of Science ID 000071093100030
- Efficient Multi-tone Harmonic Balance Simulation of Semiconductor Devices in the Presence of Linear High-Q Circuitry 1997
- A Computationally Stable Quasi-Empirical Compact Model for the Simulation of MOS Breakdown in ESD-Protection Circuit Design 1997
- Device Modeling and Simulation for VLSI Design 1997
- Next-Generation TCAD Tools--Supporting Rapid Prototyping of New Models and Numerics 1997 NASA Device Modeling Workshop 1997
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Gridding techniques for the level set method in semiconductor process and device simulation
1997 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD 97)
I E E E. 1997: 327–330
View details for Web of Science ID A1997BJ53T00082
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A new numerical formulation for thermal oxidation
1997 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD 97)
I E E E. 1997: 237–240
View details for Web of Science ID A1997BJ53T00059
- Device Modeling Challenges into the Next Century 1997
- Harmonic Balance Device Analysis of an LDMOS RF Power Amplifier with Parasitics and Matching Network 1997
- Nonlinear Dynamic Modeling of Micromachined Microwave Switches 1997
- Density-Gradient Simulations of Quantum Effects in Ultra-Thin-Oxide MOS Structures 1997
- Mixed-Technology CAD for Integrated Systems--a Confluence of Electrical and Mechanical Perspectives 1997
- Device Simulation for RF Applications IEEE International Electron Devices Meeting (IEDM) Technical Digest, Washington, D.C. 1997: 301-304
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Stabilized Element Residual Method (SERM): A posteriori error estimation for the advection-diffusion equation
JOURNAL OF COMPUTATIONAL AND APPLIED MATHEMATICS
1996; 74 (1-2): 3-17
View details for Web of Science ID A1996VT30900002
- Advanced Geometric Techniques in 3D Process Simulation 1996
- Challenges in Computational Prototyping of Deep Sub-Micron Integrated Circuit Technology 1996
- A New Practical Method to Include Recombination-Generation Process in Self-Consistent Monte Carlo Device Simulation 1996
- Circuit Embedded Device Simulation for Heterogeneous Circuitry 1996
- The TCAD Road Ahead 1996
- Efficient 3D Mesh Adaptation in Diffusion Simulation 1996
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Parasitic characterization of radio-frequency (RF) circuits using mixed-mode simulation
IEEE 1996 Custom Integrated Circuits Conference
IEEE. 1996: 445–448
View details for Web of Science ID A1996BF78V00097
- Parallel Adaptive Finite Element Software for Semiconductor Device Simulation 1996
- Accurate Doping Profile Determination Using TED/QM Models Extensible to Sub-quarter Micron nMOSFETs 1996
- TCAD for Analog Circuit Applications: Virtual Devices and Instruments 1996
- ESD Simulation to Find Correlation Between Junction Depth and Snapback Slope Using 0.35mm LDD MOSFETS 1996
- Atomic-Scale and Hierarchical Modeling for Nano-Electronics 1996
- Accurate C-V Characterization of Quarter-Micron MOS Devices Using Quantum Mechanical Corrections and AC Simulations 1996
- 2D/3D Etching and Deposition Simulation Tools Implemented with a General TCAD Geometry Server 1996
- 3D Solid Modeling of IC Structures Using Simulated Surface Topography 1996
- Modeling and Characterization of Three-Dimensional Effects in Physical Etching and Deposition Simulation 1996
- Large Signal Analysis of RF/Microwave Devices with Parasitics Using Harmonic Balance Device Simulation 1996
- Distortion Analysis of GaAs MESFETs Based on Physical Model using PISCES-HB IEEE International Electron Devices Meeting (IEDM) Technical Digest, San Francisco, CA 1996: 163-166
- A TCAD Based Golden Standard for MOS Technology Scaling and Compact Model Development 1996
- Physical Etching/Deposition Simulation with Collision-Free Boundary Movement IEEE International Electron Devices Meeting (IEDM) Technical Digest, Washington, D.C. 1995: 101-104
- An Accurate NMOS Mobility Model for 0.25mm MOSFETs 1995
- ALAMODE: A Layered Architecture for Model Development 1995
- Physical Modeling of Surface and Heterojunction for Mesa-Structured HBTs 1995
- Accurate Modeling of Coulombic Scattering, and its Impact on Scaled MOSFETs 1995
- Layout-based 3D Solid Modeling for IC 1995
- Unification of Macroscopic Impact Ionization Models for Nonhomogeneous Fields 1995
- Advance in Numerical Methods for Convective Hydrodynamic Model of Semiconductor Devices 1995
- FIESTA-HD: A Parallel Finite Element Program for Hydrodynamic Device Simulation Parallel CFD '95, California Inst. of Technology, Pasadena, CA 1995
- Quasi-Three-Dimensional Modeling of Sub-Micron LOCOS Structures IEEE Trans on Semiconductor Manufacturing 1995; 4 (8): 390-401
- Numerical Solution of Two-carrier Hydrodynamic Semiconductor Device Equations Employing a Stabilized Finite Element Method Comput. Methods in Appli. Mech. Eng. 1995; 125: 187-220
- A Vector Level Control Function for Generalized Octree Mesh Generation SISDEP '95 1995
- Virtual Instruments for Development of High Performance Circuit Technologies 1995
- Hierarchical Process Simulation for Nano-Electronics 1995
- Device/Circuit Simulation for Heterogeneous Technology 1995
- Dynamic Trapping Model for Analysis of GaAs MESFETs and Quantum Well Lasers 1995
- Hot Electron Transistors on Silicon Substrate (HESS)-A Computational Prototyping 1995
- Parallelizing a PDE Solver: Experiences with PISCES-MP 1995
- Formulation of a Tail Electron Hydrodynamic Model Based on Monte Carlo Results IEEE Electron Dev. Lett. 1995; 1 (16): 26-29
- A Methodology for Parallelizing PDE Solvers: Applications to Semiconductor Device Simulation 1995
- Large Signal Frequency Domain Device Analysis Via the Harmonic Balance Technique 1995
- Simulation of Deep Submicron SOI N-MOSFET Considering the Velocity Overshoot Effect IEEE Electron Dev. Lett 1995; 7 (16): 333-335
- Relaxation-Based Harmonic Balance Technique for Semiconductor Device Simulation ICCAD '95, San Jose, CA 1995: 700-703
- Comment on ‘Experimental Investigation and Modeling of the Role of Extended Defects during Thermal Oxidation’ [J. Appl. Phys. 74, 5821 (1993)] J. Appl. Phys. 1994; 10 (76): 6020-6021
- Layout-based Extraction of IC Electrical Behavior Model 1994
- An Alternative Method for Compact Model Construction and Parameter Extraction 1994
- Parasitic Extraction Based on SWR3D Framework 1994
- An Integrated Simulation Environment for Electronic Packages 1994
- Next-Generation Stanford TCAD-PISCES 2ET and SUPREM 007 IEEE International Electron Devices Meeting (IEDM) Technical Digest, San Francisco, CA 1994: 213-216
- A Comparison of Numerical Solutions of the Boltzmann Transport Equation for High-Energy Electron Transport Silicon IEEE Trans. Electron Devices 1994; 9 (41): 1646-1654
- Accurate Modeling of GaAs MESFET Sidegating Effects by Trapping Simulation 1994
- Simulation of Tungsten Etchback for Via and Contact Plugs 1994
- Technology CAD: Computer Simulation NTU Short Course 1994
- An Automatic Biasing Scheme for Tracing Arbitrarily Shaped I-V Curves IEEE Trans. on Computer-Aided Design 1994; 3 (13): 310-317
- Dual Energy Transport Model for Advanced Device Simulations 1994
- Integrated TCAD for OEIC Applications Invited paper, OE/LASE '94, SPIE Workshop, Los Angeles, CA 1994
- Impact Ionization Modeling Using Simulation of High Energy Tail Distributions 1994
- Grid Evolution for Oxidation Simulation using a Quadtree Based Grid Generator 1994
- A Self-Consistent Approach to Substrate Current Simulation in Submicron MOSFETs 1994
- Further Improvements in Decoupled Methods for Semiconductor Device Modeling 1994
- A General OO-PDE Solver for TCAD Applications 1994
- Space-Time Galerkin/Least Squares Finite-Element Formulation for the Hydrodynamic Device Equations IEICE Trans. Elect. 1994; 2 (E77-C): 227-236
- Semi-Empirical Local NMOS Mobility Model for 2-D Device Simulation Incorporating Screened Minority Impurity Scattering NUPAD V Conference, Honolulu, HI 1994: 3-6
- PISCES-2ET--Two Dimensional Device Simulation for Silicon and Heterostructures Stanford University 1994
- Formulation of Macroscopic Transport Model for Numerical Simulation of Semiconductor Devices Invited Paper, VLSI Design 1994; 2 (3): 211-224
- The Role of TCAD in Parasitic Analysis of ICs Invited Paper, ESSDERC '93, Grenoble, France 1993: 75-81
- Dual Energy Transport Model for Coupled Lattice and Carrier Systems 1993
- The Effect of Amorphizing Implants on Boron Diffusion 1993
- Virtual Instruments--Concept and Implementation 1993
- Improvement of Initial Solution Projection in Solving General Semiconductor Equations Including Energy Transport 1993
- Grid and Geometry Techniques for Multi-Layer Process Simulation 1993
- Solid Modeling-Based Parametric Operations for Device Design 1993 International Workshop on VLSI Process and Device Modeling (1993 VPAD) Digest, Nara, Japan 1993: 136-137
- Space-time Galerkin/Least Squares Finite-Element Formulation for the Hydrodynamic Device Equations 1993 International Workshop on VLSI Process and Device Modeling (1993 VPAD) Digest, Nara, Japan 1993: 16-17
- δ-Zone Triangulation: A Boundary Refinement Scheme for Quadtree Based Mesh 1993
- Technology CAD at Stanford University: Physics, Algorithms, Software, and Applications Invited Paper, SISDEP '93, Vienna, Austria 1993
- A Finite Element Formulation for the Hydrodynamic Semiconductor Device Equations Computer Methods in Applied Mechanics and Engineering 1993; 107: 269-298
- The Effects of High-Dose Silicon Implants on Boron Diffusion 1993
- Grid Techniques for Multi-Layer Device and Process Simulation 1993
- Dual Energy Transport Model with Coupled Lattice and Carrier Temperatures 1993
- Modeling of the Charge Balance Condition on Floating Gates and Simulation of EEPROM's IEEE Trans. on CAD 1993; 10 (12): 1499-1502
- Modeling of IC Technology--A Challenge to both Physics and Computation Bulletin of the Japan Society for Industrial and Applied Mathematics 1993; 3 (3): 16-28
- Experimental Investigation and Modeling of the Role of Extended Defects During Thermal Oxidation J. Appl. Phys. 1993; 9 (74): 5821-5827
- Robust Simulation of GaAs Devices Using Energy Transport Model 1993 International Workshop on VLSI Process and Device Modeling (1993 VPAD) Digest, Nara, Japan 1993: 32-33
- An Efficient Impact Ionization Model for Silicon Monte Carlo Simulation 1993 International Workshop on VLSI Process and Device Modeling (1993 VPAD) Digest, Nara, Japan 1993: 42-43
- The Role of Extended Defects in Dopant Diffusion 1993
- Silicon Interstitial Absorption During Thermal Oxidation at 900ºC by Extended Defects Formed Via Silicon Implantation Appl. Phys. Lett. 1993; 20 (62): 2498-2500
- Algorithms and TCAD Software Using Parallel Computation Invited Paper, 1993 International Workshop on VLSI Process and Device Modeling (1993 VPAD) Digest, Nara, Japan 1993: 10-12
- Technology CAD: Computer Simulation of IC Processes and Devices Kluwer Academic Publishers. 1993
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SCHOTTKY CONTACT EFFECTS IN THE SIDEGATING EFFECT OF GAAS DEVICES
IEEE ELECTRON DEVICE LETTERS
1992; 13 (3): 149-151
View details for Web of Science ID A1992HE79600005
- Power Semiconductor Devices and Circuits Tool Integration for Power Device Modeling Including 3D Aspects edited by Jaeklin, A., A. Plenum Press. 1992: 1
- A Finite Element Formulation for the Hydrodynamic Semiconductor Device Equations 1992
- PISCES-MP - Adaptation of a Dusty Deck for Multiprocessing 1992
- Numerical Characterization of a New Energy Transport Model International Workshop on Computational Electronics, U. Illinois, Urbana-Champaign, IL 1992
- Comments, with Reply, on ‘Shottky Contact Effects in the Sidegating Effect of GaAs Devices IEEE Electron Dev. Lett 1992; 10 (13): 547-548
- Analysis of Spurious Velocity Overshoot in Hydrodynamic Simulations NUPAD IV (Numerical Process and Device Modeling Workshop) Digest, Seattle, WA 1992: 109-114
- A Utility-based Integration System for Process Simulation IEEE Trans. CAD 1992; 7 (11): 911-920
- A Tool Towards Integration of IC Process, Device, and Circuit Simulation IEEE J. Solid-State Circuits 1992; 3 (27): 265-273
- Mega-Scale TCAD--Modeling Challenges for the 1990's 1992
- Extraction of Charge Partitioning in Multi-terminal Devices with AC Analysis Approach 1992
- Device CAD in the '90's: At the Crossroads 1992
- Robust and Efficient AC Analysis of High-speed Devices IEEE International Electron Devices Meeting (IEDM) Technical Digest, San Francisco, CA 1992: 935-938
- Analysis of Writing and Erasing Procedures of Flotox EEPROM Using the New Charge Balance Condition (CBC) Model NUPAD IV (Numerical Process and Device Modeling Workshop) Digest, Seattle, WA 1992: 65-69
- An Automated Mesh Refinement Scheme Based on Level-Control Function NUPAD IV (Numerical Process and Device Modeling Workshop) Digest, Seattle, WA 1992: 181 - 186
- Comparison between Hydrodynamic and Monte Carlo Models for Silicon Device Simulation 1992
- Numerical Techniques on Enhancing Robustness for Stress-Dependent Oxidation Simulation Using Finite Element Method in SUPREM-IV IEICE Trans. Elec. 1992; 2 (E75-C): 150-155
- An Improved Energy Transport Model Including Nonparabolicity and Non-Maxwellian Distribution Effects IEEE Elec. Dev. Lett. 1992; 1 (13): 26-28
- An Approach to Construct Pre-Conditioning Matrices for Block Iteration of Linear Equations IEEE Trans. on CAD 1992; 11 (11): 1334-1343
- A Modularized, Mixed IC Device/Circuit Simulation System 1992
- Linking TCAD to EDA - Benefits and Issues 1991
- Accurate Modeling and Numerical Techniques in Simulation of Impact-ionization Effects on BJT Characteristics 1991
- Picosecond Optoelectronic Gating of Silicon Bipolar Transistors by Locally Integrated GaAs Photoconductive Devices IEEE Electron Dev. Lett 1991; 7 (12): 379-381
- A Tool Towards Integration of IC Process, Device, and Circuit Simulation 1991
- Parallelization of Monte Carlo Simulation for Submicron MOSFET on Hypercube Multiprocessors 1991
- Parallelization of Monte Carlo Analysis on Hypercube Multiprocessors and on a Networked EWS System 1991
- 1 GHz Integrated Poly-Si and -SiGe Photoconductors with BiCMOS Compatibility 1991
- Technology Limitations for N+/P+ Polycide Gate CMOS due to Lateral Dopant Diffusion in Silicon/Polysilicon Layers IEEE Elect. Dev. Lett. 1991; 12 (12): 696-698
- Process Simulators for Silicon VLSI and High Speed GaAs Devices Integrated Circuits Laboratory 1991
- Numerical Small-Signal AC Modeling of Deep-Level-Trap Related Frequency-Dependent Output Conductance and Capacitance for GaAs MESFET's on Semi-insulating Substrates IEEE Trans. Elect. Dev. 1991; 6 (38): 1285-1289
- Modeling Capture, Emission and Impact Ionization of Deep-Level Traps for GaAs Semi-Insulating Substrates IEEE Trans. on Elect. Dev. 1991; 4 (38): 936-939
- On-chip Picosecond Time-Domain Measurement of Silicon Bipolar Transistor Characteristics Using Integrated GaAs Photoconductive Devices 1991
- Analytical Model and Numerical Simulation of High-level Injection in Si/SiGe HBTs 1991
- A STRIDE Towards Practical 3-D Device Simulation--Numerical and Visualization Considerations IEEE Trans. CAD 1991; 9 (10): 1132-1140
- A Self-consistent Discretization Scheme for Current and Energy Transport Equations SISDEP '91 Digest, Zurich 1991; 4: 235-240
- Modeling of Submicron Dry Etching Technology Using SUPREM-IV and SPEEDIE 1990
- A Utility-Based Integrated Process Simulation System 1990
- Process and Device Simulation for Metal-Oxide-Semiconductor/Very Large Scale Integration Circuits Soviet Physics-Semiconductors 1990; 5 (24): 599
- Modeling of Hot Carrier Effects for 0.5 Micron MOSFET's IEEE Trans. CAD/ICAS 1990
- Numerical Analysis of Breakdown Voltage Using Quasi Three Dimensional Device Simulation IEEE Trans. Electron Devices 1990; 4 (37): 1132-1140
- Annual Research Summary, Process and Device Modeling Principal Investigator 1990
- Etching, Deposition, Diffusion, and Oxidation Models in SUPREM-IV 1990
- Modeling and Simulation of High-Level Injection Behavior in Double Heterojunction Bipolar Transistors 1990
- Intelligent Simulation for Optimization of Fabrication Processes 1990
- Algorithms for `Curve-Tracer' Mode in Simulation of Devices with Highly Nonlinear Characteristics 1990
- A STRIDE Toward Practical 3D Device Simulation--Computational and Visualization Considerations 1990
- Sidegating Effect of GaAs MESFETs and Leakage Current in a Semi-Insulating GaAs Substrate IEEE Electron Dev. Lett. 1990; 11 (11): 505-507
- Modeling of Bias-Stress Dependent Transconductance Degradation of Submicron MOSFETs IEEE International Electron Devices Meeting (IEDM) Technical Digest, San Francisco, CA 1990: 459-462
- A Nonequilibrium One-Dimensional Quantum-Mechanical Simulation for AlGaAs/GaAs HEMT Structures IEEE Trans. Computer-Aided Design 1990; 11 (9): 1217-1224
- Metamorphosis of PISCES - Application-oriented Transformation of 2D Device Simulation Digest of Papers, SRC TECHCON '90, San Jose, CA 1990: 331-334
- Defensive Programming' in the Rapid Development of a Parallel Scientific Program IEEE Trans. on CAD 1990; 6 (9): 665-669
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TWO-DIMENSIONAL TRANSIENT ANALYSIS OF A COLLECTOR-UP ECL INVERTER
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
1989; 8 (10): 1038-1045
View details for Web of Science ID A1989AP29100002
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TWO-DIMENSIONAL ANALYSIS OF A MERGED BIPMOS DEVICE
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
1989; 8 (8): 929-932
View details for Web of Science ID A1989AF59700012
- Scaling Rules for Bipolar Transistors in BiCMOS Circuits IEEE International Electron Devices Meeting (IEDM) Technical Digest, Washington, D.C. 1989: 795-798
- A Manufacturing-Oriented Environment for Synthesis of Fabrication Processes 1989
- Metastability of CMOS Latch /Flip-flop 1989
- Improved Physical Modeling of Submicron MOSFET's Based on Parameter Extraction Using 2-D Simulation IEEE Trans. CAD/ICAS 1989; 4 (8): 370-379
- Application of Matrix Transformation Methods in Three-Dimensional Device Simulation 1989
- Turn-on Transient Analysis of a BiPMOS Device 1989
- Substrate Current Model for Submicrometer MOSFET's Based on Mean Free Path Analysis IEEE Trans. Elect. 1989; 7 (36): 1348-1354
- Picosecond Photoconductivity Using a Graded Bandgap AlxGa1-xAs Active Detecting Layer IEEE International Electron Devices Meeting (IEDM) Technical Digest, Washington, D.C. 1989: 721-724
- New Approaches in a 3-D One-Carrier Device Solver IEEE Trans. CAD/ICAS 1989; 5 (8): 528-537
- Modeling of the Distributed Gate RC Effects in MOSFET's IEEE Trans. CAD/ICAS 1989; 12 (8): 1365-1367
- Improvement in Norm-Reducing Newton Methods for Circuit Simulation IEEE Trans. CAD/ICAS 1989; 5 (8): 538-546
- A Single-ended BiCMOS Sense Circuit for Digital Circuits 1989
- Delay Analysis of BiCMOS Drivers Bipolar Circuits and Technology Meeting, Minneapolis, MN 1988: 220-222
- Parallel Electronic Circuit Simulation on iPSC System 1988
- Methodology for Submicron Device Model Development IEEE Trans. on Computer-Aided Design 1988; 2 (7): 299-306
- Verification of Analytic Point Defect Models Using SUPREM-IV IEEE Trans. on Computer-Aided Design 1988; 2 (7): 181-190
- Hot Carrier Analysis in Sub-0.1m GaAs MESFET 1988
- The Effect of Implantation Damage on Arsenic/Phosphorus Codiffusion IEEE International Electron Devices Meeting (IEDM) Technical Digest, San Francisco, CA 1988: 640-643
- SUPREM-IV Users Manual Integrated Circuits Laboratory 1988
- User Interfaces to Device and Process Simulation Tools TECHCON 88 1988
- Annual Research Summary Principal Investigator 1988
- Quasi Steady State Approximation of Interstitial Diffusion during Oxidation of Silicon IEEE Trans. on Computer-Aided Design 1988; 2 (7)
- August 3, 1988 Research Summary Principal Investigators 1988
- The Efficient Simulation of Coupled Point Defect and Impurity Diffusion IEEE Trans. on Computer-Aided Design 1988; 2 (7): 191-204
- New Approaches in a Parallel 3-D One-Carrier Device Solver NUPAD II, San Diego, CA 1988
- Bipolar Scaling for BiCMOS Circuits 1988
- A New Impact Ionization Model for Submicron MOSFET's 1988
- Modeling of Hot Carrier Effects for 0.5 Micron MOSFET's Workshop on Numerical Modeling of Processes and Devices for Integrated Circuits, San Diego, CA 1988
- Improvement in Norm-Reducing Newton Methods for Circuit Simulation NUPAD II, San Diego, CA 1988
- Optimal Structure for Ballistic Electron of AlGaAs/GaAs Heterojunction Bipolar Transistor 1987
- Future Bipolar Structure IEEE 1987 Bipolar Circuits and Technology Meeting 1987
- Two-Dimensional Transient Analysis of a Very Fast ECL Inverter 1987
- A Global Converge Technique for High Electron Mobility Transistor Circuits 1987
- A Parallel 3-D Poisson Solver on a Hypercube Multiprocessor 1987
- Users Guide to the Stanford HEMT SPICE Model Integrated Circuits Laboratory 1987
- Solid Phase Epitaxial Regrowth of Boron-Doped Polycrystalline Silicon Deposited by Low-Pressure Chemical Vapor Deposition Appl. Phys. Lett. 1987; 8 (51): 611-613
- Accurate Analysis of Impact Ionization Effects in Submicron MOSFET Devices 1987
- Avalanche Simulation Method 1987
- SUPREM Examples Stanford Electronics Laboratories 1987
- SUPREM 3.5 - Process Modeling of GaAs IEEE International Electron Devices Meeting (IEDM) Technical Digest, Washington, D.C. 1987: 256-259
- Two-Dimensional Process Modeling and SUPREM-IV 1986
- Kinetic Modeling and Measurement of Active Species Distribution During Dry Etching 1986
- Modeling LOCOS Effects on Diffusion ECS Spring Meeting, Semiconductor Silicon 1986 Digest 1986: 426-436
- Study and Modeling of Boron Diffusion at Polysilicon-silicon Interfaces San Diego Electrochem. Soc. Mtg. 1986
- The Use of Computer Aids in IC Technology Evolution 1986
- Monte Carlo Simulation of Schottky Diode Workshop on Numerical Modeling of Processes and Devices for Integrated Circuits 1986
- Submicron 2D MOS Modeling ICCAD 1986
- Quasi Steady State Approximation of Interstitial Diffusion During Oxidation of Silicon Workshop on Numerical Modeling of Processes and Devices for Integrated Circuits 1986
- Modeling Corner Oxidation Workshop on Numerical Modeling of Processes and Devices for Integrated Circuits 1986
- Modeling and Simulation for VLSI 1986
- MOS Pass Transistors with Reduced Transient Error Charge 1986
- Computer-Aided Design of Integrated Circuits Fabrication Processes for VLSI Devices Stanford Electronics Laboratories 1986
- Dopant Diffusion under Conditions of Thermal Nitridation of Si and SiO2 P. M. Fahey, R. W. Dutton, in Semiconductor Silicon edited by Huff, H., R., Abe, T., Kolbesen, B. The Electrochemical Society, Inc.. 1986: 571
- SUPREM IV Users Manual Stanford Electronics Laboratories 1986
- New n-well Fabrication Techniques Based on 2D Process Simulation IEEE International Electron Devices Meeting (IEDM) Technical Digest, Los Angeles, CA 1986: 518-521
- Multi- Window Device Analysis of Hot Carrier Transport IEEE International Electron Devices Meeting (IEDM) Technical Digest, Los Angeles, CA 1986: 563-566
- A Reply to Comments on Small Geometry MOS Transistor Capacitance Measurement Method Using Simple On-Chip Circuits IEEE Elect. Dev. Lett. 1985; 1 (6): 64-67
- New Integrated Polysilicon Photoconductors for Ultrafast Measurements on Silicon IEEE International Electron Devices Meeting (IEDM) Technical Digest, Washington, D.C. 1985: 117-120
- 2D Transient Simulation of IC Devices and Technology 1985
- Two-Dimensional Numerical Analysis of Latchup in a VLSI CMOS Technology Joint Special Issue IEEE Trans. CAD/ICAS and IEEE Trans. Elec. Dev. 1985; 4,10 (4, 32)
- Low Field Channel Pinch-Off Mechanism in GaAs MESFET's 1985
- SEDAN III--A Generalized Electronic Material Device Analysis Program Stanford Electronics Laboratories 1985
- Computer-Aided Design of Integrated Circuits Fabrication Processes for VLSI Devices ICL 17-79, Stanford Electronics Laboratories, Technical Report No. ICL-17-79 1985
- Temperature Dependence of the Fermi Level Position at Al-nGaAs Interfaces Fabricated by Molecular Beam Epitaxy 1985
- An Analytical Algorithm for Placement of Arbitrarily Sized Rectangular Blocks 1985
- Velocity Saturation Effect on Short-Channel MOS Transistor Capacitance IEEE Electron Dev. Lett. 1985; 3 (6): 120-122
- PISCES II-B Supplementary Report Stanford Electronics Laboratories 1985
- Data Requirements and Program Interfaces for Simulating Integrated-Circuit Technology Invited Paper, IEEE ElectroTechnology Review 1984: 49-51
- High Performance Latchup Free CMOS 1984
- Nonplanar Schottky Device Analysis and Applications 1984
- Latchup Free CMOS Using Guarded Schottky Barrier PMOS 1984
- Electrical End Point Detection of Plasma Etched IC Contact Openings 1984
- Simulation of Multilayer Structures for VLSI Using the SUPREM-III Process Simulation Program edited by Board, K., Owen, D., R. J. 1984
- Small Geometry MOS Transistor Capacitance Measurement Method Using Simple On-Chip Circuits IEEE Electron Dev. Lett. 1984; 10 (5): 395-397
- Modeling of Polysilicon Dopant Diffusion for Shallow-Junction Bipolar Technology IEEE International Electron Devices Meeting (IEDM) Technical Digest, San Francisco, CA 1984: 757-760
- Lump Partitioning of IC Bipolar Transistor Models for High Frequency Applications 1984
- PISCES II: Poisson and Continuity Equation Solver Stanford Electronics Laboratories 1984
- Quantum Mechanical Considerations and Electrical Characterization of Metal (Silicide)-Silicon Interfaces 1984
- Computer-Aided Process Modeling for Design and Process Control Silicon Processing, ASTM STP edited by Gupta, D., C. American Society for Testing and Materials. 1984: 407–421
- Small Geometry MOS Intrinsic and Extrinsic Capacitance Measurement Test Structures for VLSI 1984 IEEE VLSI Workshop on Test Structures, San Diego, CA 1984
- Computer-Aids for Analysis and Scaling of Extrinsic Devices IEEE International Electron Devices Meeting (IEDM) Technical Digest, San Francisco, CA 1984: 288-291
- Small Geometry MOS Transistor Measurements and Observed Short and Narrow Channel Effects 1984
- Two-Dimensional Compaction Strategies 1983
- SUPREM III-Process Simulation Toward VLSI 1983
- Resistance Extraction from Mask Layout Data IEEE Transactions on Computer Aided Design 1983; 3 (2): 145-150
- SUPREM III Stanford Electronics Laboratories, SEL 83-001 1983
- VLSI Process Modeling--SUPREM III IEEE Trans. Electron Devices 1983; 11 (30): 1438-1453
- Computer-Aided Design of Integrated Circuit Fabrication Processes for VLSI Devices ICL 17-79, Stanford Electronics Laboratories, Technical Report No. TR DXG501-83 1983
- The Role of Point Defects in VLSI Processing 1983
- SOAP, Stanford Oxidation Analysis Program Stanford Electronics Laboratories, SEL 83-002 1983
- An Overview of Process Models and Two-Dimensional Analysis Tools Stanford Electronics Laboratories, Technical Report No. G201-13 1982
- Stresses in Local Oxidation IEEE International Electron Devices Meeting (IEDM) Technical Digest, San Francisco, CA 1982: 228-232
- SUXES, Stanford University Extractor of Model Parameters (Users Manual) Stanford Electronics Laboratories 1982
- Modeling Latch-Up in CMOS Integrated Circuits IEEE Trans. on CAD of IC and S. 1982; 4 (1): 157-162
- Modeling of Polycrystalline in Silicon Structures for Integrated Circuit Fabrication Process NATO Advanced Study Institute on Process and Device Simulation for MOS-VLSI Circuits, Urbino, Italy 1982
- Analysis of Nonplanar Devices NATO Advanced Study Institute on Process and Simulation for MOS-VLSI Circuits, Urbino 1982
- Path Delay Computation for Integrated Systems 1982
- Two-Dimensional Process Simulation-SUPRA NATO Advanced Study Institute on Process and Device Simulation for MOS-VLSI Circuits, Urbino, Italy 1982
- Supplementary Report on SEDAN II Stanford Electronics Laboratory, Stanford University, Technical Report No. G201-12 1982
- Two-Dimensional Simulation of Local Oxidation 1982
- Two-Dimensional Modeling of Local Oxidation DRC 1982
- Computer-Aided Design of Integrated Circuit Fabrication Process for VLSI Devices ICL.17-79, Stanford Electronics Laboratories 1982
- Supplementary Report on SEDAN II Stanford Electronics Laboratory 1982
- Process Simulation---Physical and Numerical Considerations NASECODE II, Dublin, Ireland 1981
- Modeling and Measurement of Impurity Diffusion in Polysilicon Grains 1981
- Simplified Two-Dimensional Analysis for Time-Dependent Carrier Transport and Impurity Redistribution 1981
- Two-Dimensional Process Modeling for High Density (LOCOS) Technology 1981
- Computer Aided Design of Integrated Circuit Fabrication Processes for VLSI Devices ICL 17-79, Stanford Electronics Laboratory 1981
- Two-Dimensional Low Concentration Boron Profiles: Modeling and Measurement IEEE Trans. Electron Devices 1981; 10 (28): 1136-1147
- The Growth of Oxidation Stacking Faults and the Point Defect Generation at Si-SiO Interface During Thermal Oxidation of Silicon J. Electrochem. Soc. 1981; 5 (128): 1121-1130
- Stanford Overview in VLSI Research IEEE Circuits and Systems, Chicago 1981
- Computer Simulation in Silicon Epitaxy J. Electrochem. Soc. 1981; 4 (128): 909-918
- Practical Considerations in Technology-Oriented Device Analysis 1981
- Position Statement--Tools for Design Automation from a University Point of View 1981
- SUPRA - Stanford University Process Analysis Program Stanford Electronics Laboratory 1981
- Modeling of High-Speed, Large-Signal Transistor Switching Transients from S-Parameter Measurements IEEE International Electron Devices Meeting (IEDM) Technical Digest, Washington, D.C. 1981: 608-611
- Optimization of IC Processes Using SUPREM Stanford Electronics Laboratory 1981
- Nonplanar VLSI Device Analysis Using the Solution of Poisson's Equation IEEE Trans. Electron Devices 1980; 8 (27): 1520-1532
- Two-Dimensional Analysis for Device Modeling Technical Report No. G201-7, Stanford Electronics Laboratory 1980
- Segregation of Arsenic to the Grain Boundaries in Polycrystalline Silicon J. Electrochem. Soc. 1980; 10 (127): 2227-2229
- A Surface Kinetics Model for Plasma Etching 1980
- Transient Analysis of MOS Transistors IEEE Trans. Electron Devices 1980; 8 (27): 1571-1578
- Process Design Using Coupled 2D Process and Device Simulations IEEE International Electron Devices Meeting (IEDM) Technical Digest, Washington, D.C. 1980: 223-226
- Enhanced Diffusion in the Single Crystal Silicon Substrate During Oxidation of a Deposited Polysilicon Doping Source 1980
- Computer Modeling for VLSI 1980
- Computer Aided Engineering of Semiconductor Integrated Circuits ICL 17-78, Stanford Electronics Laboratory 1980
- Process Modeling of Multilayer Structures Involving Polycrystalline Silicon IEEE International Electron Devices Meeting (IEDM) Technical Digest, Washington, D.C. 1980: 219-222
- Process and Device Simulation for VLSI Modeling University of Maryland, UCLA 1980
- Two-Dimensional Process Modeling for High-Density (LOCOS) Technology 1980
- Computer Simulation in Silicon Epitaxy ECS Extended Abstracts, Boston, MA 1979: 352-358
- A Desktop-Computer Based Process Control and Device Characterization System 1979
- Computer-Aided Engineering of Semiconductor Integrated Circuits ICL 7-77, Stanford Electronics Laboratory 1979
- The Lateral Effect of Oxidation-Enhanced Diffusion (LOED) in <100> Silicon 1979
- One-Dimensional Semiconductor Device Analysis (SEDAN) SEL 78-020, Stanford Electronics Laboratory 1979
- Measurement of Two-dimensional Profiles Near Locally Oxidized Regions 1979
- Bulk Punchthrough Characterization of Submicron Transistor Using Poisson's Solution 1979
- The Rate-Control Model of Oxidation-Stacking Faults Growth in Silicon ECS Meeting, Los Angeles, CA 1979
- The Lateral Effect of Oxidation on Boron Diffusion in <100> Silicon Appl. Phys. Lett. 1979; 8 (27): 1520-1532
- Short-Channel MOSFET's in the Punchthrough Current Mode IEEE ED/JSSC Joint VLSI Special Issue 1979; 2 (14): 368-375
- Sensitivity of Electrical Parameters to Fabrication Variables for a Phosphorus Bipolar Process ECS Extended Abstracts, Boston, MA 1979: 369-372
- Process Statistics of Submicron MOSFET's IEEE International Electron Devices Meeting (IEDM) Technical Digest, Washington DC 1979: 34-37
- Process Simulation for Device Design and Control 1979 ISSCC Digest of Technical Papers 1979: 244-245
- On Redistribution of Boron During Thermal Oxidation of Silicon J. Electrochem. Soc. 1979; 11 (126): 2001-2007
- Oxidation Rate Dependence of B and P Oxidation-Enhanced Diffusions in <100> Silicon ECS Extended Abstract, Boston, MA. 1979: 356-359
- A Simplified Two-Dimensional Analysis of MOS Devices 1979
- A Charge-Oriented Model for MOS Transistor Capacitances IEEE J. Solid-State Circuits 1978; 5 (13): 703-708
- Latch-Up in CMOS Integrated Circuits 1978
- Characteristics of Short Channel MOSFETs in the Punch-Through Current Mode 1978
- SUPREM II -- A Program for IC Process Modeling and Simulation SEL 78-020, Stanford Electronics Laboratory 1978
- High Speed Implementation and Experimental Evaluation of Multilayer Spreading Resistance Analysis J. Electrochem. Soc. 1978; 7 (125): 1170-1176
- Process Modeling for IC Device Technologies 1978
- Modeling Latch-Up in CMOS Integrated Circuits 1978
- An Analysis of Latch-up Prevention in CMOS IC’s Using an Epitaxial-buried Layer Process 1978
- Characteristics of Short Channel MOSFETS in the Punch-through Current Mode 1978
- Statistical Circuit Simulation on Computer Aided Design 1978
- Computer Aided Engineering of Semiconductor Integrated Circuits SEL 78-011, Stanford Electronics Laboratory 1978
- Model Parameter Correlations in Statistical Circuit Simulation 1978
- Oxidation-Enhanced Diffusion of Arsenic and Phosphorus in Near-Intrinsic <100> Silicon Appl. Phys. Lett. 1978; 12 (33): 1030-1033
- Coupling of Process and Device Simulation for VLSI WESCON 1978
- An Integrated Injection Logic I2L Macromodel WESCON 77, Paper 11/2, WESCON Technical Program 1977: 1-9
- Modeling of Moving Boundaries During Semiconductor Fabrication Processes 1977
- SUPREM I -- A Program for IC Process Modeling and Simulation Stanford Electronics Laboratory Technical Report, SEL 77-006 1977
- Bipolar IC Device Statistics - An Experimental Study 1977
- Technology Modeling for IC Fabrication Modeling Semiconductor Devices (Journees D' Electronique 1977), Lausanne, Switzerland 1977
- Effects of the Diffused Impurity Profile on the DC Characteristics of VMOS and DMOS Devices IEEE J. Solid-State Circuits 1977; 4 (12): 356-362
- Modeling Integrated Injection Logic (I2L) Performance and Operational Limits IEEE J. Solid-State Circuits 1977; 5 (12): 450-462
- Oxidation and Epitaxy Stanford Electronics Laboratory Technical Report, Technical Report 5021-1 1977
- Bipolar Models for Statistical IC Design Process and Device Modeling for Integrated Circuit Design 1977
- Stanford Electronics Laboratory Technical Report Technical Report 5021-2 1977
- Invited Lectures on Process Models, Statistical Models and SUPREM 1977
- Local Truncation Error Control for Circuit Simulators 1977
- Modeling I2L Performance and Operational Limits IEEE ISSCC, Technical Digest 1977: 46-47
- A Charge-Oriented Model for MOS Transistor Capacitances 1977
- Spreading Resistance of Impurity Profile Stanford Electronics Laboratory Technical Report, SEL 76-004 1977
- Integrated Systems and Technologies in Stanford Curricula ISHM, Albuquerque, NM 1977
- A Computer Aided Design Model for High Voltage MOS (DMOS) Transistors IEEE J. Solid-State Circuits 1976; 5 (11): 718-726
- High Speed Multilayer Corrections for Spreading Resistance 1976
- An Integrated Injection Logic (I2L) Macromodel Including Current Redistribution Effect IEEE J. Solid-State Circuits 1976; 5 (11): 648-657
- A Two-Lump Transistor Model for Computer Circuit Simulation IEEE J. Solid-State Circuits 1976; 5 (11): 726-730
- Mini-MSINC--A minicomputer Simulator for MOS Circuits with Modular Built-in Model IEEE J. Solid-State Circuits 1976; 5 (11): 730-732
- Characterization and Modeling of Simultaneously Fabricated DMOS and VMOS Transistors 1976
- Boron Redistribution after Oxidation 1976
- Modeling Integrated Injection Logic Asilomar, Fall 1976
- Minicomputer Calculation of the DC Operating Point of Bipolar Circuits Stanford Electronics Laboratory Technical Report, SEL 76-012 1976
- Successful Circuit Simulation Using Minicomputers 1976
- CAD Modeling of the Two-Terminal Uniform Distributed RC Line 1975
- DMOS Experimental and Theoretical Study 1975
- Bipolar Transistor Modeling of Avalanche Generation for Computer Circuit Simulation IEEE Trans. Electron Devices 1975; 6 (22): 334-338
- of Computer-Aided Design Techniques to Process, Device, and Circuit Designs Stanford Electronics Laboratory Technical Report, SEL-75-017 1975
- A Monolithic Analog Signal Processor for Ultrasonic Imaging Systems 1975
- Lump Partitioning of Bipolar Junction Transistor Models for High Frequency Application 1975
- Fabrication Process Modeling Applied to IC npn Transistors Using a Minicomputer 1975
- An Experimental and Theoretical Analysis of Double-Diffused MOS Transistors IEEE J. Solid-State Circuits 1975; 5 (10): 322-331
- Threshold Voltage Controllability in Double Diffused-MOS Transistors IEEE Trans. Electron Devices 1974; 12 (21): 778-784
- MSINC- A Modular Simulator for Integrated Nonlinear Circuits with MOS Model Example 1974
- Extraction and Sensitivity of Parameters for Higher-Order MOS Models 1974
- MSINC - A MOS Simulator for Integrated Nonlinear Circuits with Modular Built-in Model Stanford Electronics Laboratory Technical Report, SEL-74-038 1974
- Techniques and Applications of Computer-Aided Circuit Simulation for Integrated Circuit and System Design. Part II: CAD Applications Stanford Electronics Laboratory Technical Report, SEL-74-017 1974
- Techniques and Applications of Computer-Aided Circuit Simulation for Integrated Circuits and System Design. Part I: CAD Techniques Stanford Electronics Laboratory Technical Report, SEL-74-005 1974
- Threshold Voltage Controllability in Double Diffused-MOS Transistors IEEE International Electron Devices Meeting (IEDM) Technical Digest, Washington, D.C. 1973: 68-71
- Large Grain Tellurium Thin Films Thin Solid Films 1972; 11: 229-236
- Electrical Properties of Tellurium Thin Films 1971
- Forward Current-Voltage and Switching Characteristics of p+-n-n+ (Epitaxial) Diodes IEEE Trans. Electron Devices 1969; 16: 458-467
- Thin Film CdS-CdTe Heterojunction Diodes Solid-State Electronics 1968; 11: 749-756
- Computer-Aided Design of Integrated Circuits Fabrication Processes for VLSI Devices ICL 17-79, Stanford Electronics Laboratories, Technical Report No. TR DXG501-84 1894
- Proc. of the ICSSDP Simulation of Multilayer Structures for VLSI Using the SUPREM-III Process Simulation Program edited by R.J., Board, D. Pineridge Press.
- New Challenges in Device Design for Integrated Electronic Systems
- Analysis of Advanced Devices Using Industry-Networked Technology CAD (ALADDIN-CAD) Final Report, California Competitive Technology Program (CompTech Grant # C90-072).
- Simulation of Integrated Circuits Design Process and Device Modeling for Integrated Circuit Design
- Technology CAD at Stanford University: Physics, Algorithms, Software, and Applications edited by Fasching, F., Halama, S., Selberherr, S. Microelectronics Journal. 1993, 1995