I am a first-year master’s student pursuing MS EE (Computer Architecture and Embedded Systems track) at Stanford University.

My research interests lie primarily in the area of Computer Systems Architecture. My research involves the development and implementation of efficient and effective hardware architectures for a given application. I am constantly striving to improve my understanding of computing systems, to develop better intuition of the tradeoffs involved, and make better well-informed hardware architecture decisions.

Before starting my MS, I worked at Nvidia as an ASIC Design Engineer in the GPU Hardware Security team, where I contributed to the development of computer chips used in datacenters. Prior to that I worked at Ceremorphic a stealth startup on their first energy-efficient AI supercomputing test chip and gained insight into their heterogenous computing model.

I completed my undergraduate studies at BITS Pilani, India. During this period, I was associated with Prof. Akash Kumar at the Chair for Processor Design, TU Dresden for my year-long undergraduate thesis. I also had the opportunity to work under Prof. Gerd Grau during my MITACS Globalink Summer Internship.

Work Experience

  • ASIC Engineer - GPU Hardware Security Team, NVIDIA Corporation (1/3/2022 - 8/18/2023)

    1. Developed C++based functional model of Message-Network-on-Chip a MCU peripheral for secure message transfer
    2. Implemented Recovery Controller’s RTL involved in the recovery of GPU’s firmware & security critical parameters
    3. It supports interface logic to access critical data from external (I2C or PCIe) and internal (GPU sub-unit) clients
    4. Altered existing GPU Foundational Security Processor’s functional model to support generational feature updates


    Nvidia Graphics India Pvt Ltd - Discovery Building

  • Processor Design Engineer - Machine Learning Subsystem, Ceremorphic, Inc. - Stealth Startup (1/4/2021 - 12/31/2021)

    1. Involved in the development of microarchitecture specifications and RTL design for the ML Neural Processor IP
    2. Designed parallel RTL datapaths to support FP32 deployment & INT8 inference with channel-wise quantization
    3. Developed a Python based simulation model of the Neural Processor IP to facilitate architectural exploration
    4. Altered the existing pipelined Neural Processor IP architecture to meet a higher 2 GHz clock speed requirement


    Ceremorphic Technologies Private Limited

  • Guest Researcher, Chair for Processor Design, Technische Universitat Dresden (1/5/2020 - 12/27/2020)

    1. Explored Posit numerical format for energy efficient deployment of DNNs on FPGA-based embedded systems
    2. Analysed accuracy, compute delay & memory footprint impact of Posit quantization on DNN model parameters
    3. Designed Posit to Fixed-point conversion algorithm : Posits for data movement, storage & Fixed-point compute
    4. Implemented a Processing Element to ascertain the impact of the proposed hardware design in a DNN FC layer


    Center For Advancing Electronic Dresden