Suresh Nambi

Bio

I am an AI/ML Compute Architect specializing in cross-stack optimization for LLMs and deep learning systems. Currently I am focused on datacenter-scale performance from application analysis to hardware design :

- Full-stack workload analysis and optimization from model architecture to writing hardware kernels
- Multi-Node Performance Simulation, Roofline modeling and architecture-specific optimizations
- Achieve efficiency at scale by delivering improvements in training/inference through novel microarchitectures

I am a master’s student pursuing MS EE (Software and Hardware Systems) at Stanford University. Before starting my MS, I worked at Nvidia as an ASIC Design Engineer in the GPU Hardware Security team, where I contributed to the development of computer chips used in datacenters. Prior to that I worked at Ceremorphic a stealth startup on their first energy-efficient AI supercomputing test chip and gained insight into their heterogenous computing model.

I completed my undergraduate studies at BITS Pilani, India. During this period, I was associated with Prof. Akash Kumar at the Chair for Processor Design, TU Dresden for my year-long undergraduate thesis. I also had the opportunity to work under Prof. Gerd Grau during my MITACS Globalink Summer Internship.