Bio


Priyanka Raina is an Assistant Professor in Electrical Engineering at Stanford University. Previously, she was a Visiting Research Scientist in the Architecture Research Group at NVIDIA​ ​Corporation. She received her Ph.D. degree in 2018 and S.M. degree in 2013 in Electrical Engineering and​ ​Computer Science from MIT and her B.Tech. degree in Electrical Engineering from Indian Institute of Technology​ ​(IIT) Delhi in 2011.​ Priyanka’s current research interests are designing energy-efficient and high-performance circuits and systems for image, vision and machine learning applications on mobile devices, integrating emerging non volatile memory technologies in accelerator architectures, and creating frameworks for improving hardware/software system design productivity.

Academic Appointments


Honors & Awards


  • Hellman Fellow, Stanford (2019)
  • Best Young Scientist Paper Award, ESSCIRC 2016 (2017)
  • ISSCC Student Research Preview Award, ISSCC 2016 (2017)
  • Bimla Jain Medal, IIT Delhi (2011)
  • Institute Silver Medal, IIT Delhi (2011)
  • Gold Medal at Indian National Chemistry Olympiad, InChO (2007)

Professional Education


  • Ph.D., Massachusetts Institute of Technology (MIT), Electrical Engineering and Computer Science (2018)
  • S.M., Massachusetts Institute of Technology (MIT), Electrical Engineering and Computer Science (2013)
  • B.Tech., Indian Institute of Technology (IIT) Delhi, Electrical Engineering (2011)

Current Research and Scholarly Interests


For Priyanka's research please visit her group research page at https://stanfordaccelerate.github.io

Stanford Advisees


All Publications


  • A 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Inference Accelerator with Ground-Referenced Signaling in 16nm Zimmer, B., Venkatesan, R., Shao, S., Clemons, J., Fojtik, M., Jiang, N., Keller, B., Klinefelter, A., Pinckney, N. Journal of Solid-State Circuits (JSSC). 2020
  • A 74TMACS/W CMOS-ReRAM Neurosynaptic Core with Dynamically Reconfigurable Dataflow and In-Situ Transposable Weights for Probabilistic Graphical Models Wan, W., Kubendran, R., Eryilmaz, S., Zhang, W., Liao, Y., Wu, D., Deiss, S., Gao, B., Raina, P., Joshi, S., Wu, H., Cauwenberghs, G., Wong, H. International Solid-State Circuits Conference (ISSCC). 2020
  • A Framework for Adding Low-Overhead, Fine-Grained Power Domains to CGRAs Nayak, A., Zhang, K., Setaluri, R., Carsello, A., Mann, M., Richardson, S., Bahr, R., Hanrahan, P., Horowitz, M., Raina, P. Design, Automation and Test in Europe Conference (DATE). 2020
  • Using Halide’s Scheduling Language to Analyze DNN Accelerators Yang, X., Gao, M., Liu, Q., Pu, J., Nayak, A., Setter, J., Bell, S., Cao, K., Ha, H., Raina, P., Kozyrakis, C., Horowitz, M. International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS). 2020
  • Automating Vitiligo Skin Lesion Segmentation Using Convolutional Neural Networks Low, M., Raina, P. IEEE International Symposium on Biomedical Imaging (ISBI). 2020
  • A-QED Verification of Hardware Accelerators Singh, E., Lonsing, F., Chattopadhyay, S., Strange, M., Wei, P., Zhang, X., Zhao, Y., Cong, J., Chen, D., Zhang, Z., Raina, P., Barrett, C., Mitra, S. Design Automation Conference (DAC). 2020
  • Timeloop: A Systematic Approach to DNN Accelerator Evaluation Parashar, A., Raina, P., Shao, Y., Chen, Y., Ying, V. A., Mukkara, A., Venkatesan, R., Khailany, B., Keckler, S. W., Emer, J., IEEE IEEE. 2019: 304–15
  • A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm Zimmer, B., Venkatesan, R., Shao, Y., Clemons, J., Fojtik, M., Jiang, N., Keller, B., Klinefelter, A., Pinckney, N., Raina, P., Tell, S., Zhang, Y., Dally, W., Emer, J., Gray, C., Keckler, S., Khailany, B. Symposium on VLSI Circuits (VLSI). 2019
  • Neuro-inspired computing with emerging memories: where device physics meets learning algorithms Li, H., Raina, P., Wong, H., Drouhin, H. J., Wegrowe, J. E., Razeghi, M., Jaffres, H. SPIE-INT SOC OPTICAL ENGINEERING. 2019

    View details for DOI 10.1117/12.2529916

    View details for Web of Science ID 000511161100014

  • A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator Designed with a High-Productivity VLSI Methodology Khailany, B., Venkatesan, R., Shao, Y., Zimmer, B., Clemons, J., Fojtik, M., Jiang, N., Keller, B., Klinefelter, A., Pinckney, N., Raina, P., Tell, S., Zhang, Y., Dally, W., Emer, J., Gray, C., Keckler, S. Hot Chips: A Symposium on High Performance Chips (HotChips). 2019
  • Creating An Agile Hardware Flow Bahr, R., Barrett, C., Bhagdikar, N., Carsello, A., Chizgi, N., Daly, R., Donovick, C., Durst, D., Fatahalian, K., Hanrahan, P., Hofstee, T., Horowitz, M., Huff, D., Kong, T., Liu, Q., Mann, M., Nayak, A., Niemetz, A., Nyengele, G., Richardson, S., Setaluri, R., Setter, J., Stanley, D., Strange, M., Thomas, J., et al Hot Chips: A Symposium on High Performance Chips (HotChips). 2019
  • Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture Shao, S., Clemons, J., Venkatesan, R., Zimmer, B., Fojtik, M., Jiang, N., Keller, B., Klinefelter, A., Pinckney, N., Raina, P., Tell, S., Zhang, Y., Dally, B., Emer, J., Gray, C., Khailany, B., Keckler, S. International Symposium on Microarchitecture (MICRO). 2019
  • MAGNet: A Modular Accelerator Generator for Neural Networks Venkatesan, R., Shao, S., Wang, M., Clemons, J., Dai, S., Fojtik, M., Keller, B., Klinefelter, A., Pinckney, N., Raina, P., Zhang, Y., Zimmer, B., Dally, B., Emer, J., Keckler, S., Khailany, B. International Conference On Computer Aided Design (ICCAD). 2019
  • An Energy-Scalable Accelerator for Blind Image Deblurring Raina, P., Tikekar, M., Chandrakasan, A. P. IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. 2017: 1849–62
  • A 0.6V 8mW 3D Vision Processor for a Navigation Device for the Visually Impaired Jeon, D., Ickes, N., Raina, P., Wang, H., Rus, D., Chandrakasan, A., IEEE IEEE. 2016: 416–U584
  • An Energy-Scalable Accelerator for Blind Image Deblurring Raina, P., Tikekar, M., Chandrakasan, A. P., IEEE IEEE. 2016: 113–16
  • Reconfigurable Processor for Energy-Efficient Computational Photography Rithe, R., Raina, P., Ickes, N., Tenneti, S. V., Chandrakasan, A. P. IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. 2013: 2908–19
  • Reconfigurable Processor for Energy-Scalable Computational Photography Rithe, R., Raina, P., Ickes, N., Tenneti, S. V., Chandrakasan, A. P., IEEE IEEE. 2013: 164–U972