
Priyanka Raina
Assistant Professor of Electrical Engineering and, by courtesy, of Computer Science
Bio
Priyanka Raina is an Assistant Professor in Electrical Engineering at Stanford University. Previously, she was a Visiting Research Scientist in the Architecture Research Group at NVIDIA Corporation. She received her Ph.D. degree in 2018 and S.M. degree in 2013 in Electrical Engineering and Computer Science from MIT and her B.Tech. degree in Electrical Engineering from Indian Institute of Technology (IIT) Delhi in 2011. Priyanka’s current research interests are designing energy-efficient and high-performance circuits and systems for image, vision and machine learning applications on mobile devices, integrating emerging non volatile memory technologies in accelerator architectures, and creating frameworks for improving hardware/software system design productivity.
Academic Appointments
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Assistant Professor, Electrical Engineering
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Assistant Professor (By courtesy), Computer Science
Honors & Awards
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Hellman Fellow, Stanford (2019)
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Best Young Scientist Paper Award, ESSCIRC 2016 (2017)
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ISSCC Student Research Preview Award, ISSCC 2016 (2017)
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Bimla Jain Medal, IIT Delhi (2011)
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Institute Silver Medal, IIT Delhi (2011)
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Gold Medal at Indian National Chemistry Olympiad, InChO (2007)
Professional Education
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Ph.D., Massachusetts Institute of Technology (MIT), Electrical Engineering and Computer Science (2018)
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S.M., Massachusetts Institute of Technology (MIT), Electrical Engineering and Computer Science (2013)
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B.Tech., Indian Institute of Technology (IIT) Delhi, Electrical Engineering (2011)
Current Research and Scholarly Interests
For Priyanka's research please visit her group research page at https://stanfordaccelerate.github.io
2021-22 Courses
- Design Projects in VLSI Systems I
EE 272 (Win) - Design Projects in VLSI Systems II
EE 372 (Spr) - Emerging Non-Volatile Memory Devices and Circuit Design
EE 309B (Win) - Introduction to VLSI Systems
EE 271 (Aut) - Semiconductor Memory Devices and Circuit Design
EE 309A (Aut) -
Independent Studies (3)
- Master's Thesis and Thesis Research
EE 300 (Aut, Win, Spr, Sum) - Special Studies and Reports in Electrical Engineering
EE 391 (Aut, Win, Spr, Sum) - Special Studies or Projects in Electrical Engineering
EE 390 (Aut, Win, Spr, Sum)
- Master's Thesis and Thesis Research
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Prior Year Courses
2020-21 Courses
- Design Projects in VLSI Systems I
EE 272A (Win) - Design Projects in VLSI Systems II
EE 272B (Spr) - Emerging Non-Volatile Memory Devices and Circuit Design
EE 309B (Win) - Semiconductor Memory Devices and Circuit Design
EE 309A (Aut)
2019-20 Courses
- Design Projects in VLSI Systems
EE 272 (Win) - Introduction to VLSI Systems
EE 271 (Aut)
2018-19 Courses
- Design Projects in VLSI Systems
EE 272 (Win) - Introduction to VLSI Systems
EE 271 (Aut)
- Design Projects in VLSI Systems I
Stanford Advisees
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Doctoral Dissertation Reader (AC)
Nikhil Bhagdikar, Alex Carsello, Rohan Doshi, Massimo Giordano, Taeyoung Kong, Qiaoyi(Joey) Liu, Shuhan Liu, Zachary Myers, Ankita Nayak, Gedeon Nyengele, Alex Rucker, Kavya Sreedhar, Maxwell Strange, Tian Zhao -
Doctoral Dissertation Advisor (AC)
Po-Han Chen, Kathleen Feng, Kalhan Koul, Akash Levy, Jackson Melchert -
Master's Program Advisor
John Espera, Kavya Somasi, Jeffrey Yu -
Doctoral (Program)
Po-Han Chen, Nikhil Poole, Kartik Prabhu, Khushal Sethi, Ritvik Sharma
All Publications
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CHIMERA: A 0.92-TOPS, 2.2-TOPS/W Edge AI Accelerator With 2-MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference
IEEE JOURNAL OF SOLID-STATE CIRCUITS
2022
View details for DOI 10.1109/JSSC.2022.3140753
View details for Web of Science ID 000750226200001
- Efficient Routing for Coarse-Grained Reconfigurable Arrays using Multi-Pole NEM Relays IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC) 2022
- Enabling Reusable Physical Design Flows with Modular Flow Generators Design Automation Conference (DAC) 2022
- An Agile Approach to the Design of Hardware Accelerators and Adaptable Compilers GOMACTech 2022
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SAPIENS: A 64-kb RRAM-Based Non-Volatile Associative Memory for One-Shot Learning and Inference at the Edge
IEEE TRANSACTIONS ON ELECTRON DEVICES
2021; 68 (12): 6637-6643
View details for DOI 10.1109/TED.2021.3110464
View details for Web of Science ID 000724501000107
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RADAR: A Fast and Energy-Efficient Programming Technique for Multiple Bits-Per-Cell RRAM Arrays
IEEE TRANSACTIONS ON ELECTRON DEVICES
2021; 68 (9): 4397-4403
View details for DOI 10.1109/TED.2021.3097975
View details for Web of Science ID 000686761500038
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Simba: Scaling Deep-Learning Inference with Chiplet-Based Architecture
COMMUNICATIONS OF THE ACM
2021; 64 (6): 107-116
View details for DOI 10.1145/3460227
View details for Web of Science ID 000656072300024
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Best Papers From Hot Chips 32
IEEE MICRO
2021; 41 (2): 6
View details for DOI 10.1109/MM.2021.3060294
View details for Web of Science ID 000639559200002
- Automated Codesign of Domain-Specific Hardware Accelerators and Compilers ASCR Workshop on Reimagining Codesign. 2021
- CHIMERA: A 0.92 TOPS, 2.2 TOPS/W Edge AI Accelerator with 2 MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference Symposium on VLSI Circuits (VLSI) 2021
- One-Shot Learning with Memory-Augmented Neural Networks Using a 64-kbit, 118 GOPS/W RRAM-Based Non-Volatile Associative Memory Symposium on VLSI Technology (VLSI) 2021
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A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm
IEEE JOURNAL OF SOLID-STATE CIRCUITS
2020; 55 (4): 920–32
View details for DOI 10.1109/JSSC.2019.2960488
View details for Web of Science ID 000522446300009
- Automating Vitiligo Skin Lesion Segmentation Using Convolutional Neural Networks IEEE International Symposium on Biomedical Imaging (ISBI). 2020
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A Voltage-Mode Sensing Scheme with Differential-Row Weight Mapping For Energy-Efficient RRAM-Based In-Memory Computing
IEEE. 2020
View details for Web of Science ID 000668063000053
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Monte Carlo Simulation of a Three-Terminal RRAM with Applications to Neuromorphic Computing
IEEE. 2020: 197–99
View details for Web of Science ID 000636981000050
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Creating an Agile Hardware Design Flow
IEEE. 2020
View details for Web of Science ID 000628528400063
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A-QED Verification of Hardware Accelerators
IEEE. 2020
View details for Web of Science ID 000628528400220
- A 74TMACS/W CMOS-ReRAM Neurosynaptic Core with Dynamically Reconfigurable Dataflow and In-Situ Transposable Weights for Probabilistic Graphical Models International Solid-State Circuits Conference (ISSCC). 2020
- A Framework for Adding Low-Overhead, Fine-Grained Power Domains to CGRAs Design, Automation and Test in Europe Conference (DATE). 2020
- Using Halide’s Scheduling Language to Analyze DNN Accelerators International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS). 2020
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A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm
IEEE. 2019: C300–C301
View details for Web of Science ID 000531736500102
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MAGNet: A Modular Accelerator Generator for Neural Networks
IEEE. 2019
View details for Web of Science ID 000524676400085
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Neuro-inspired computing with emerging memories: where device physics meets learning algorithms
SPIE-INT SOC OPTICAL ENGINEERING. 2019
View details for DOI 10.1117/12.2529916
View details for Web of Science ID 000511161100014
- A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator Designed with a High-Productivity VLSI Methodology Hot Chips: A Symposium on High Performance Chips (HotChips). 2019
- Creating An Agile Hardware Flow Hot Chips: A Symposium on High Performance Chips (HotChips). 2019
- Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture International Symposium on Microarchitecture (MICRO). 2019
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Timeloop: A Systematic Approach to DNN Accelerator Evaluation
IEEE. 2019: 304–15
View details for DOI 10.1109/ISPASS.2019.00042
View details for Web of Science ID 000470201600034
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An Energy-Scalable Accelerator for Blind Image Deblurring
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. 2017: 1849–62
View details for DOI 10.1109/JSSC.2017.2682842
View details for Web of Science ID 000404301300012
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A 0.6V 8mW 3D Vision Processor for a Navigation Device for the Visually Impaired
IEEE. 2016: 416–U584
View details for Web of Science ID 000382151400172
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An Energy-Scalable Accelerator for Blind Image Deblurring
IEEE. 2016: 113–16
View details for Web of Science ID 000386656300026
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Reconfigurable Processor for Energy-Efficient Computational Photography
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. 2013: 2908–19
View details for DOI 10.1109/JSSC.2013.2282614
View details for Web of Science ID 000326265100030
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Reconfigurable Processor for Energy-Scalable Computational Photography
IEEE. 2013: 164–U972
View details for Web of Science ID 000366612300065