
Priyanka Raina
Assistant Professor of Electrical Engineering and, by courtesy, of Computer Science
Bio
Priyanka Raina is an Assistant Professor in Electrical Engineering at Stanford University. Previously, she was a Visiting Research Scientist in the Architecture Research Group at NVIDIA Corporation. She received her Ph.D. degree in 2018 and S.M. degree in 2013 in Electrical Engineering and Computer Science from MIT and her B.Tech. degree in Electrical Engineering from Indian Institute of Technology (IIT) Delhi in 2011. Priyanka’s current research interests are designing energy-efficient and high-performance circuits and systems for image, vision and machine learning applications on mobile devices, integrating emerging non volatile memory technologies in accelerator architectures, and creating frameworks for improving hardware/software system design productivity.
Academic Appointments
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Assistant Professor, Electrical Engineering
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Assistant Professor (By courtesy), Computer Science
Honors & Awards
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Hellman Fellow, Stanford (2019)
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Best Young Scientist Paper Award, ESSCIRC 2016 (2017)
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ISSCC Student Research Preview Award, ISSCC 2016 (2017)
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Bimla Jain Medal, IIT Delhi (2011)
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Institute Silver Medal, IIT Delhi (2011)
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Gold Medal at Indian National Chemistry Olympiad, InChO (2007)
Professional Education
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Ph.D., Massachusetts Institute of Technology (MIT), Electrical Engineering and Computer Science (2018)
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S.M., Massachusetts Institute of Technology (MIT), Electrical Engineering and Computer Science (2013)
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B.Tech., Indian Institute of Technology (IIT) Delhi, Electrical Engineering (2011)
Current Research and Scholarly Interests
For Priyanka's research please visit her group research page at https://stanfordaccelerate.github.io
2020-21 Courses
- Design Projects in VLSI Systems I
EE 272A (Win) - Design Projects in VLSI Systems II
EE 272B (Spr) - Emerging Non-Volatile Memory Devices and Circuit Design
EE 309B (Win) - Semiconductor Memory Devices and Circuit Design
EE 309A (Aut) -
Independent Studies (16)
- Computer Laboratory
CS 393 (Spr, Sum) - Curricular Practical Training
CS 390A (Spr, Sum) - Curricular Practical Training
CS 390B (Spr, Sum) - Curricular Practical Training
CS 390C (Sum) - Independent Database Project
CS 395 (Spr, Sum) - Independent Project
CS 399 (Spr, Sum) - Independent Project
CS 399P (Spr, Sum) - Independent Work
CS 199 (Spr, Sum) - Independent Work
CS 199P (Spr, Sum) - Master's Thesis and Thesis Research
EE 300 (Aut, Win, Spr, Sum) - Programming Service Project
CS 192 (Sum) - Senior Project
CS 191 (Spr, Sum) - Special Studies and Reports in Electrical Engineering
EE 391 (Aut, Win, Spr, Sum) - Special Studies or Projects in Electrical Engineering
EE 390 (Aut, Win, Spr, Sum) - Supervised Undergraduate Research
CS 195 (Spr, Sum) - Writing Intensive Senior Project (WIM)
CS 191W (Spr)
- Computer Laboratory
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Prior Year Courses
2019-20 Courses
- Design Projects in VLSI Systems
EE 272 (Win) - Introduction to VLSI Systems
EE 271 (Aut)
2018-19 Courses
- Design Projects in VLSI Systems
EE 272 (Win) - Introduction to VLSI Systems
EE 271 (Aut)
- Design Projects in VLSI Systems
Stanford Advisees
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Doctoral Dissertation Reader (AC)
Nikhil Bhagdikar, Alex Carsello, Rohan Doshi, Massimo Giordano, Sung-Jin Kim, Taeyoung Kong, Haitong Li, Qiaoyi(Joey) Liu, Zachary Myers, Ankita Nayak, Gedeon Nyengele, Alex Rucker, Kavya Sreedhar, Maxwell Strange, Daniel Villamizar, Weier Wan, Tian Zhao -
Doctoral Dissertation Advisor (AC)
Kathleen Feng, Akash Levy -
Master's Program Advisor
George Klimiashvili, Namit Mishra, Sneha Pendharkar, Elias Stein, Xinhui Zhao -
Doctoral (Program)
Po-Han Chen, Nikhil Poole, Khushal Sethi
All Publications
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A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm
IEEE JOURNAL OF SOLID-STATE CIRCUITS
2020; 55 (4): 920–32
View details for DOI 10.1109/JSSC.2019.2960488
View details for Web of Science ID 000522446300009
- A-QED Verification of Hardware Accelerators Design Automation Conference (DAC). 2020
- Monte Carlo Simulation of a Three-Terminal RRAM with Applications to Neuromorphic Computing International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) 2020
- A 74TMACS/W CMOS-ReRAM Neurosynaptic Core with Dynamically Reconfigurable Dataflow and In-Situ Transposable Weights for Probabilistic Graphical Models International Solid-State Circuits Conference (ISSCC). 2020
- A Framework for Adding Low-Overhead, Fine-Grained Power Domains to CGRAs Design, Automation and Test in Europe Conference (DATE). 2020
- Using Halide’s Scheduling Language to Analyze DNN Accelerators International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS). 2020
- Automating Vitiligo Skin Lesion Segmentation Using Convolutional Neural Networks IEEE International Symposium on Biomedical Imaging (ISBI). 2020
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A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm
IEEE. 2019: C300–C301
View details for Web of Science ID 000531736500102
- A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm Symposium on VLSI Circuits (VLSI). 2019
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MAGNet: A Modular Accelerator Generator for Neural Networks
IEEE. 2019
View details for Web of Science ID 000524676400085
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Neuro-inspired computing with emerging memories: where device physics meets learning algorithms
SPIE-INT SOC OPTICAL ENGINEERING. 2019
View details for DOI 10.1117/12.2529916
View details for Web of Science ID 000511161100014
- A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator Designed with a High-Productivity VLSI Methodology Hot Chips: A Symposium on High Performance Chips (HotChips). 2019
- Creating An Agile Hardware Flow Hot Chips: A Symposium on High Performance Chips (HotChips). 2019
- Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture International Symposium on Microarchitecture (MICRO). 2019
- MAGNet: A Modular Accelerator Generator for Neural Networks International Conference On Computer Aided Design (ICCAD). 2019
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Timeloop: A Systematic Approach to DNN Accelerator Evaluation
IEEE. 2019: 304–15
View details for DOI 10.1109/ISPASS.2019.00042
View details for Web of Science ID 000470201600034
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An Energy-Scalable Accelerator for Blind Image Deblurring
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. 2017: 1849–62
View details for DOI 10.1109/JSSC.2017.2682842
View details for Web of Science ID 000404301300012
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A 0.6V 8mW 3D Vision Processor for a Navigation Device for the Visually Impaired
IEEE. 2016: 416–U584
View details for Web of Science ID 000382151400172
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An Energy-Scalable Accelerator for Blind Image Deblurring
IEEE. 2016: 113–16
View details for Web of Science ID 000386656300026
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Reconfigurable Processor for Energy-Efficient Computational Photography
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. 2013: 2908–19
View details for DOI 10.1109/JSSC.2013.2282614
View details for Web of Science ID 000326265100030
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Reconfigurable Processor for Energy-Scalable Computational Photography
IEEE. 2013: 164–U972
View details for Web of Science ID 000366612300065